In this paper, a fixed-point quantization noise estimator aiming at Digital Signal Processing (DSP) algorithms is presented. The estimator enables significant reduction in the computation time required to perform complex word-length optimizations while providing a high accuracy. Affine Arithmetic (AA) is used to provide a Signal-to-Quantization Noise-Ratio (SQNR) estimation for differentiable non-linear algorithms with and without feedbacks. The estimation is based on the parameterization of the statistical properties of the noise at the output of fixed-point algorithms. This parameterization allows to relate the fixed-point formats of the signals with the output noise distribution by means of fast matrix operations. Thus, a fast estimation is achieved and the word-length optimization computation time is significantly reduced. The estimator is tested using a subset of non-linear algorithms such as vector operations, power computation IIR filter, adaptive filters, and channel equalizers. The Word-length optimization computation time is boosted by three orders of magnitude while keeping the average estimation error down to 6% for most cases.

Traditional approaches for fixed-point characterization are based on long simulations or additive noise models that do not show the nonlinear behavior of the quantization operations in reasonable time. In this paper, a novel interval-based approach that provides both tighter and faster results than the existing approaches is presented. It is based on a nonlinear adaptation of the quantization operations of affine arithmetic (AA). The results obtained with this method are compared to other published interval-based approaches, and the problem of interval oversizing is discussed in detail. Simulations show that: 1) the propagation techniques are not well suited to characterize the quantized linear systems with feedback loops; 2) the AA provides oversized bounds in this type of systems; and 3) the proposed adaptation does not provide guaranteed bounds as in the traditional interval-based computations, but it provides tighter estimates of the evolution in time of the ranges of the fixed-point signals and better runtime than the existing interval-based characterization techniques.

In this paper we address the high-level synthesis of multiple word-length DSP algorithms over programmable devices (FPGAs). Previous approaches tend to simplify the set of resources, thus alleviating the complexity of the high-level synthesis, but leading to non-optimal solutions. Here, we present a high-level synthesis framework that overcomes these limitations by means of considering: (i) both logic-based and embedded multipliers, (ii) both constant and generic multipliers and (iii) variable latency resources. A simulated annealing based approach for the combined scheduling, resource allocation and binding tasks is presented. When compared to previous approaches, area improvements of up to 60% are reported

One of the main challenges in bioinformatics nowadays is to create a framework to compare efficiently new DNA sequence information to large existing databases. Optimal methods, such as the Smith-Waterman algorithm, provides more sensitive results than heuristic algorithms such as FASTA and BLAST, with the drawback of increased computational complexity. FPGAs implementations of Smith-Waterman exploit the intrinsic parallelism in the algorithm and achieve computation time reductions of several orders of magnitude. In this paper we present an implementation of a Smith-Waterman linear systolic array that doubles throughput of existing ones with a minimum increase of area. The processing speed improvement is achieved by means of assigning the computation of four edit distances to a single systolic cell. Implementation results on Xilinx devices XC2V6000 and XCV1000E are reported. An array that processes 8000-nucleotid DNA sequences achieves 3200 BCUPS operating at 200 Mhz on a XC2V6000-5 device.