A key requirement for silicon debug and continuous monitoring is to detect and isolate functional failures that escape structural tests. This paper will use the case study of an embedded trace system developed based on the Efficient Trace for RISV-V (E-Trace) specification to highlight the central position it occupies in building a comprehensive SLM solution. Results on some industrial benchmarks demonstrate the efficiency of this approach.

A key requirement for silicon debug and continuous monitoring is to detect and isolate functional failures that escape structural tests. This paper will use the case study of an embedded trace system developed based on the Efficient Trace for RISV-V (E-Trace) specification to highlight the central position it occupies in building a comprehensive SLM solution. Results on some industrial benchmarks demonstrate the efficiency of this approach.

Automotive designs demand the highest possible test coverage for safety and reliability. One approach is to add as many test points as possible to the circuit. To avoid increasing the die size, test point sharing can be used to maximize the number of test point nodes while using fewer test point flops. While test point sharing reduces area overhead, extra wiring is needed leading to congestion which again limits the number of test points that can be added. This paper presents a method to reduce wiring congestion when sharing a large number of test points. Our method also reduces the impact sharing can have on fault coverage. Test point sharing is optimized in the physical implementation tool to reduce wiring and congestion leading to improvements in PPA. Results from five automotive designs show up to a 67% reduction in wiring for test point logic, an average 24% reduction in congestion, and improvements in PPA. Alternatively, one can increase the number of test points and achieve a 1.62% improvement in LBIST coverage without introducing additional congestion or impacting PPA.

Test Compression and logic built-in self-test (LBIST) are proven DFT solutions to address the quality and safety requirements of automotive electronics but their high impact to backend physical implementation can be a huge barrier to successful adoption. Unified compression is a new approach that unifies scan compression and LBIST. It leverages recent innovations in Physical DFT Synthesis to solve routing congestion and area issues from traditional discrete approaches and paves the road to high-quality testing. Area savings of 35-47%, and scan wirelength savings of 63-77% for the same scan chain length can be achieved while reducing test application time by 50%.

Multiple defects are prevalent in early stages of yield improvement for a new technology. When a logic diagnosis procedure is applied to a faulty unit that contains a multiple defect, it sometimes produces a large set of candidate faults. Such a set includes extra candidates that do not match the defect present in the faulty unit. An earlier study indicates that a logic diagnosis procedure may prefer certain faults as candidate faults, causing them to appear as extra candidates in many sets of candidate faults. This points to the possibility of using a small number of observation points to eliminate extra candidates that appear often. This paper takes advantage of this observation to improve the quality of diagnosis by placing observation points. Experimental results for benchmark circuits demonstrate the effectiveness of observation points in reducing large sets of candidate faults.

Test Compression ratios are currently stalled at 100-200X. A new 2-dimensional physically-aware sequential Compressor-Decompressor design addresses the severe wiring congestion as well as the test coverage droop and pattern spike at the highest compression ratios. Results on some commonly used industrial designs shows a 2X reduction in routing overhead and congestion associated with Test Compression logic. The target test coverage is maintained while achieving up to 3.7X reduction in test data volume and test application time beyond the conventional methods.

Inter-die connections in 2.5D-and 3D-stacked ICs require at-speed testing as their dynamic performance is crucial to the performance of the stack as a whole. In order to test at mission-mode speed and benefit from the already existing clock distribution network, our at-speed test approach for inter-die connections targets the entire register-to-register path that includes the interconnect. This forces the launching and capturing wrapper cells to be shared with functional flip-flops. In some designs, this unavoidably leads to some 'shore logic': a, typically small, amount of combinational logic outside the die's wrapper boundary register. This paper describes how we have adapted a previously developed 3D-DfT architecture and corresponding EDA tool flows to support at-speed interconnect testing, also in the presence of such 'shore logic'. The adaptations affect the DfT insertion of wrapper cells, the boundary model extraction, and the interconnect test pattern generation.

As chip design sizes continue to increase and they contain multiple instances of large and small cores, there is a need for a chip test architecture that allows efficient chip-level tests to be created while also reducing the memory and CPU time needed to create the tests. We define a hierarchical and core-based architecture for generating tests for cores and migrating them to the chip. This architecture allows testing multiple instances of the same core for the same cost as testing a single instance. The architecture also allows testing multiple instances of different cores as well. Memory use is kept low by generating tests for cores out of context and migrating them to the chip. We never have to build a full gate-level chip ATPG model. We show results of pattern count reduction possible when targeting multiple cores simultaneously.

Low-power testing has become a need for modern designs due to rapid increasing of power density with further shrinking of feature size into nanoscale designs. In spite of low-power design efforts and low-power ATPG adopted in common test flows, excessive power dissipation and instant peak current cannot be necessarily avoided during test application. There is a need for fast peak power detection for test vectors. The test industry lacks such efficient solution. In this work, we propose a fast test power analysis methodology. By reading and processing layout data and other supporting files such as parasitic files, the proposed analysis engine performs a simplified power grid analysis with layout partition and provides following power results for each test cycle: switching activity, absolute power, hot spot contour map, absolute current estimation on power pads. The proposed flow was verified on industry designs and proved to be very efficient than using commercial power sign-off solutions for test power analysis.

Three-dimensional stacked integrated circuits (3D-SICs) implemented with through-silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller, and more energy-efficient chips. As all micro-electronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. Previously, we defined, implemented, and automated a 3D-DfT (Design-for-Test) architecture that provides modular test access for 3D-SICs containing monolithic logic dies in a single-tower stack. However, the logic dies comprising a 3D-SIC typically are complex System-on-Chip (SoC) designs that include embedded intellectual property (IP) cores, wrapped for modular test. Also, multi-tower 3D-SICs have started to emerge. In this paper, our existing 3D-DfT architecture is extended with support for wrapped embedded IP cores and multi-tower stacks and its implementation is automated with industrial electronic design automation (EDA) tools.

IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.

Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.

Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.

Using Through-Silicon Vias (TSVs) in three-dimensional stacked ICs (3D-SICs) has benefits in terms of interconnect density, performance, and power dissipation. For 3D-SICs, an extension of the Design-for-Test architecture based on die-level wrappers is required to enable pre-bond die testing as well as modular post-bond die and interconnect testing. This paper presents an approach that automates the insertion of die wrappers. Experimental results show that the user can perform automated 3D-DfT insertion through existing EDA tools with negligible area costs, and verify the proposed DfT by test pattern generation and simulation.

At-speed testing with functional speed clocks is often done using On-Product Clock Generation (OPCG). When test compression logic is also embedded within the circuit's DFT architecture, the loading of the OPCG programming bits can impact test compression results. We present an approach to the use of OPCG that enables high-speed testing and is compatible with test compression. It also enables the use of tests that pulse multiple domains to further reduce test time and data volume. It also supports generation of inter-domain and static ATPG tests. We present results on four designs; one design shows an over 35% reduction in patterns due to use of multiple clock domains per test. An additional 10+% savings is possible using side-scan to load the OPCG programming registers.

Designs using advanced low power techniques like multi-supply multi-voltage and power shutoff bring with them a new set of challenges that manufacturing test must deal with carefully. These designs have low power components-isolation cells, retention flops, level shifters, power switches, etc.,-that must be tested not only structurally but also addressing their behavior across multiple power modes. This paper describes the challenges in testing the key low power components and proposes novel solutions. The defective behavior of state retention logic is modeled to enable fault grading. ATPG modeling of defective behavior of isolation logic and level shifters is described for designs that support multiple supply voltages and power shutoff. The solutions are supported by experimental results on industrial designs.

Scan-based manufacturing test of low power designs often exceeds the very tight functional constraints on average and instantaneous logic switching. The logic activity during the shift and launch-capture of test pattern data may lead to excessive power consumption and voltage droop. This paper focuses on the management of instantaneous power during the capture phase. By taking advantage of the existing clock gating circuitry and selectively holding the value of some scan flip-flops, switching activity during the capture cycles of a test can be reduced. The effectiveness of this technique is demonstrated on several industrial designs that show up to 30% (55%) reduction in instantaneous (average) capture switching.

As low power designs with multiple switchable power domains become more common, there is a need to ensure that the low power component structures in the design -such as isolation cells, state retention logic, and level shifters - are robustly tested during manufacturing test. This paper describes some of the challenges involved in testing low power components like state retention logic and proposes a novel method for testing them by cycling through the power modes of the chip to test their retention capability.

This paper describes the challenges of testing low-power designs that use the commonly used multi-supply multi-voltage (MSMV) and power shut-off (PSO) design methodology. We describe a novel solution to address the manufacturing test of an MSMV/PSO design by using power-mode specifications to map multiple power modes to their target test modes and enhancing the DFT and ATPG methodology to enable a comprehensive test methodology. We provide experimental results and future directions for power-aware test.

This paper explores the savings in power achieved using an I/O gating and Reduced Pin Count Test (RPCT) technique during manufacturing test. Since I/O pads consume significant power, preventing them from toggling during test will bring about a corresponding savings in power. The paper describes a fully automated RPCT methodology for low power that includes insertion of the RPCT and I/O gating logic and test generation. Based on simulation of the ATPG patterns, we show that the power consumed during scan test can be reduced significantly.

This paper describes an automated methodology to insert IEEE 1149.6 boundary scan in a production ASIC environment. The methodology includes updating the ASIC library to support the new test receiver component, updating the TAP controller logic and boundary cells, and finally providing support for embedded high speed I/O logic. Results from several industrial designs and example circuits are shown. These examples include multi-GHz serial I/O such as those used with serial ATA and PCI-Express

As the industry fabricates devices with more on-chip circuitry using complex, advanced process technologies, the challenge to achieve satisfactory yield becomes more daunting (Madge, 2005). Leading-edge nanometer designs can be sensitive to inherent irregularity in sub-wavelength photolithography and variability in parametric characteristics often found in nanometer manufacturing environments. These factors often result in devices being fabricated with intermittent electrical performance problems. These types of systemic interactions (process-design) are the major factor in manufacturing yield loss in nanometer technology nodes. Failure diagnostics is being asked to identify these systemic defects, preferably during early product development, and provide enough information so that each defect is understood and can be addressed. This paper presents a case study, which empirically examines the challenges of achieving high yield during the early stage of wafer production with an examination of yield loss mechanisms. A proven methodology and model (volume yield diagnostics) for an economic justification enabling the timely identification of yield loss is discussed along with quick process methodology and analysis results based on real manufacturing data

This presentation describes a scalable on-chip architecture for test data compression that provides a flexible means to specify, compile, verify, generate tests and diagnose chips with the embedded building blocks described above. The design flow, options and trade-offs that address the specific requirements of different segments of the user community will be presented with some case studies and results

As SoC feature sizes are moving down to the nanometer range there is an increasing need to develop high quality, cost-effective and sensitive tests for nanometer devices. Many of the newer defects like resistive vias and bridges exhibit defective timing behavior, and require the usage of the transition fault model and sophisticated control of the launch-to-capture timings to the equivalent of system speeds.

Testing at-speed delay defects is difficult on a speed constrained low cost tester. This paper describes the use of a clock chopper based onproduct clocking circuitry and interfaces to delay ATPG to achieve reliable test patterns. We also describe the test compression methods used to address the problem of increased test data volume due to delay tests. Data is presented on several industrial circuits to demonstrate the effectiveness of these DFT methods on nanometer designs. Our results show that a seamless combination of atspeed delay testing with compression can help to test the nanometer defects at a very competitive cost.

The effectiveness of on-product test compression methods is degraded by the capture of unknown logic states ("X-states") by the scan elements. This work describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs. It also discusses various aspects of the channel masking hardware and the synthesis and validation methodology to support its use in a typical design flow. Results are presented to show its effectiveness on some large industrial designs.

This work describes an economic and return-on-investment (RoI) model for a test methodology that ensures product quality for logic devices that are in the 130 nm technology node and below. We describe the key components of the nanometer test methodology (NTM) and how it drives the model. In addition to ensuring product quality we address the cost of test and time to volume and how both factors can be improved. Examples from realistic scenarios are provided to illustrate the net savings from the proposed NTM using this model.

System-on-Chip (SOC) designs use numerous and diverse embedded cores and memories. Very high system reliability requirements mandate greater than 99.9% ATPG chip manufacturing test coverage. Logic BIST and memory BIST are increasingly used for high system test coverage with additional constraints that some cores or pockets of user designed logic have to be functionally active during BIST. This paper describes the challenges of a design methodology to handle such SOC designs and the automated solutions that address these problems.

Logic BIST techniques normally focus on testing random logic blocks. If one observes the current design trends for high-performance ASICs, the number and size of embedded memories is increasing rapidly. This presents several challenges to the design and integration of at-speed logic BIST when the number of bits of embedded memories is a large percentage of the total number of storage bits in the design. This paper will discuss some novel techniques to address the DFT and clocking considerations in designs with extensive usage of embedded memories.

The maturity of high-level synthesis systems has enabled the use of design-for-test (DFT) methods early in the design phase. Early DFT synthesis ensures that the processing and transformation of multibit register variables, clock-gating, and initialization specifications are consistent with the high-level specification. Functional and test logic can be optimized in the same pass without the need for an iterative timing closure procedure. It allows designers to keep a single design source while synthesizing and mapping the logic to multiple technology libraries. This paper addresses the implementation of an early DFT synthesis system and presents experimental results to compare the early mode insertion approach with a late-mode approach.

The widespread adoption of hardware description languages (HDLs) and structured design for testability (DFT) methods in ASIC design flows has led to an increasing emphasis on technology independence. Many DFT techniques such as boundary scan design, I/O sharing between test and functional ports. I/O wrap testing etc., rely on an accurate I/O specification. This paper describes some novel technology independent solutions to the problem of I/O cell specification and synthesis of DFT structures that involve I/O cell transformations. The solution speed up behavioral simulation of the HDL specification while also providing accurate I/O models for test synthesis.

Recent studies show that a stuck-at test applied at the operational speed of the circuit identifies more defective chips than a test having the same fault coverage but applied at a lower speed. Design-for-testability approaches based on full scan, partial scan, or silicon-based solutions such as CrossCheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed. In this work, we investigate various design-for-testability (DFT) techniques for sequential circuits that permit at-speed application of tests while providing for very high fault coverage. The method involves parallel loading of flip-flops in test mode for enhanced controllability combined with probe point insertion for enhanced observability. Fault coverage and ATG effectiveness improved to greater than 96% and 99.7%, respectively, for the ISCAS89 sequential benchmark circuits studied when these nonscan DFT techniques were used. The average area overhead for the nonscan DFT enhancements was 9.9% for standard cell implementations of three circuits synthesized from high-level descriptions, compared to 20.2% for full scan. ATG effectiveness improved to greater than 99.3% for all three circuits with the nonscan DFT enhancements.>

The increasing use of hardware description languages (HDL's) in VLSI design and the emergence of high-level test generation programs has led to an interesting problem. There is a need for design for testability (DFT) techniques that can be applied early in the design phase to improve the effectiveness of ATPG programs on hard-to-test circuits. By an early identification of hard-to-test areas of a circuit, testability can be inserted prior to logic synthesis. In this paper, we first present a comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits. Based on an evaluation of the results, we propose techniques to automatically extract information from the high-level circuit description that could improve the performance of both ATPG tools. An automatic DFT tool that utilizes VHDL descriptions of the circuit to make an intelligent selection of flip-flops for partial scan is then described. Results on six hard-to-test circuits show that very high fault coverages can be obtained by both a gate-level and a high-level test generator on these circuits after scan. With this detailed study we demonstrate that a DFT tool can make a more efficient and effective selection of partial scan flip-flops by exploiting the high-level circuit information. It can accurately predict the hard-to-test areas of a circuit. Significant improvements in fault coverage and ATPG efficiency, and speedups in ATPG time, can be obtained by a gate-level and a high-level test generator after high-level scan selection.>

Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-for-testability approaches based on full scan, partial scan or silicon-based solutions such as Crosscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed of the circuit. In this paper, a design-for-test method that permits at-speed testing is introduced. The method is based on probe point insertion for improved observability, and it requires enhancements to an existing sequential circuit fault simulator. Faults that can be activated but not detected at existing primary outputs are targeted. A minimal set of probe points is selected to detect these faults, and the probe points are compressed to one or two output pins using exclusive-OR trees. The issue of aliasing of fault effects is addressed. Improvements in fault coverage were made for all 17 of the ISCAS89 sequential benchmark circuits studied. Fault coverages between 99% and 100% were obtained for seven circuits, and 100% ATG effectiveness was achieved on all but two circuits.>

Article Free Access Share on Non-scan design-for-testability techniques for sequential circuits Authors: Vivek Chickermane View Profile , Elizabeth M. Rudnick View Profile , Prithviraj Banerjee View Profile , Janak H. Patel View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 236–241https://doi.org/10.1145/157485.164686Published:01 July 1993Publication History 49citation329DownloadsMetricsTotal Citations49Total Downloads329Last 12 Months43Last 6 weeks19 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

When a logic module is embedded in a large circuit, the architectural level functional constraints usually cause don't cares at the interface of this module. If the logic of the module is not synthesized using these don't cares, then redundancy may exist making the circuit very hard to test. In this paper, architectural level circuit structural and instruction behavioral information is exploited to analyze functional constraints and extract don't cares. The don't cares are used to optimize the logic of the module and to remove many redundant faults.>

A comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits is presented. Based on the examination of the results DFT techniques that use high-level circuit information are proposed. The results obtained after partial scan selection by a high-level DFT tool are compared with results obtained by a gate-level partial scan tool. This detailed comparative study demonstrates that a DFT tool can make a more effective selection of partial scan flip-flops by exploiting the high-level circuit information, and by accurately predicting the hard-to-test areas of a circuit.>

This paper presents techniques to utilize high-level structural, functional and register-transjer information to perform design-for-testability (DFT}. An automatic tool which utilizes VHDL descriptions of the datapath and control unit of sequential circuits to make an intelligent selection of scan pip-pops is described. This DFT tool ADEPT can make design enhancements early in the design phase. Results on four hard-to-test circuits show that very high fault coverages can be achieved by both a gate-level and a high-level test generator on these circuits after scan selection. Fewer scan jlip-flops were chosen as compared to a gate-level partial scan selection.

Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-for-testability approaches based on full scan, partial scan, or silicon-based solutions like Crosscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed. In this paper, a design-for-test method which permits at-speed testing is introduced. The method is based on probe point insertion for improved observability. Improvements in fault coverage were made for all 16 of the ISCAS-80 benchmark circuits studied. Fault coverages between 99% and 100% were obtained for six circuits, and 100% ATG efficiency achieved on all but two circuits.>

The authors propose a fault oriented partial scan design methodology to be performed as a sequel to test generation. Given the cost of converting each flip-flop to a scanned flip-flop and an overall bound on the cost of the scan design, the program OPUS-2 selects a set of flip-flops which are most likely to improve the quality of test generation. The expected improvement in testability is modeled by profit functions quantifying the reduction in weighted cycles, or the reduction in SCOAP values at hard-to-detect fault sites. Experiments performed on ISCAS89 sequential benchmark circuits show that, by analytically selecting only 10-20% of the flip-flops, the circuits can be tested to the same level of quality as a fully scanned circuit. The advantages of the proposed method are that the highest possible fault coverage can be achieved while limiting the cost of scan to a user-specified limit.>

The problem of selecting flip-flops for inclusion into a partial scan path is formulated as an optimization problem. Scan flip-flops result in layout and delay overheads. Hence, scan flip-flops have to be chosen such that the net cost associated with these overheads is bounded by some user-specified limit. The problem then reduces to choosing a set of flip-flops which gives the best improvement in testability, while keeping the cost bounded. Cost functions are proposed for a standard cell design approach to model the effects of the overheads. Profit functions for three different testability criteria are proposed, and the optimization methodology for each is discussed. The optimization process is modeled on the lines of the 0/1 knapsack problem. Results for some medium-sized sequential circuits which show a very large improvement in fault coverage obtained by optimally selecting a small fraction of the flip-flops in the circuit are presented.>