This article addresses the issue of output synchronization via intermittent dynamic event-triggered sampled-data (IDETSD) security control of reaction-diffusion neural networks (RDNNs) under spatially local averaged measurements (SLAMs) subject to both delays and random deception attacks, where a Bernoulli distribution is utilized to describe whether channels suffer from the cyberattacks. An IDETSD security control method under SLAMs and random deception attacks is presented to achieve the output synchronization of delayed RDNNs. Compared with time-triggered intermittent sampled-data (SD) control strategies, a dynamic event-triggered (ET) mechanism to more effectively mitigate the impact induced by random deception attacks that intentionally tamper with the state transmission signals from sensors to controllers is introduced in this article. Moreover, new output synchronization criteria are established by applying an ET-dependent switched Lyapunov functional (LF) and inequality techniques. Then, the desired IDETSD controller is obtained by solving linear matrix inequalities (LMIs). To validate the efficacy of the proposed approach, simulation outcomes from two numerical studies are presented.

We study the synchronization of delayed reaction-diffusion neural networks (RDNNs) with Neumann boundary conditions, considering both distributed and discrete delays. Particularly, boundary sampled-data (SD) control is proposed to synchronize delayed RDNNs. In the proposed synchronization strategy, boundary SD control is based on boundary and distributed SD measurements. Based on the Lyapunov stability theory and inequality techniques, some synchronization criteria via the boundary SD control are proposed for delayed RDNNs. The boundary SD control gains are obtained by solving the conditions with linear matrix inequalities. Finally, a numerical example is presented to demonstrate the feasibility and effectiveness of the proposed method.

We introduce an Outlier-Efficient Modern Hopfield Model (termed OutEffHop) and use it to address the outlier inefficiency problem of training gigantic transformer-based models. Our main contribution is a novel associative memory model facilitating outlier-efficient associative memory retrievals. Interestingly, this memory model manifests a model-based interpretation of an outlier-efficient attention mechanism (Softmax_1): it is an approximation of the memory retrieval process of OutEffHop. Methodologically, this allows us to introduce novel outlier-efficient Hopfield layers as powerful alternatives to traditional attention mechanisms, with superior post-quantization performance. Theoretically, the Outlier-Efficient Modern Hopfield Model retains and improves the desirable properties of standard modern Hopfield models, including fixed point convergence and exponential storage capacity. Empirically, we demonstrate the efficacy of the proposed model across large-scale transformer-based and Hopfield-based models (including BERT, OPT, ViT, and STanHop-Net), benchmarking against state-of-the-art methods like Clipped_Softmax and Gated_Attention. Notably, OutEffHop achieves an average reduction of 22+% in average kurtosis and 26+% in the maximum infinity norm of model outputs across four models. Code is available at GitHub; future updates are on arXiv.

Spatial transcriptomic (ST) clustering employs spatial and transcription information to group spots spatially coherent and transcriptionally similar together into the same spatial domain. Graph convolution network (GCN) and graph attention network (GAT), fed with spatial coordinates derived adjacency and transcription profile derived feature matrix are often used to solve the problem. Our proposed method STGIC (spatial transcriptomic clustering with graph and image convolution) is designed for techniques with regular lattices on chips. It utilizes an adaptive graph convolution (AGC) to get high quality pseudo-labels and then resorts to dilated convolution framework (DCF) for virtual image converted from gene expression information and spatial coordinates of spots. The dilation rates and kernel sizes are set appropriately and updating of weight values in the kernels is made to be subject to the spatial distance from the position of corresponding elements to kernel centers so that feature extraction of each spot is better guided by spatial distance to neighbor spots. Self-supervision realized by Kullback-Leibler (KL) divergence, spatial continuity loss and cross entropy calculated among spots with high confidence pseudo-labels make up the training objective of DCF. STGIC attains state-of-the-art (SOTA) clustering performance on the benchmark dataset of 10x Visium human dorsolateral prefrontal cortex (DLPFC). Besides, it's capable of depicting fine structures of other tissues from other species as well as guiding the identification of marker genes. Also, STGIC is expandable to Stereo-seq data with high spatial resolution.

Stacked HfOxbased vertical RRAM with interface engineering for 3D cross-point architecture is fabricated using a cost-effective fabrication process. The excellent performances such as low reset current, fast switching speed, high switching endurance and disturbance immunity, good retention and self-selectivity are demonstrated in the fabricated HfOxbased vertical RRAM devices. The scaling limit and the functionality along with a viable write/read scheme of the presented vertical RRAM are investigated. The experiments show that the pillar electrode thickness and the plane electrode thickness of the vertical RRAM can be scaled down to 3nm and 5nm without significant performance degradation, respectively.

Design guidelines were proposed to evaluate and optimize the 3D RRAM cross-point architecture by a full-size 3D circuit simulation in SPICE. The performance metrics that were evaluated include the write/read margin, access latency, energy consumption per programming, and the density per bit. Different 3D cross-point architecture including the horizontally stacked or the vertically stacked structure were compared in terms of these metrics, revealing the advantages of the vertical RRAM structure. Then the scaling trend of the vertical RRAM based 3D array with respect to the scaling of lateral feature size, vertical electrode thickness and vertical isolation layer thickness were evaluated. The design parameters that affect the scaling trend include the metal interconnect resistance, RRAM on-state cell resistance (or the nonlinearity of the I-V). The design trade-offs are discussed considering those parameters constraints.

Low-power applications, such as sensing, are becoming increasingly important and demanding in terms of minimizing energy consumption, driving the search for new and innovative interface architectures and technologies. Carbon Nanotube FETs (CNFETs) are excellent candidates for further energy reduction, as CNFET-based digital circuits are projected to potentially achieve an order of magnitude improvement in energy-delay product at highly scaled technology nodes. This paper presents an overview of the first demonstration of a complete sub-system, a sensor interface circuit, implemented entirely using CNFETs. The demonstrated sub-system is an all-digital capacitive sensor to digital converter. The CNFET sensor interface is demonstrated by using the CNFET circuitry to interface with a sensor used to control a handshaking robot.

Carbon Nanotube Field-Effect Transistors (CNFETs) are excellent candidates for building highly energy-efficient digital systems. However, imperfections inherent in carbon nanotubes (CNTs) pose significant hurdles to realizing practical CNFET circuits. In order to achieve CNFET VLSI systems in the presence of these inherent imperfections, careful orchestration of design and processing is required: from device processing and circuit integration, all the way to large-scale system design and optimization. In this paper, we summarize the key ideas that enabled the first experimental demonstration of CNFET arithmetic and storage elements. We also present an overview of a probabilistic framework to analyze the impact of various CNFET circuit design techniques and CNT processing options on system-level energy and delay metrics. We demonstrate how this framework can be used to improve the energy-delay-product (EDP) of CNFET-based digital systems.

Carbon Nanotube Field-Effect Transistors (CNFETs) are excellent candidates for designing highly energy-efficient future digital systems. However, carbon nanotubes (CNTs) are inherently highly subject to imperfections that pose major obstacles to robust CNFET digital VLSI. This paper summarizes commonly raised questions and concerns about CNFET technology through a series of frequently asked questions. The specific questions addressed in this paper are motivated by recent advances in the field since the publication of our earlier paper on frequently asked questions in the Proceedings of the 2009 Design Automation Conference.

It is well-known that in order to enhance system performance, channel estimation in coherent OFDM systems is necessary and crucial. In practice, lots of coherent OFDM systems transmit pilot symbols over some of the subcarriers for the purpose of estimating channel attenuation, and also insert cyclic prefixto avoid inter-carrier and inter-symbol interference. In this paper, a pseudo noise (PN) sequence combined with zero padding is inserted in the postfix of each OFDM symbol to estimate the channel impulse response. The major advantage of the proposed channel estimation techniques is the ability of estimating and, then, tracking the channel variations. These proposed channel estimation algorithms include least-square technique with decision-directed data-assistance (DDLS), least-square (LS) estimation and maximum-likelihood (ML) scheme with different observation windows. The proposed techniques are thus very appropriately used in presence of high mobility with large Doppler spreads. Some comparative simulations are given to illustrate the superior performance of the proposed channel estimation techniques.