This paper presents the design of a fully flexible temperature sensor for wearable applications. The sensor is implemented using the newly available flexible integrated electronic circuit (Flex-IC) technology from Pragmatic Semiconductor [1]. To address the design challenges due to the limited set of thin film components available in this non-CMOS technology, a counter-based time-to-digital conversion (TDC) technique has been developed, where the pulses provided by a temperature-dependent ring oscillator are gated and counted by a temperature-independent delay cell. The operation of the delay cell relies on the temperature coefficient cancellation of resistive components by a cross-coupled pair. A tunable calibration mechanism is also incorporated in the design to handle the process corners in a temperature range of 32 °C - 42 °C suitable for biological sensing. The presented sensor design exhibits a low time-jitter induced measurement error, with a 0.81 % probability of toggling the least significant bit (LSB) per sample, maintaining 0.1 °C precision and a zero-error range of 6.8 °C, while dissipating a power of 2.5 mW with an acquisition time of 3 ms. The chip layout measures 3.0 mm×3.0 mm with a die thickness of 30 μm. Compared to existing rigid and hybrid systems, the Flex-IC technology opens up opportunities for advancing conformal electronics, particularly for applications requiring continuous monitoring on dynamic body surfaces.

This paper proposes a new curriculum for under-graduate students that teaches chip-level design and assembly for developing a complete, tapeout-ready System-on-Chip (SoC) that includes synthesized digital components, analog/mixed-signal blocks, and IP such as memories and I/O drivers. The course will guide students through the process of synthesizing RTL into layout blocks, floor planning, chip-level routing of components, simulation, verification, and tapeout using a 45 nm public-domain PDK. By the end of the class, students will be capable of designing a complete, verified, and tapeout-ready SoC containing complex digital microcontroller circuitry and analog/mixed-signal front-ends. The course will take students through the steps to design and assemble a chip based on an existing SoC designed at the authors’ university. This will lead to the development of a workforce capable of designing mixed-signal SoC solutions for broader industrial and academic needs.

This work presents a single-chip electronics interface for low power, high count rate gamma ray spectroscopy using a novel current nulling scheme that reduces power consumption to 8.8 mW at a count rate of 30 kcps. The current nulling circuit monitors and subtracts the time-varying PMT anode bias network current that would normally lead to a significant integration error at high count rates. This allows the use of low power, event-driven circuit topologies downstream at higher count rates than would otherwise be supported. With this method, the detection resolution degradation improves from 0.85%70/kcps to 0.02%/kcps and the spectrum shift is reduced from −22bins/kcps to 0.32 bins/kcps.

Electronic skin (e-skin) interface building blocks are presented that are suitable for integration with array-based tactile sensors for prosthetic applications. The first is a low power, low noise capacitive transimpedance amplifier (CTIA) compatible with charge-based polyvinylidene fluoride (PVDF) sensors. The second is a high efficiency RISC-V microcontroller unit (MCU) with a custom, on-chip neural processing unit (NPU) to accelerate gesture recognition tasks. Two test chips have been fabricated using a 65 nm CMOS technology: one for the prototype analog front-end (AFE) including the CTIA, and the other for the MCU and NPU. The AFE consumes 112.5 nW per channel, and the MCU consumes 2.83 mW while running the NPU at 112 MHz.

A standalone radiation detection and identification system is designed and tested which quantizes gamma ray energies with a scintillator, photomultiplier tube, and a custom multichannel analyzer chip to construct a gamma ray energy histogram. The histogram is used as the input to a fast, low memory, versatile neural network that runs in software on a microcontroller and identifies in real time which radioisotopes are present in the radiation source. The neural network accurately identifies the radioisotopes for which it has been trained, running in under 91.4 ms, consuming less than 6.2 kB of memory, and expending 274 μJ of energy each time it is executed.

A low-power, single-chip electronic skin interface is presented. Its small size and reduced battery requirements are ideal for advanced prosthetic limbs that utilize electronic skin to provide their user tactile feedback. The architecture consists of multiple charge-sensitive analog front ends (AFEs) interfaced to a central, 16-bit microcontroller core which is capable of processing the sensory information in real-time. Event-driven operation allows the chip to monitor all input channels while idle and consuming minimal energy. A test chip has been fabricated in a 0.13 μm CMOS technology and implements 13 AFE channels. Its functionality is demonstrated by interfacing the chip to a prototype electronic skin based on polyvinylidene fluoride (PVDF) piezoelectric sensors. Signals from the sensors are captured by the presented chip and processed to calculate the corresponding charge. This is accomplished by programming the microcontroller with a custom software algorithm implemented in C, granting the system the flexibility to interface to different types of sensors. The single-chip electronic skin system consumes 7.0 μW per channel and 76.5 μW in the example application, making it suitable for use with battery-powered prosthetics.

This paper presents the design and test results of a low-power radiation detection system. When paired with a scintillation-based detector, the design forms a compact, portable unit suitable for use in long-duration radiation monitoring applications. The system consists of two distinct modules. The first is a low-power detector power supply (DPS) used to generate multiple high voltages necessary to bias a photomultiplier tube (PMT), which is controlled and regulated by a 0.35 μm controller chip. The second is a 0.13 μm low-power multichannel analyzer (MCA) chip with an integrated microcontroller and event-driven charge-sensitive front-ends with 10-bit ADCs used to acquire and analyze the energy spectrum of the radiation. The MCA interfaces with the DPS through a digital interface, allowing it to tune the PMT voltage to compensate for temperature and time variations in the detector. Both modules were fabricated and tested to verify low-power functionality, consuming 2.4 mW when sensing radiation events at 1000 counts/sec (cps).

This work presents a smart camera application of real-time trajectory calculation, utilizing a neighborhood-level parallel processing vision chip to track objects and predict their path of motion. The vision chip contains arrays of pixel elements embedded into neighborhood processors, which are tiled to create a 64×80 resolution vision chip. The high frame rate and processing speed of the vision chip allows for calculation of the object's trajectory before leaving the frame. Algorithm design for the tracking algorithm is discussed and hardware test results for linear and non-linear path predictions are presented. Further considerations in optimizing the algorithm for higher precision and robust trajectory forecasting are discussed.

This paper presents the design and test results of a low-power 10-bit multichannel analyzer (MCA) chip for radiation detection. A low-power and event driven charge sensitive front-end and analog-to-digital converter (ADC) are implemented together with a microcontroller on a single chip. This level of integration leads to a compact MCA that can process and build pulse height spectra when interfaced with a range of scintillator detectors, with the ability to digitally process the spectra using software running as embedded code. The design was fabricated in a 0.13 μm CMOS technology and tested to validate the approaches taken. The measured power consumption of the MCA is below 85 μW while detecting multiple radioisotopes.

This live demonstration features a vision chip based on a neighborhood level parallel processing paradigm. Processors are physically embedded within groups of pixels, complete with memory and algorithmic capabilities controlled by a custom instruction set. This results in a scalable resolution, parallel processing vision chip with flexible programmability that can perform a wide variety of image and video processing tasks. A prototype vision chip has been fabricated in a 0.13μm CMOS technology consisting of an 8×10 array of processors with a 64×80 resolution. The setup demonstrates how the vision chip can execute various parallel processing programs and manipulate image acquisition parameters to match the requirements of a scene in real-time.

This paper presents a novel vision chip architecture based on pixel-neighborhood level parallel processing. The architecture consists of neighborhoods of 8×8 digital pixel sensors, where each group of 8×8 sensors is physically embedded within its own neighborhood processing core on the same focal plane. To that end, a low complexity neighborhood processor architecture along with a general-purpose, 8-bit instruction set has been designed and implemented. This allows program execution to be carried out in parallel on a two-dimensional array of pixel-neighborhood processing cores, allowing for direct scalability in terms of resolution. A prototype vision chip housing an array of 8×10 neighborhoods with a 64×80 resolution has been designed and fabricated in a 0.13 μm fabrication process. The single-chip vision system can be programmed to perform a variety of image and video processing tasks. A number of image processing tasks are presented to demonstrate the functionality of pixel-neighborhood level parallelism.

This paper presents the design of an Analog-to-Information spectral decomposition scheme suitable for parallel low-power analog and mixed-signal VLSI implementation. The novel scheme extracts sufficient information to achieve good back-end signal detection and classification performance while using less power than purely digital spectral techniques such as FFT. Simulations of a prototype system in a mixed-signal 130nm CMOS process show a feasible solution space given an on-line self-calibrating system.

This paper presents the design and test results of a computational radiation sensor system based on a single chip solution that can perform standalone gamma isotope identification. A low power sensor front end with a charge sensitive amplifier, an event driven analog-to-digital converter, and a dedicated microcontroller are integrated on the same chip to process and bin the isotope data from a NaI gamma ray detector according to gathered pulse height. This combination effectively implements a single chip multichannel analyzer with the capability to do further processing of the data in software. To that end, a compact fixed-point program was developed to further analyze the pulse height spectra gathered from a variety of gamma ray sources and perform on-chip real-time gamma isotope identification. The design was fabricated in a 0.18 μm CMOS technology with field tests demonstrating the validity of the approaches taken. The total computational sensor system power consumption is less than 30 μW, excluding the detector power consumption. The gamma isotope identification program executes in 70 ms.

The design of an ultra-low power buck regulator is proposed. The regulator is designed to be integrated with a single-chip wireless sensor network and provide high efficiency at low output currents to maximize the sensor's battery life. The maximum output current is 50 mA. Dynamic voltage scaling is also supported to further reduce total power dissipation. The no-load current of the complete regulator is less than 1 muA. Simulation results give an expected efficiency of over 80% at 20 muW of output power and a peak efficiency of over 95%.

The design of the baseband processor for a non-coherent ultra-wideband receiver is presented. The design integrates all functions necessary for a stand-alone UWB receiver including packet detection and symbol synchronization. The design does not require any high-speed ADCs, but instead relies on simple circuits in the analog domain to acquire the packet and track the incoming data stream. The design provides extensive feedback to the host system about channel conditions and signal strength. The design has been implemented in a 0.18 [m process with a baseband power consumption of 3.5 mW.

This paper presents the design and testing results of a computational radiation sensor. The design utilizes a dedicated microcontroller to perform computation and data aggregation on the sensor head to reduce the information bit rate. A low-power charge sensitive amplifier and ADC complete the design. The design was implemented in a 0.35 µm CMOS technology with field tests demonstrating the validity of the approaches taken.

This paper presents the design and measurements of a predictive coding on-sensor compression CMOS imager. Predictive coding is employed to decorrelate the image. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit. The decorrelated image is encoded with a bank of column-parallel entropy encoders. Each encoder is combined with a single-slope analog-to-digital converter (ADC) to reduce area complexity and power consumption. The area savings resulting from such combination allow to integrate an ADC and an entropy encoder at the column level. A prototype chip was fabricated in a 0.35 μm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm × 5.96 mm which includes an 80 × 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

In this paper, a focal plane SPIHT image compression scheme has been integrated on the focal plane of CMOS image sensor. A test chip is prototyped in 0.35μm technology to verify the design. In our image compression scheme, focal plane prediction replaces the traditional wavelet transform for image decomposition, and the traditional SPIHT coding is modified to reduce computational complexity and to suit the parallel implementation on the sensor focal plane. Simulated compression performance is still good, especially at low bit rates, compared to traditional SPIHT and other compression schemes. Integrating SPIHT compression on the focal plane not only reduces the sensor readout volume, but also provides all the advantages of SPIHT compression including both high image quality and optimized data ordering for progressive image transmission.

A complete low-power front end for particle detection applications is proposed. The front end integrates a charge sensitive amplifier with a novel adaptive biasing scheme which allows the DC bias currents to be scaled below conventional limits. A peak detector circuit obtains a peak value for each detection event which is then converted to digital via an 8 bit charge-redistribution successive approximation analog to digital converter. The ADC is shut off in between detection events to further reduce power consumption. The entire circuit consumes between 39muW and 400muW of power depending on the particle detection rate. This low power operation enables the development of compact, long-life, battery powered, remote particle sensors.

A CMOS image sensor has been designed to perform the front-end image decomposition in a prediction-SPIHT image compression scheme. The prediction circuitry based on charge sharing is integrated inside the sensor array to perform 3-level image decomposition. A CMOS test chip has been prototyped and tested. The test results justify the pixel design and demonstrate that lossy prediction based focal plane image compression can be realized inside the sensor pixel array to achieve a high frame rate but with much less data readout volume. Also, the sensor can be used to achieve comparable compression performance with much lower computational complexity compared to 2D discrete wavelet transform (DWT) based image compression.

Based on the encoding process, arithmetic codes can be viewed as tree codes and current proposals for decoding arithmetic codes with forbidden symbols belong to sequential decoding algorithms and their variants. However, arithmetic coding can also be modeled as a finite state machine and can be treated as a variable-length trellis code. The number of states used for decoding can be reduced and techniques used for convolutional codes such as the list Viterbi decoding algorithm can be applied on the trellis. The proposed approach provides a rich environment for the design of joint source/channel codes. The particular implementation presented here shows significant performance improvement over previous approaches.

In this paper, the minimum error entropy (MEE) criterion is considered as an alternative to the mean square error (MSE) criterion in obtaining predictor coefficients for lossless still image coding. Estimation of the error entropy is done using Renyi's formula. The PDF of the error between image pixels and the predicted values is estimated using the Parzen windowing with a Gaussian kernel. The performance of the error entropy minimization and the mean square error minimization is compared using the first order Shannon's entropy of the residual error. Comparison between MEE and MSE is extended to the issue of treating the image as a number of independent blocks, where each block uses its optimized predictor. The behavior of MEE is similar to MSE with a small improvement when using the maximum allowable window size.

A focal plane video compression integrated circuit is presented. The design consists of a 128 times 128 pixel array and a bank of column-level processors. Each one of the column-level processors performs the tasks of image decorrelation, quantization, and entropy encoding. The chip provides at its output a compressed bit stream. The integration of the quantizer and the entropy encoder at the column level is possible by sharing circuitry between a single-slope analog-to-digital converter and a Golomb-Rice entropy encoder. In addition, the design includes a low-complexity algorithm for the adaptation of the Golomb-Rice coder to the statistics of the video signal. The design has been fully verified through simulations and has been implemented in a 0.35 mum CMOS technology. The chip layout occupies an area of 7 times 5 mm2

We present a CMOS image sensor that performs focal plane image decomposition based on charge sharing computation circuitry. The effect of parasitic capacitance between capacitor bottom plate and substrate on the computational accuracy is discussed and a new circuit is also proposed to characterize the parasitic effects. The test results demonstrate that prediction based focal plane image compression can be realized inside the sensor array resulting in high compression performance using frame rate pixel parallel computation. This architecture can subsequently be combined with backend level testing encoding to form a complete compression sensor.

Ultra wideband (UWB) systems provide high data rates for wireless systems but are also challenged by high power, narrowband interferers falling within the band of interest. This paper proposes an RF front-end implementation to adaptively remove a narrowband, high power interferer from a UWB signal. These signals can drive front-end electronics into saturation, resulting in the loss of the UWB signal. The system is based on an analog implementation of the LMS algorithm. In this study two antenna sensors and analog signal processing are utilized to remove one interferer. This can be extended to more interferers when utilizing additional antenna elements. As opposed to varactor diode based notch filters, this filter implementation achieves wide tuning ranges and can be fully integrated in CMOS. Matlab simulations show that the impact of the adaptive interferer removal on the UWB band can be limited to a narrow frequency band preserving most of the UWB signal power.

Current proposals for using arithmetic coding in a joint source/channel coding framework require 'soft' information to provide error correction. However, in many applications only the binary arithmetic coded output is available at the decoder. We propose a hard decision technique that uses only the information in the bitstream to provide error correction. Where soft information is available this decoder can also be used to substantially enhance the performance of any soft decision decoders by using the two decoders in an iterative fashion.

Previous work has indicated that using an arithmetic encoder with reserved probability space can provide powerful error detection and error correction when used with a sequential decoding algorithm. However, performance improvements were limited at high error rates, principally because of the lack of an explicit decoding tree. In this work a trellis coded modulation scheme is used to provide a convenient tree for a list decoding algorithm. Results are obtained for both a small alphabet application (SPIHT encoded image) and a large alphabet application (predictive lossless image compression). Simulations on AWGN channels with bit error rates in the range of 10/sup -3/ to 10/sup -1.5/ show significant packet recovery rates even for the poorest channels.

An array of microphones is used for both noise suppression and spatial voice activity detection (SVAD). A generalized sidelobe canceler (GSC) is employed for robust adaptive interference rejection and the signals within the GSC are also exploited to provide speech activity detection for the desired signal. The SVAD shows promising results for the difficult case of an interfering speaker.

Reserving space fur a symbol that is not in the source alphabet has been shown to provide excellent error detection. In this paper, we show how to exploit this capability using two sequential decoder structures to provide powerful error correction capability. This joint source/channel coder design provides significant packet loss recovery with minimal rate overhead, and compares favorably with conventional schemes.

Reserving space for a symbol that is not in the source alphabet has been shown to provide excellent error detection. In this paper we show how to use this capability using a sequential decoder structure to provide powerful error correction capability. This joint source/channel coder design provides significant packet loss recovery with minimal overhead.

A robustly constrained minimum variance adaptive array algorithm for general noise suppression and subsequent speech coding is applied in realistic room environments. The results indicate that the robust algorithm is suitable for enhancing speech for subsequent coding. Results also show that the array processing gains are transparent to a CELP coder but not necessarily to an LPC-10 coder.

The paper describes a general broadband, time-domain, robust beamformer design technique and demonstrates its effectiveness. The basic beamforming approach considered is constrained power minimization. The most important quality of this constrained adaptive processor is that the amount of cancellation of the desired signal is directly limited. The processor is designed as follows. An acceptable amount of cancellation of the desired signal is specified. Source models of anticipated types of array imperfections such as misteer, element placement uncertainty, and element response uncertainty are then derived from either modeled or measured array responses. These source models are the basis of both robust linear constraints as well as a single quadratic constraint that define the robust broadband spatial filter. The robust processor design is demonstrated for a headworn array of microphones (hearing aid). A simple, effective adaptive algorithm for processing speech input is also described. Small room reverberation and acoustic headshadow effects are included in the simulations. The resulting processor limits the amount of cancellation of the desired signal that occurs to the allowable amount in the presence of the array imperfections under all input SNR conditions. Effective attenuation of interfering sounds is also exhibited.>

An approach for beamforming in the presence of coherent signals is developed. The correlation between a desired signal and an interferer is broken down by virtual dithering of a beamspace array. The technique can be applied to arbitrary array geometries. Simulation results are presented for narrowband signals for two array geometries: a linear equispaced array and a semicircular array which incorporates the effects of acoustic headshadow. The linear equispace array results allow comparison of this method to spatial smoothing, while the headshadow array results demonstrate the usefulness of the approach for an array which is quite dissimilar to the uniform linear array.>

High-resolution spatial spectrum estimation procedures in conjunction with narrowband multiple beam antenna (MBA) data are considered for source localization. The focus is on aspects of azimuth/elevation-spectrum estimation considering eigenspace estimators. Only two basic approaches to eigenspace spatial-spectrum estimators can be used with MBAs to provide unambiguous source azimuth/elevation estimates. These are the MUSIC approach and the recently developed first principal vectors (FINES) approach. Of these, FINES is recommended because it provides higher resolution.>