Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Stephen M. Sohn

dblp:03/4420 · DBLP profile ↗
← Back
7ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5Artificial intelligence and machine learning · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Parallel and multicore computing · 44% Interconnection networks and networks-on-chip · 42% Hardware accelerators and domain-specific architectures · 10%
Theoretical computer science
1 paper
Algorithms and data structures · 100%

Topics — the 13 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network topology › hypercubic networks
hypercube
0.021991
Parallel Regognition and Parsing on the Hypercube · IEEE Trans. Computers 1991
On Mapping Systolic Algorithms onto the Hypercube · IEEE Trans. Parallel Distributed Syst. 1990
Parallel and multicore computing › parallel algorithms › parallel string algorithms
parallel parsing
0.011991
Parallel Regognition and Parsing on the Hypercube · IEEE Trans. Computers 1991
Algorithms and data structures
dynamic programming
0.011991
Parallel Regognition and Parsing on the Hypercube · IEEE Trans. Computers 1991
Algorithms and data structures
parallel algorithms
0.011991
Parallel Regognition and Parsing on the Hypercube · IEEE Trans. Computers 1991
Interconnection networks and networks-on-chip › graph embedding
hypercube embedding
0.011990
On Mapping Systolic Algorithms onto the Hypercube · IEEE Trans. Parallel Distributed Syst. 1990
Interconnection networks and networks-on-chip
interconnection networks
0.011990
On Mapping Systolic Algorithms onto the Hypercube · IEEE Trans. Parallel Distributed Syst. 1990
Parallel and multicore computing › parallel algorithms › parallel algorithm design
parallel algorithm mapping
0.011990
On Mapping Systolic Algorithms onto the Hypercube · IEEE Trans. Parallel Distributed Syst. 1990
Hardware accelerators and domain-specific architectures
systolic array
0.011990
On Mapping Systolic Algorithms onto the Hypercube · IEEE Trans. Parallel Distributed Syst. 1990
Parallel and multicore computing
parallel algorithms
0.011988
Two-Dimensional Convolution on a Pyramid Computer · IEEE Trans. Pattern Anal. Mach. Intell. 1988
Parallel and multicore computing › parallel architecture
pyramid computer
0.011988
Two-Dimensional Convolution on a Pyramid Computer · IEEE Trans. Pattern Anal. Mach. Intell. 1988
Parallel and multicore computing
load balancing
0.011991
Parallel Regognition and Parsing on the Hypercube · IEEE Trans. Computers 1991
Distributed systems
communication optimization
0.011990
On Mapping Systolic Algorithms onto the Hypercube · IEEE Trans. Parallel Distributed Syst. 1990
Parallel and multicore computing
parallel computing
0.011990
On Mapping Systolic Algorithms onto the Hypercube · IEEE Trans. Parallel Distributed Syst. 1990

Methods — techniques the papers use, named apart from their topics

hypercube interconnection · 0.0dynamic load balancing · 0.0mapping technique · 0.0affine scheduling · 0.0
YearPublicationVenuePosition
1995 A note on parsing pattern languages
Oscar H. Ibarra, Ting-Chuen Pong, Stephen M. Sohn
Pattern Recognit. Lett.3
1991 Layered Networks A New Class of Multistage Interconnection Networks
Donald B. Bennett, Stephen M. Sohn
ICPP (1)2
1991 Parallel Regognition and Parsing on the Hypercube
abstract
The authors present parallel algorithms for recognizing and parsing context-free languages on the hypercube. This algorithm is both time-wise and space-wise optimal with respect to the usual sequential dynamic programming algorithm. Also, the number of nonoverlapping interprocessor data transmissions for the recognition phase is small. It is noted that this is desirable since communication cost in reality is a function of the number of transmissions as well as transmission length. The authors present another recognition algorithm that achieves the same time and space bounds but employs a dynamic loading balancing technique to increase processor utilization. The results of implementing these algorithms on a 64-node NCUBE/7 MIMD hypercube machine are also given. The experimental evidence indicates that, while both recognition algorithms exhibit acceptable speedups, using load balancing results in significantly better performance. The authors obtain parallel algorithms with the same time and space bounds as above for the polygon triangulation problem and the matrix product chain problem.>
Oscar H. Ibarra, Ting-Chuen Pong, Stephen M. Sohn
IEEE Trans. Computers3
1990 On Mapping Systolic Algorithms onto the Hypercube
abstract
Consideration is given to the problem of mapping systolic array algorithms into efficient algorithms for a fixed-size hypercube architecture. The authors describe in detail several optimal implementations of algorithms given for one-way one- and two-dimensional systolic arrays. Since interprocessor communication is many times slower than local computation in parallel computers built to date, the problem of efficient communication is specifically addressed for these mappings. In order to validate the technique experimentally, five systolic algorithms were mapped in various ways onto a 64-node NCUBE/7 MIMD hypercube machine. The algorithms are for the following problems: the shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, matrix multiplication, and computing the Boolean transitive closure. Experimental evidence indicates that good performance is obtained for the mappings.>
Oscar H. Ibarra, Stephen M. Sohn
IEEE Trans. Parallel Distributed Syst.2
1989 On Mapping Systolic Algorithms onto the Hypercube
Oscar H. Ibarra, Stephen M. Sohn
ICPP (1)2
1988 Two-Dimensional Convolution on a Pyramid Computer
abstract
An algorithm for convolving a k*k window of weighting coefficients with an n*n image matrix on a pyramid computer of O(n/sup 2/) processors in time O(logn+k/sup 2/), excluding the time to load the image matrix, is presented. If k= Omega ( square root log n), which is typical in practice, the algorithm has a processor-time product O(n/sup 2/ k/sup 2/) which is optimal with respect to the usual sequential algorithm. A feature of the algorithm is that the mechanism for controlling the transmission and distribution of data in each processor is finite state, independent of the values of n and k. Thus, for convolving two (0, 1)-valued matrices using Boolean operations rather than the typical sum and product operations, the processors of the pyramid computer are finite-state.>
Jik H. Chang, Oscar H. Ibarra, Ting-Chuen Pong, Stephen M. Sohn
IEEE Trans. Pattern Anal. Mach. Intell.4
1987 Two-Dimensional Convolution on a Pyramid Computer
Jik H. Chang, Oscar H. Ibarra, Ting-Chuen Pong, Stephen M. Sohn
ICPP4