In this paper the problem of testing high speed CMOS circuits is considered. A test methodology based on a Built-in Self-Test scheme adapted to TSPC circuits is proposed. We show through HSpice simulations on netlists extracted from layout that this scheme can operate at more than 580 MHz. Moreover, an efficient solution to the problem of redesigning an easily testable functionally equivalent logic block to eliminate hard to test and untestable faults in TSPC circuits is introduced.

An inexpensive Design For Testability (DFT) technique, called Partial Reset (PR), was recently proposed to ease automatic test pattern generation of sequential circuits. In the present paper, we propose a new PR-like method. With this method, flip-flops to be reset are selected in order to ease pseudo-random testing of sequential circuits. Moreover, the control of these reset are condensed on a reduced set of input lines. Therefore, only a small number of additional primary inputs are required. This technique has been evaluated on a large subset of the 1989 ISCAS sequential benchmark circuits and promising results were obtained.

In this paper, a new design-for-testability technique for sequential circuits is presented. This technique may be considered as an alternative to full scan. The fault coverages obtained with this technique are comparable to those produced by full scan techniques. However, the present method improves full scan in several ways. The application test time of a device is reduced to that of applying parallel vectors at the operational speed. This characteristic of applying test vectors at the operational speed has a positive impact on the test quality. Indeed, a stuck-at test, applied at the operational speed of the circuit, identifies more defective chips than the same test applied at a lower speed. Furthermore, the timing and the area overheads, which are often considered to be serious disadvantages of DFT techniques, are in this case acceptable. With this method, all FFs are replaced with XFF gates. The XFF gate is similar to a T flip-flop without feedback. However, in some cases, when observability problems are still important, a probe observation point is inserted at the pseudo-primary inputs (PPIs).

In this paper, the initialization of sequential circuits using pseudorandom input patterns is addressed. An extended Markov chain model that covers the initialization phase is proposed. This model supports the theoretical framework used to demonstrate that sequential circuits can be initialized with pseudorandom vectors. This leads to a uniform BIST approach in which initialization and testing are performed together with a single pseudorandom generator.>