Computer-aided design tools have been limited by the use of the Binary Decision Diagram (BDD). The major drawback of the BDD is its abundant usage of CPU time and memory. Techniques such as BDD variable ordering and sharing have been used in the past to address the size issue. However these techniques remain to be limited to modest-sized circuits. In this paper, we present a significant variation to the conventional BDD, the Connective Binary Decision Diagram (CBDD). The CBDD addresses the size issue concerning conventional BDD implementations by employing the use of minimized-scalable binary decision diagrams (MSBDDs) combined with the structural connectivity present in the circuit's netlist. The experimental results section will demonstrate that the proposed method reduces the BDD size by more than two orders of magnitude for large circuits.

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This paper presents a human-like dynamic programming neural network method for speech recognition using dynamic time warping. The networks are configured, much like human's, such that the minimum states of the network's energy function represent the near-best correlation between test and reference patterns. The dynamics and properties of the neural networks are analytically explained. Simulations for classifying speaker-dependent isolated words, consisting of 0 to 9 and A to Z, show that the method is better than conventional methods. The hardware implementation of this method is also presented.

A pulse-mode digital multilayer neural network (DMNN) based on stochastic computing techniques is implemented with simple logic gates as basic computing elements. The pulse-mode signal representation and the use of simple logic gates for neural operations lead to a massively parallel yet compact and flexible network architecture, well suited for VLSI implementation. Algebraic neural operations are replaced by stochastic processes using pseudorandom pulse sequences. The distributions of the results from the stochastic processes are approximated using the hypergeometric distribution. Synaptic weights and neuron states are represented as probabilities and estimated as average pulse occurrence rates in corresponding pulse sequences. A statistical model of the noise (error) is developed to estimate the relative accuracy associated with stochastic computing in terms of mean and variance. Computational differences are then explained by comparison to deterministic neural computations. DMNN feedforward architectures are modeled in VHDL using character recognition problems as testbeds. Computational accuracy is analyzed, and the results of the statistical model are compared with the actual simulation results. Experiments show that the calculations performed in the DMNN are more accurate than those anticipated when Bernoulli sequences are assumed, as is common in the literature. Furthermore, the statistical model successfully predicts the accuracy of the operations performed in the DMNN.

A new architecture and a statistical model for a pulse-mode digital multilayer neural network (DMNN) are presented. Algebraic neural operations are replaced by stochastic processes using pseudo-random pulse sequences. Synaptic weights and neuron states are represented as probabilities and estimated as average rates of pulse occurrences in corresponding pulse sequences. A statistical model of error (or noise) is developed to estimate relative accuracy associated with stochastic computing in terms of mean and variance. The stochastic computing technique is implemented with simple logic gates as basic computing elements leading to a high neuron-density on a chip. Furthermore, the use of simple logic gates for neural operations, the pulse-mode signal representation, and the modular design techniques lead to a massively parallel yet compact and flexible network architecture, well suited for VLSI implementation. Any size of a feedforward network can be configured where processing speed is independent of the network size. Multilayer feedforward networks are modeled and applied to pattern classification problems such as encoding and character recognition.

An architecture and a statistical model for a pulse-mode digital multilayer neural network (DMNN) are presented. The model uses simple logic gates as basic computing units. Modular design techniques lead to an extremely compact and flexible network architecture for VLSI implementation. An example network for character recognition and its performance are presented.>

Neural networks for linear and quadratic programming are analyzed. The network proposed by M.P. Kennedy and L.O. Chua (IEEE Trans. Circuits Syst., vol.35, pp.554-562, May 1988) is justified from the viewpoint of optimization theory and the technique is extended to solve optimization problems, such as the least-squares problem. For quadratic programming, the network converges either to an equilibrium or to an exact solution, depending on whether the problem has constraints or not. The results also suggest an analytical approach to solve the linear system Bx =b without calculating the matrix inverse. The results are directly applicable to optimization problems with C(2) convex objective functions and linear constraints. The dynamics and applicability of the networks are demonstrated by simulation. The distance between the equilibria of the networks and the problem solutions can be controlled by the appropriate choice of a network parameter.

A novel two-phase neural network that is suitable for solving a large class of constrained or unconstrained optimization problem is presented. For both types of problems with solutions lying in the interior of the feasible regions, the phase-one structure of the network alone is sufficient. When the solutions of constrained problems are on the boundary of the feasible regions, the proposed two-phase network is capable of achieving the exact solutions, in contrast to existing optimization neural networks which can obtain only approximate solutions. Furthermore, the network automatically provides the corresponding Lagrange multiplier associated with each constraint. Thus, for linear programming, the network solves both the primal problems and their dual problems simultaneously.

An architecture for dynamic programming neural networks is presented. The architecture is based on a building block paradigm in which the network is constructed from neuron array and weight assignment chips. Because of its simple and regular structure, the architecture is a feasible implementation for dynamic programming neural networks with current VLSI technology. Moreover, this architecture can be further extended to other Hopfield-Tank type networks.>

A method for improving the performance of artificial neural networks for linear and nonlinear programming is presented. By analyzing the behavior of the conventional penalty function, the reason for the inherent degenerating accuracy is discovered. Based on this, a new combination penalty function is proposed which can ensure that the equilibrium point is acceptably close to the optimal point. A known neural network model has been modified by using the new penalty function and the corresponding circuit scheme is given. Simulation results show that the relative error for linear and nonlinear programming is substantially reduced by the new method.

All analytical examination of the energy function associated with a dynamic programming neural network is presented. The analysis is carried out in two steps. First, the locations and numbers of the minimum states for different components of the energy function are investigated in the extreme cases. A clearer insight into the energy function can be gained through the minimum states of different components. Secondly, the locations of the minimum states of the energy function using different parameter values are derived. It is shown that the minimum states can reside in regions which are regarded as valid solutions with certain conditions. Examples and simulation results are given to justify the validity of the theories developed.

Presents an analysis of the stability properties of a linear-programming neural network used for minimizing a linear cost function under the constraint that the feasible region is a hypercube inRn, i.e. [0,1]n. A properly designed neural network structure can possess both the Lagrangian function method and the penalty function method concepts. The equilibrium of the network is asymptotically stable and is in the neighborhood of a corner of the hypercube, where the corner is the point minimizing the cost function. The equilibrium point of the network can be made arbitrarily close to the minimizer of the cost function by varying a factor introduced into the network

An artificial neural network (ANN) formulation for solving the dynamic programming problem (DPP) is presented. The DPP entails finding an optimal path from a source node to a destination node which minimizes (or maximizes) a performance measure of the problem. The optimization procedure is implemented and demonstrated using a modified Hopfield–Tank ANN. Simulations show that the ANN can provide a near-optimal solution during an elapsed time of only a few characteristic time constants of the circuit for DPPs with sizes as large as 64 stages with 64 states in each stage. An application of the proposed algorithm to an optimal control problem is presented. The proposed artificial neural network dynamic programming algorithm is attractive due to its radically improved speed over conventional techniques especially where real-time near-optimal solutions are required.

Previous work on computer architecture design for robotics is reviewed. Based on the analysis of the performance data, two crucial issued are addressed: the decision on how specific an architecture should be and which architecture styles should be chosen for particular applications.>

ASIC (application-specific integrated circuit) technology has created opportunities for implementing robotic control algorithms directly in silicon. However, the sheer complexity of VLSI design represents a tremendous knowledge barrier to system designers. To lower this knowledge barrier, a concise conceptual framework is presented which allows robotics hardware designers to acquire the essential knowledge of the ASIC technology efficiently. It addresses different aspects of how design decisions are made. The global strategy is to limit the search space through methodology implemented by CAE (computer-aided engineering) and expert systems. Alternatives are recognized through a proper framing of design space. A set of techniques for evaluation of the alternatives is classified. The conceptual framework enables system designers and application engineers to acquire and apply ASIC technology in a systematic and logical manner and thus facilitates efficient application of the technology in robotic hardware designs.>

An attempt is made to gain a better understanding of the nature of ASIC (application-specific integrated circuit) design. This is done from a decision-making perspective, in terms of three knowledge frames: the design process, the design hyperspace, and the design repertoire. The design process frame emphasizes the hierarchical design approach and presents the methodology as a formalization of the design process. The design hyperspace concept relates to the recognition of design alternatives. Analysis techniques for evaluating algorithmic and architectural alternatives are collected and classified to form the design repertoire. This conceptual framework is an effective instrument for bridging the widening gap between system designers and VLSI technology. It also provides a conceptual platform for the development of tools for high-level architectural designs.>

An improved systematic method is introduced which reduces the number of ad hoc steps and provides all possible systolic solutions for a given algorithm. Algorithms are modeled using index space (geometric) representations where the index transformation matrices are determined systematically. Systolic arrays are produced by geometric projections.

A conceptual framework consisting of the design process, the design space, and the design repertoire for ASIC hardware is presented. An Inter-Level Design Process Model (ILDP) is proposed as a general model for expressing and implementing hierarchical design methodologies. The proposed conceptual framework is an effective instrument for bridging the increasingly wider gap between application engineers and VLSI designers.

The desire to add more intelligent functionality and enhanced real-time Control capability to robotic systems places a heavy demand on computational resources. Nascent application-specific VLSI technology offers an unprecedented opportunity to relieve this computational burden by implementing specific robotic functions directly in hardware. A VLSI architecture, designed to compute the direct kinematic solution (DKS) on a single chip, is described. The DKS chip features fixed-point calculation and on-chip generation of trigonometric functions. The calculation achieves the resolution required for most industrial applications. Innovative modifications of the conventional adder control and the form of the homogeneous transformation matrix have improved throughput. Simulation results indicate that speed improvements of several orders of magnitude in the kinematic computation are achievable with application-specific integrated circuit technology, compared to microprocessor implementation.

The architecture of a VLSI chip dedicated to the real-time computation of the Direct Kinematic Solution (DKS) is described. The design features fixed-point calculation and on-chip generation of trigonometric functions. The computed output has the resolution required for most industrial applications. Consideration of VLSI design regularity leads to the modification of the homogeneous transformation matrices. Pipelining techniques are applied to improve throughput. The control-store implementation provides adaptability to virtually all robot arms. Transistor and cell counts confirm the feasibility of a semi-custom implementation approach with current technology. Results indicate that the DKS can be obtained in microseconds with this new architecture, which amounts to a speed improvement of three orders of magnitude compared to a similar algorithm implemented on a 16-bit microprocessor.