Modular multilevel converters (MMCs) obtain widespread utilization in high-voltage direct current (HVdc) applications scenarios. The cost of power losses plays a significant part in MMC’s operating costs. Hence, this article proposes a quantum genetic algorithm-based power losses optimization control (QGA-PLOC). By comprehensively considering the power losses of the MMC, the quantum genetic algorithm determines the first-best value of the injected second circulating current magnitude and phase angle in the arm, as well as the optimal MMC power losses under given conditions. The quantum genetic algorithm incorporates the quantum state vector representation into genetic encoding and utilizes quantum logic gates for chromosome evolution, greatly improving the algorithm’s performance and significantly enhancing its computational efficiency and global optimization capability. Moreover, introducing the quantum genetic algorithm into the field of MMC power losses optimization offers a new path to address the acquisition of the optimal circulating current reference value in power loss optimization problems. MMC Simulation and experiment are also conducted, and the research results verify the effectiveness of the proposed QGA-PLOC for MMCs.

This paper presents a Bayesian data fusion framework for estimating journey time variability that uses a mixture distribution model to classify feeding data into different traffic states. Different from most studies, the proposed framework offers a generalized statistical foundation for making full use of multiple traffic data sources to estimate the vehicular journey time variability. Feeding data collected from multiple data sources are classified based on the associated traffic conditions, and the corresponding estimation biases of the individual data sources are determined by arbitrary distributions. The proposed framework is implemented and tested on a Hong Kong corridor with actual data collected from the field. Different statistical distributions of prior and likelihood knowledge are applied and compared. The findings of the case study show significant improvement in the journey time estimations of the proposed method compared with the individual measurements. The results also highlight the benefit of incorporating a traffic state classifier and prior knowledge in the fusion framework. This study contributes to the development of reliability-based intelligent transportation systems based on advanced traffic data analytics.

The releases of Intel SGX and AMD SEV mark the transition of hardware-based enclaves from research prototypes to mainstream products. These two paradigms of secure enclaves are attractive to both the cloud providers and tenants, since security is one of the key pillars of cloud computing. However, it is found that current hardware-defined enclaves are not flexible and efficient enough for the cloud. For example, although SGX can provide strong memory protection with both confidentiality and integrity, the size of secure memory is tightly restricted. On the contrary, SEV enables enclaves to use more memory but has critical security flaws due to no memory integrity protection. Meanwhile, both types of enclaves have relatively long booting latency, which makes them not suitable for short-term tasks like serverless workloads. After an in-depth analysis, we find that there are some intrinsic tradeoffs between security and performance due to the limitation of architectural designs. In this article, we investigate a novel hardware-software co-design of enclaves to meet the requirements of cloud by placing a part of the logic of the enclave mechanism into a lightweight software layer, named Enclavisor, to achieve a balance between security, performance, and flexibility. Specifically, our implementation is based on AMD's SEV and, Enclavisor is placed in the guest kernel mode of SEV's secure virtual machines. Enclavisor inherently supports memory encryption with no memory limitation and also achieves efficient booting, multiple enclave granularities, and post-launch remote attestation. Meanwhile, we also propose hardware/software solutions to mitigate the security flaws caused by the lack of memory integrity. We implement a prototype of Enclavisor on an AMD SEV server. The experiments on both micro-benchmarks and application benchmarks show that enclaves on Enclavisor can have close-to-native performance.