This paper presents two novel ultra-low-voltage (ULV) Single-Edge-Triggered flip-flops (SET-FF) based on the True-Single-Phase-Clocking (TSPC) scheme. By exploiting the TSPC principle, the overall energy efficiency has been improved compared to the traditional flip-flop designs while providing fully static, contention-free functionality to satisfy ULV operation. At 0.5V near-Vthlevel in 65nm bulk CMOS technology, the proposed SET-FFs demonstrate up to 11-45% and 7-20% of energy efficiency at 0% and 100% data activity rates compared to the best known SET-FFs. The proposed SET-FF can safely operate down to 0.24V of supply voltage without corrupting rail-to-rail voltage levels at its internal nodes. The integration of proposed SET-FFs in a 320-bit parallel shift register demonstrated up to 33% of clock network power, 17-39% of register power reductions compared to the state-of-the-art and commercial standard-cells at near-Vthlevel. In addition to these merits, with the aid of parasitic modeling, this paper re-evaluates the vital performance metrics of SET-FFs at near-Vthvoltage domain, improving their characterization accuracy and enabling the VLSI integration for commercial end-use.

This paper presents an energy-efficient standard-cell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub- Vthoperation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30 % -60 % of energy savings at 0.5V, typical near- Vthlevel for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25- Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.

This paper presents two novel circuit arrangements for an ultra-low voltage, low-power 4-to-2 compressor targeting typical near-Vthapplication domain. A hybrid logic style is utilized to exploit energy efficiency by means of parasitic reduction in circuit blocks. Proposed structures are evaluated against prevalent compressors in terms of their typical figure of merits and noise immunity. From extensive post-layout simulations in 65-nm bulk CMOS process technology, the most optimal arrangement was found to be 35% more power efficient, 3.4% faster, 8% more area efficient and 37% better in PDP at 0.4VDDcompared to most appealing implementations in literature.

This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general.

In spite of the fact that floating-point arithmetic is costly in terms of silicon area, the joint design of hardware for floating-point and integer arithmetic is seldom considered. While components like multipliers and adders can potentially be shared, floating-point and integer units in contemporary processors are practically disjoint. This work presents a new architecture which tightly integrates floating-point and integer arithmetic in a single datapath. It is mainly intended for use in low-power embedded digital signal processors and therefore the following design constraints were important: limited use of pipelining for the convenience of the compiler; maintaining compatibility with existing technology; minimal area and power consumption for applicability in embedded systems. The architecture is tailored to digital signal processing by combining floating-point fused multiply-add and integer multiply-accumulate . It could be deployed in a multi-core system-on-chip designed to support applications with and without dominance of floating-point calculations. The VHDL structural description of this architecture is available for download under BSD license. Besides being configurable at design time, it has been thoroughly checked for IEEE-754 compliance by means of a floating-point test suite originating from the IBM Research Labs. A proof-of-concept has also been implemented using STMicroelectronics 65nm technology. This prototype supports 32-bit signed two's complement integers and 41-bit (8-bit exponent and 32-bit significand) floating-point numbers. Our evaluations show that over 67% energy and 19% area can be saved compared to a reference design in which floating-point and integer arithmetic are implemented separately. The area overhead caused by combining floating-point and integer is less than 5%. Implemented in ST's general-purpose CMOS technology, the design can operate at a frequency of 1.35GHz, while 667MHz can be achieved in low-power CMOS. Considering that the entire datapath is partitioned in just three pipeline stages, and the fact that the design is intended for use in the low-power domain, these frequencies are adequate. They are in fact competitive with current technology low-power floating-point units. Post-layout estimates indicate that the required area of a low-power implementation can be as small as 0.04mm 2 . Power consumption is on the order of several milliwatts. Strengthened by the fact that clock gating could reduce power consumption even further, we think that a shared floating-point and integer architecture is a good choice for signal processing in low-power embedded systems.

This paper presents a novel minutiae matching method that describes elastic distortions in fingerprints by means of a thin-plate spline model, which is estimated using a local and a global matching stage. After registration of the fingerprints according to the estimated model, the number of matching minutiae can be counted using very tight matching thresholds. For deformed fingerprints, the algorithm gives considerably higher matching scores compared to rigid matching algorithms, while only taking 100ms on a 1GHz P-III machine. Furthermore, it is shown that the observed deformations are different from those described by theoretical models proposed in the literature.

The first subject of the paper is the estimation of a high resolution directional field of fingerprints. Traditional methods are discussed and a method, based on principal component analysis, is proposed. The method not only computes the direction in any pixel location, but its coherence as well. It is proven that this method provides exactly the same results as the "averaged square-gradient method" that is known from literature. Undoubtedly, the existence of a completely different equivalent solution increases the insight into the problem's nature. The second subject of the paper is singular point detection. A very efficient algorithm is proposed that extracts singular points from the high-resolution directional field. The algorithm is based on the Poincare index and provides a consistent binary decision that is not based on postprocessing steps like applying a threshold on a continuous resemblance measure for singular points. Furthermore, a method is presented to estimate the orientation of the extracted singular points. The accuracy of the methods is illustrated by experiments on a live-scanned fingerprint database.

CRACKER is an algorithm able to handle a large class of routing problems. Operating on a grid and using two wiring layers, it can deal with floating and fixed terminals, arbitrarily located in the routing area, and with obstacles in either of the two layers. The routing process consists of two stages. In the first stage, all nets are interconnected quickly, without avoiding conflicts with previously routed nets or obstacles. In the iterative second stage, connectivity-preserving local transformations are applied in a systematic way, such that, eventually, a solution without conflict is reached. There is no rip-up and reroute. The same algorithm is able to solve well-known examples of switchbox routing, routing with irregular boundaries, L-shaped channels, three-sided channels, etc.>

An algorithm for switchbox routing called PACKER is presented. In an initial phase, the connectivity of each net is established in a fast way without taking the other nets into account. In general, this gives rise to conflicts (short circuits). In the second stage the conflicts are removed iteratively using connectivity-preserving local transformations. They reshape a net by displacing one of its segments without disconnecting it from the net. The transformations are applied in a systematic way using a scan-line technique. During this process, a subset of the segments at the position of the scan line is densely packed in the (two) layers available for routing. The remaining segments are pushed to the next scan-line position. Scanning in the four available directions (left to right, right to left, top to bottom, and bottom to top) is performed until all conflicts have disappeared or no solution is found within a maximum number of iterations. It turns out that the new approach to routing, as implemented in PACKER, also has practical merits: most of the well-known benchmark examples are solved.>