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Richard Korry

dblp:03/6769 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 67% Processor architecture and microarchitecture · 33%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
multithreading
0.011997
Tera Hardware Software Cooperation · SC 1997
Parallel and multicore computing
parallel programming models
0.011997
Tera Hardware Software Cooperation · SC 1997
Parallel and multicore computing › parallel programming models
shared-memory parallelization
0.011997
Tera Hardware Software Cooperation · SC 1997
Compilers and program optimization › parallel program optimization
compiler optimization for parallel architectures
0.011997
Tera Hardware Software Cooperation · SC 1997
YearPublicationVenuePosition
1997 Tera Hardware Software Cooperation
abstract
The development of Tera's MTA system was unusual. It respected the need for fast hardware and large shared memory, facilitating execution of the most demanding parallel application programs. But at the same time, it met the need for a clean machine model enabling calculated compiler optimizations and easy programming; and the need for novel architectural features necessary to support fast parallel system software. From its inception, system and application needs have molded the MTA architecture. The result is a system that offers high performance and ease of programming by virtue not only of fast physical hardware and flat shared memory, but also of the streamlined software systems that well utilize the features of the architecture intended to support them.
Gail A. Alverson, Preston Briggs, Susan Coatney, Simon Kahan, Richard Korry
SC5
1995 Scheduling on the Tera MTA
Gail A. Alverson, Simon Kahan, Richard Korry, Cathy McCann, Burton J. Smith
JSSPP3