Intercore communication in many-core processors presently faces scalability issues similar to those that plagued intracity telecommunications in the 1960s. Optical communication promises to address these challenges now, as then, by providing low latency, high bandwidth, and low power communication. Silicon photonic devices presently are vulnerable to fabrication and temperature-induced variability. Our fabrication and measurement results indicate that such variations degrade interconnection performance and, in extreme cases, the interconnection may fail to function at all. In this paper, we propose a reliability-aware design flow to address variation-induced reliability issues. To mitigate effects of variations, limits of device design techniques are analyzed and requirements from architecture-level design are revealed. Based on this flow, a multilevel reliability management solution is proposed, which includes athermal coating at fabrication-level, voltage tuning at device-level, as well as channel hopping at architecture-level. Simulation results indicate that our solution can fully compensate variations thereby sustaining reliable on-chip optical communication with power efficiency.

While transistor performance and energy efficiency have dramatically improved in recent years, electrical interconnect improvements has failed to keep pace. Recent advances in nanophotonic fabrication have made on-chip optics an attractive alternative. However, system integration challenges remain. In particular, the parameters of on-chip nanophotonic structures are sensitive to fabrication-induced process variation and run-time spatial thermal variation across the die. This work addresses the performance and reliability challenges that arise from this sensitivity to variation. The paper first presents a model predicting the system-level effects of thermal and process variation in nanophotonic networks. It then shows how to optimize many-core system performance and reliability by using run-time techniques to compensate for the thermal and process variation effects.

The nanophotonic network promises improved communications between cores in many-core systems. This paper discusses a novel modeling and simulation methodology. This infrastructure can compare performance, power consumption and reliability of nanophotonic network designs. Phenomenologically determined transfer-matrix device models are employed to characterize network performance under realistic multi-threaded applications, optical power transmission across the full wevelength-division multiplexing spectrum, and network reliability as affected by fabrication-induced process variation and run-time system thermal effects. Five recently proposed networks are analyzed to better elucidate advantages and limitations.

On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfers, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article analyzes on-chip communication challenges and studies the characteristics of existing electrical and emerging nanophotonic interconnect. Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network, is thus introduced. Iris's circuit-switched subnetwork supports throughput-sensitive data transfer. Iris's optical-antenna-array-based broadcast--multicast subnetwork optimizes latency-critical traffic and supports the path setup of circuit-switched communication. Overall, the proposed nanophotonic network design offers an on-chip communication backplane that is power efficient while demonstrating low latency and high throughput.

Recent advances in nanophotonic technology have made nano- photonic interconnect an attractive on-chip communication solution for emerging many-core systems. However, fabrication- induced process variation and run-time system thermal effects directly affect nanophotonic device operation, and introduce serious challenges, e.g., signal power loss and crosstalk, to the power, performance and reliability of nanophotonic communication.

On many-core chip designs, short, often-multicast, latency-critical messages, used extensively in high-level coherence and synchronization protocols, often become the bottleneck of parallel performance scaling. This paper presents Spectrum, a hybrid nanophotonic-electric on-chip network that optimizes both throughput and latency. Spectrum's novel planar nanophotonic subnetwork broadcasts latency-critical messages through a wavelength-division multiplexed (WDM) two-dimensional waveguide. Spectrum's throughput-optimized packet-switching electrical subnetwork handles high bandwidth traffic. Overall, Spectrum delivers an almost ideal CMOS-compatible interconnection network for many-core systems.

On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article presents Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network. Iris' linear-waveguide-based throughput-optimized circuit-switched subnetwork supports throughput-sensitive data transfer. Iris' planar-waveguide-based WDM broadcast-multicast subnetwork optimizes latency-critical traffic and supports the circuit setup of circuit-switched communication. Overall, the proposed design delivers an on-chip communication backplane with high power efficiency, low latency, and excellent throughput.