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Nan Ni

dblp:03/757 · DBLP profile ↗
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7ranked-venue papers
4as first author
0since 2021 · last 2020
0000-0002-7987-5226ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 3 first-authorComputer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
2 papers
Routing and switching · 48% Internet architecture and protocols · 29% Wireless networking · 11%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 100%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols
buffer management
0.022002
Fair Scheduling in Internet Routers · IEEE Trans. Computers 2002
Fair Scheduling and Buffer Management in Internet Routers · INFOCOM 2002
Routing and switching › switch buffer management
early packet discard
0.022002
Fair Scheduling in Internet Routers · IEEE Trans. Computers 2002
Fair Scheduling and Buffer Management in Internet Routers · INFOCOM 2002
Internet architecture and protocols
quality of service
0.022002
Fair Scheduling and Buffer Management in Internet Routers · INFOCOM 2002
Fair Scheduling in Internet Routers · IEEE Trans. Computers 2002
Network optimization and economics › resource allocation › bandwidth allocation
fair bandwidth allocation
0.012002
Fair Scheduling and Buffer Management in Internet Routers · INFOCOM 2002
Wireless networking
fair scheduling
0.012002
Fair Scheduling in Internet Routers · IEEE Trans. Computers 2002
Routing and switching › switch scheduling
input-queued switch scheduling
0.012002
Fair Scheduling and Buffer Management in Internet Routers · INFOCOM 2002
Routing and switching
router architecture
0.012002
Fair Scheduling and Buffer Management in Internet Routers · INFOCOM 2002
Routing and switching
switch scheduling
0.012002
Fair Scheduling in Internet Routers · IEEE Trans. Computers 2002
Interconnection networks and networks-on-chip
switch architecture
0.011999
The Impact of Link Arbitration on Switch Performance · HPCA 1999
Interconnection networks and networks-on-chip
multiprocessor interconnection
0.011999
The Impact of Link Arbitration on Switch Performance · HPCA 1999

Methods — techniques the papers use, named apart from their topics

simulation · 0.1iterative fair scheduling · 0.0synthetic workload simulation · 0.0execution-driven simulation · 0.0
YearPublicationVenuePosition
2020 Fabsim-X: A Simulation Framework for the Analysis of Large-Scale Topologies and Congestion Control Protocols in Data Center Networks
abstract
The explosive growth in cloud-computing and overall data center system growth has created an unprecedented demand on system architects and designers to continuously develop more complex system networks to effectively satisfy the insatiable appetite to process, move, and store large amounts of data. Nonlinear system behavior caused by emerging workloads and use-cases, varying end-to-end congestion protocols, and heterogeneity in the various compute and storage capabilities of custom designed accelerators further compounds the design problem. Modern simulation methodologies lack a cohesive and efficient framework to address the interoperability of the intersecting layers at scale. In this paper, we present a simulation framework for evaluating congestion control protocols. Furthermore, we present a set of optimizations that enable analysis for longer simulated times and at network scales up to 128K nodes, which is vital for proper analysis of workloads that require long run times (e.g., AI training) or workloads that are known to have scaling issues (e.g., RDMA). Specifically, we evaluate congestion control performance at various scales, study the implications of topology scaling on congestion, and the performance impact of simultaneous heterogeneous protocols.
Malek Musleh, Roberto Peñaranda, Allister Alemania, Pedro Yébenes, Gene Wu, Jan Zielinski, Krzysztof Raszkowski, Nan Ni, Scott Diesing, Anupama Kurpad, Ram Huggahalli, Curt E. Bruns, Sujoy Sen
MASCOTS8
2002 Fair Scheduling and Buffer Management in Internet Routers
abstract
Input buffered switch architecture has become attractive for implementing high performance routers, and expanding use of the Internet sees an increasing need for quality of service. It is challenging to provide a scheduling technique that is both highly efficient and fair in resource allocation. We first introduce an iterative fair scheduling (iFS) scheme for input buffered switches that supports fair bandwidth distribution among the flows and achieves asymptotically 100% throughput. The iFS is evaluated both under synthetic workload and with Web traces from the Internet. Compared to the commonly used synthetic input, our simulation results reveal significant difference in performance when real network traffic is employed. We then consider fair scheduling under various buffer management mechanisms and analyze their impact on the fairness in bandwidth allocation. Our studies indicate that early packet discard in anticipation of congestion is necessary and per-flow based buffering is effective for protecting benign users from being adversely affected by misbehaved traffic. Buffer allocation according to bandwidth reservation is especially helpful when the input traffic is highly bursty.
Nan Ni, Laxmi N. Bhuyan
INFOCOM1
2002 Fair Scheduling in Internet Routers
abstract
Input buffered switch architecture has become attractive for implementing high performance routers and expanding use of the Internet sees an increasing need for quality of service. It is challenging to provide a scheduling technique that is both highly efficient and fair in resource allocation. In this paper, we first introduce an iterative fair scheduling (IFS) scheme for input buffered switches that supports fair bandwidth distribution among the flows and achieves asymptotically 100 percent throughput. The IFS is evaluated both under synthetic workload and with Web traces from the Internet. Compared to the commonly used synthetic input, our simulation results reveal significant difference in performance when the real network traffic is employed. We then consider fair scheduling under various buffer management mechanisms and analyze their impact on the fairness in bandwidth allocation. Our studies indicate that early packet discard in anticipation of congestion is necessary and per-flow based buffering is effective for protecting benign users from being adversely affected by misbehaving traffic. Buffer allocation according to bandwidth reservation is especially helpful when the input traffic is highly bursty.
Nan Ni, Laxmi N. Bhuyan
IEEE Trans. Computers1
2001 Fair Scheduling for Input Buffered Switches
abstract
Input buffered switch architecture has become attractive for implementing high performance switches for workstation clusters. It is challenging to provide a scheduling technique that is both highly efficient and fair in resource allocation. In this paper, we first introduce an iterative fair scheduling(iFS) scheme for input buffered switches that supports fair bandwidth distribution among the flows and achieves asymptotically 100% throughput. We then apply the idea of fair scheduling to switches with multicasting capability and propose an mFS scheme which allocates bandwidth to various flows according to their reservations. We show that mFS produces throughput comparable to the existing schemes while distributing the bandwidth as per the given reservations. Extensive simulation results are presented to validate the effectiveness of our proposed schemes.
Nan Ni, Laxmi N. Bhuyan
IPDPS1
2000 Exploring the Switch Design Space in a CC-NUMA Multiprocessor Environment
abstract
The switch design for interconnection networks plays an important role in the overall performance of multiprocessors and computer networks. It is therefore crucial to study various factors in the switch design space and their influence on the system performance. In this paper we first propose a 4-D framework for the design of input queuing switches with wormhole routing and virtual channels. Then we explore the design space to examine in detail the impact of four parameters: virtual channel allocation, intraswitch connectivity buffer space allocation and link arbitration policy. Our simulations, performed with an execution driven simulator with ILP processors, show that the cumulative effect of the four switch enhancements ranges between 7% and 38%. The most important parameter proves to be VC allocation method (up to 28% improvements in execution time). The other three bring about the same level of performance: between 1% and 7% depending on the application.
Marius Pirvu, Nan Ni, Laxmi N. Bhuyan
IPDPS2
1999 The Impact of Link Arbitration on Switch Performance
abstract
Switch design for interconnection networks plays an important role in the overall performance of multiprocessors and computer networks. In this paper we study the impact of one parameter in the switch design space, link arbitration. We demonstrate that link arbitration can be a determining factor in the performance of current networks. Moreover, we expect increased research focus on arbitration techniques to become a trend in the future, as switch architectures evolve towards increasing the number of virtual channels and input ports. In the context of a state-of-the-art switch design we use both synthetic workload and execution driven simulations to compare several arbitration policies. Furthermore, we devise a new arbitration method, Look-Ahead arbitration. Under heavy traffic conditions the Look-Ahead policy provides important improvements over traditional arbitration schemes without a significant increase in hardware complexity. Also, we propose a priority based policy that is capable of reducing the execution time of parallel applications. Lastly, we enhance the arbitration policies by a supplemental mechanism, virtual channel reservation, intended to alleviate the hot-spot problem.
Marius Pirvu, Laxmi N. Bhuyan, Nan Ni
HPCA3
1998 Circular buffered switch design with wormhole routing and virtual channels
abstract
Switch design for interconnection networks plays an important role in the overall performance of multiprocessors and computer networks. In this paper, a new switch design, namely FC-CB, is proposed that offers low average message latency and high throughput over a wide range of input workloads. The FC-CB switch incorporates wormhole routing and virtual channels with a full crossbar connection. Its structure is based on a novel circular buffer design with dynamic allocation. We have performed extensive simulations to compare its performance with other alternatives. Our results show that the proposed design is superior in terms of latency and throughput, especially for heavy input traffic rate and low buffer space.
Nan Ni, Marius Pirvu, Laxmi N. Bhuyan
ICCD1