Modern FPGA System-on-Chips (SoCs) embed large FPGA logics capable of hosting multiple hardware accelerators. Typically, hardware accelerators require direct access to the shared DRAM memory for reaching the high performance demanded by modern applications. In commercial FPGA SoCs, this goal is achieved by interconnecting the hardware accelerators on an interconnect based on AMBA AXI, which is the de-facto industrial standard for on-chip communications. The AXI standard provides great flexibility in the definition of the network topology. Nevertheless, such flexibility generates a significant unpredictability when attempting to bound the hardware accelerators’ response time when executing under contention. This work focus on bounding the worst-case memory access time of hardware accelerators deployed on commercial FPGA SoCs. We propose a modeling and analysis technique to bound the response time of the hardware accelerators and evaluate the schedulability of a system applicable to arbitrary AXI-based bus structures deployed on FPGA SoCs. Our results are validated on real execution traces collected on two popular FPGA SoCs belonging to the Xilinx ZYNQ-7000 and Zynq-Ultrascale+ families and by simulated results.

This article proposes a technique for optimizing the timing performance and the resource consumption of hardware accelerators for deep neural network (DNN) inference on FPGA-based system-on-chips (SoC). When required, the accelerators are decomposed into chunks, each exploiting at best the available FPGA area, and dynamic partial reconfiguration (DPR) is leveraged to schedule such chunks at run-time. To this end, the article presents accurate models of the resource consumption and timing of DNN accelerators provided by the Xilinx FINN framework. The models are then used to formulate an optimization problem that computes the optimal decomposition of DNN accelerators (and their configuration) by minimizing the inference time while ensuring area constraints on the FPGA. Experimental results on Zynq-7000 platforms demonstrate that the proposed technique provides consistent improvements with respect to both stock configurations of the accelerators and other configurations that can be obtained with a static FPGA allocation.

FPGA System-on-Chips (SoCs) are heterogeneous platforms that combine general-purpose processors with a field-programmable gate array (FPGA) fabric. The FPGA fabric is composed of a programmable logic in which hardware accelerators can be deployed to accelerate the execution of specific functionality. The main source of unpredictability when bounding the execution times of hardware accelerators pertains the access to the shared memories via the on-chip bus. This work is focused on bounding the worst-case bus contention experienced by the hardware accelerators deployed in the FPGA fabric. To this end, this work considers the AMBA AXI bus, which is the de-facto standard communication interface used in most the commercial off-the-shelf (COTS) FPGA SoCs, and presents an analysis technique to bound the response times of hardware accelerators implemented on such platforms. A fine-grained modeling of the AXI bus and AXI interconnects is first provided. Then, contention delays are studied under hierarchical bus infrastructures with arbitrary depths. Experimental results are finally presented to validate the proposed model with execution traces on two modern FPGA-based SoC produced by Xilinx (Zynq-7000 and Zynq-Ultrascale+ families) and to assess the performance of the proposed analysis.

Hardware platforms for real-time embedded systems are evolving towards heterogeneous architectures comprising different types of processing cores and dedicated hardware accelerators, which can be implemented on silicon or dynamically deployed on FPGA fabric. Such accelerators typically access a shared memory to exchange a significant amount of data with other processing elements. Existing COTS solutions focus on maximizing the overall throughput of the system, rather than guaranteeing the timing constraints of individual hardware accelerators. This paper presents the AXI budgeting unit (ABU), a hardware-based solution to implement a bandwidth reservation mechanism on top of the AMBA AXI standard infrastructure for hardware accelerators deployed on FPGAs. An accurate and tractable model, as well as the corresponding analysis, are also proposed to bound the response time of hardware accelerators in the presence of ABUs, in order to verify whether they can complete before their deadlines. Finally, a set of experiments are reported to evaluate the proposed approach on a state-of-the-art platform, namely the Zynq-7020 by Xilinx. The resource consumption of the ABU has been quantified to be less than 1% of the total FPGA resources of the Zynq-7020.

Over the last years convolutional neural networks (CNNs) have shown remarkable results in different image classification tasks, including medical imaging. One area that has been less explored with CNNs is Positron Emission Tomography (PET). Fluorodeoxyglucose Positron Emission Tomography (FDG-PET) is a PET technique employed to obtain a representation of brain metabolic function. In this study we employed 3D CNNs in FDG-PET brain images with the purpose of discriminating patients diagnosed with Parkinson’s disease (PD) from controls. We employed Scaled Subprofile Modeling using Principal Component Analysis as a preprocessing step to focus on specific brain regions and limit the number of voxels that are used as input for the CNNs, thereby increasing the signal-to-noise ratio in our data. We performed hyperparameter optimization on three CNN architectures to estimate the classification accuracy of the networks on new data. The best performance that we obtained was [Formula: see text] and area under the receiver operating characteristic curve [Formula: see text] on the test set. We believe that, with larger datasets, PD patients could be reliably distinguished from controls by FDG-PET scans alone and that this technique could be applied to more clinically challenging tasks, like the differential diagnosis of neurological disorders with similar symptoms, such as PD, Progressive Supranuclear Palsy (PSP) and Multiple System Atrophy (MSA).

AMBA AXI is a popular bus protocol that is widely adopted as the medium to exchange data in field-programmable gate array system-on-chips (FPGA SoCs). The AXI protocol does not specify how conflicting transactions are arbitrated and hence the design of bus arbiters is left to the vendors that adopt AXI. Typically, a round-robin arbitration is implemented to ensure a fair access to the bus by the master nodes, as for the popular SoCs by Xilinx. This paper addresses a critical issue that can arise when adopting the AXI protocol under round-robin arbitration; specifically, in the presence of bus transactions with heterogeneous burst sizes. First, it is shown that a completely unfair bandwidth distribution can be achieved under some configurations, making possible to arbitrarily decrease the bus bandwidth of a target master node. This issue poses serious performance, safety, and security concerns. Second, a low-latency (one clock cycle) module named AXI burst equalizer (ABE) is proposed to restore fairness. Our investigations and proposals are supported by implementations and tests upon three modern SoCs. Experimental results are reported to confirm the existence of the issue and assess the effectiveness of the ABE with bus traffic generators and hardware accelerators from the Xilinx’s IP library.

Computing platforms are evolving towards heterogeneous architectures including processors of different types and field programmable gate arrays (FPGAs), used as hardware accelerators for speeding up specific functions. The increasing capacity and performance of modern FPGAs, with their partial reconfiguration capabilities, have made them attractive in several application domains, including space applications.This paper proposes a framework for supporting the development of safety-critical real-time systems that exploit hardware accelerators developed through FPGAs with dynamic partial reconfiguration capabilities.A model is first presented and then used to derive a response-time analysis to verify the schedulability of a real-time task set under given constraints and assumptions. Although the analysis is based on a generic model, the proposed framework has been conceived to account for several real-world constraints present on today's platforms and has been practically validated on the Zynq platform, showing that it can actually be supported by state-of-the-art technologies. Finally, a number of experiments are reported to evaluate the worst-case performance of the proposed approach on synthetic workload.

Abstract The authors describe a flexible model and a system for content‐based image retrieval of objects' shapes. Flexibility is intended as the possibility of customizing the system behavior to the user's needs and perceptions. This is achieved by allowing users to modify the retrieval function. The system implementing this model uses multiple representations to characterize some macroscopic characteristics of the objects shapes. Specifically, the shape indexes describe the global features of the object's contour (represented by the Fourier coefficients), the contour's irregularities (represented by the multifractal spectrum), and the presence of concavities and convexities (represented by the contour scale space distribution). During a query formulation, the user can specify both the preference for the macroscopic shape aspects that he or she considers meaningful for the retrieval, and the desired level of accuracy of the matching, which means that the visual query shape must be considered with a given tolerance in representing the desired shapes. The evaluation experiments showed that this system can be suited to different retrieval behaviors, and that, generally, the combination of the multiple shape representations increases both recall and precision with respect to the application of any single representation.

Multisource spatial data fusion strategies have generally to cope with distinct kinds of uncertainty, deriving by both the trust of the source, the imperfection of the spatial data, and the vagueness of the fusion strategy itself. In this paper we propose a consensual fusion that allows to flexibly model several fusion strategies ranging from a risk-taking to a risk-adverse attitude, and capable to cope with both data imprecision and uncertainty and source reliability. Uncertainty and imprecision in spatial data is represented by associating a fuzzy value with each spatial unit. The fusion function has a quantifier-guided nature reflecting the concept of a fuzzy majority and works on imprecise values to compute an imprecise result. It is formalized by a generalized OWA operator defined in the paper for aggregating imprecise values with distinct importance. The consensual fusion works so that the greater the trust score of the source and its agreement with the other sources, the more influent (important) is the data from the source in determining the consensual values. Further, when the data are affected by uncertainty one can require to fuse them so as to compute a result affected by at most a given maximum uncertainty level.

This poster overviews the main characteristics of a flexible retrieval systems of shapes present in binary images and discusses some evaluation results. The system applies multiple indexing criteria of the shapes synthesizing distinct characteristics such as global features of the objects contour (Fourier Coefficients), boundary irregularities (Multifractal Spectrum), presence of concavities and convexities on the boundary (Contour Scale Space distribution). The system is flexible since it allows customizing the retrieval function to fit an application need. The query is a binary image containing the desired shape and a set of parameters specifying the distinct importance of the shape characteristics that must be taken into account to evaluate the relevance of the retrieved shapes. The retrieval function is then defined as a Flexible Multicriteria fusion Function producing ranked results. The evaluation experiments showed that this system can be suited to different retrieval purposes, and that generally the combination of the distinct shape indexing criteria increases both Recall and Precision with respect to the application of any single indexing criterion alone.