Approximate computing is a promising approach for high-performance, and low-energy computation in inherently error-tolerant applications. This paper proposes an approximate adder comprising a constant-truncation block in the least significant part and several non-overlapping summation blocks in the more significant parts of the adder. The carry-in of each block is supplied using the most significant bit of one of the input operands from the earlier block. In the most significant block, two more-precise approaches are used to generate candidate values for the carry-in. The final value of the carry-in for this block is selected based on the values of the input operands. In fact, the proposed approximate adder is input-aware, and dynamically adjusts its operation in one or two cycles to improve accuracy while limiting the average delay. The experimental results indicate that the proposed adder has a better quality-effort tradeoff than state-of-the-art approximate adders. Different configurations of the proposed adder improve delay, energy, and the energy-delay product (EDP) by 78%, 72%, and 87%, respectively, when compared to state-of-the-art approximate adders, all without any loss in accuracy. Additionally, the efficiency of the proposed adder is confirmed in both image dithering and stock price prediction through regression.

In response to reliability challenges of new systems being built, we are proposing a scalable Self-Test architecture for many-core processor systems. This BIST architecture periodically distributes test stimuli among identical processing cores in a many-core processor system, suspends normal operation of individual processing cores, applies test, detects faulty cores, and removes them from the system if any are found faulty. Test is continuously performed without any perceptible down-time to the end-user, realizing a many-core processor system with self-healing capability.

A possible solution to the reliability challenges of new fabrication technologies is self-test and self-reconfiguration with no or limited external control. This necessitates the inclusion of mechanisms for detection, recovery and reconfiguration, providing the chip with self-healing capability. While appropriate mechanisms for system recovery and reconfiguration exist, detection remains to be a challenge in realization of self-healing and graceful degradable many-core processors. In this paper we propose a scalable test architecture to distribute test stimuli among homogeneous processing cores in a many-core processor. We have incorporated test infrastructure in the architecture that periodically suspends normal operation of processing cores and applies test to them. This procedure is performed in an online fashion without any downtime visible to the end user. Our proposed fault detection mechanism can be accompanied with appropriate recovery and reconfiguration techniques in order to realize a many-core processor with self-healing capability.

Extending instruction set architecture (ISA) of embedded processors is an effective way to enhance performance and energy efficiency. The typical approaches for identifying custom instructions (CIs) limit the maximum number of input and output (I/O) operands to the available register file port. Recently, there are several work that explore CI candidates without imposing a limit on the number of input and output operands. In this paper, we present a new algorithm based on Particle Swarm Optimization (PSO) to identify CIs within a given data flow graph (DFG) and evaluate it for both categories of CI identification approaches (with and without I/O constrains). By novel evolving strategy, we enhance the quality of the results in our partitioning algorithm. Experimental results show that in most cases CI identification with I/O constraints based on PSO finds better or the same CIs in terms of performance compared to genetic algorithm (GA)[1] and ISEGEN [2] (96% and 90%, respectively). Comparing our proposed algorithm with [12] and [13] reveals that ours has a shorter run-time several order of magnitudes for large DFGs and is independent of the number of forbidden nodes. Moreover, we propose a modified version of PSO called Wrapper PSO that is up to 100× and 500× faster than GA and ISEGEN in large DFGs, respectively.