This paper presents a 13.56MHz active rectifier used in a wireless power transfer system for implantable medical devices that employs digital-to-time converters in replacing analog comparators to generate delay-compensated gate control signals for the power transistors. The low-power digital controller employs a successive approximation register (SAR) to generate digital codes for delay compensation, achieving zero-voltage switching and eliminating reverse conduction loss. Fabricated in a standard 65nm CMOS process, the proposed rectifier has an active area of 0.02mm2. The quiescent power is$13.6\mu $W, 15 times lower than the traditional design. The power transfer efficiency is maintained above 90% from 3mW to 40mW with maximum efficiency of 95% at 16mW. Under light load condition, the proposed design achieves more than 20% efficiency enhancement compared to the rectifier without delay compensation.

A 112-Gb/s single-ended (SE) four-level pulse amplitude modulation (PAM-4) transceiver front-end for the reach-extension module in long-reach (LR) link is proposed. The receiver front-end features an SE-to-differential (S2D) amplifier and a continuous-time linear equalizer (CTLE). Asymmetric inductive peaking, compensation capacitance, and current blending techniques are employed in S2D to eliminate the mismatch at the pseudo-differential outputs. A compact and peaking-enhanced CTLE is achieved by the inductor reused technique. The transmitter front-end is based on a differential-to-SE (D2S) driver where the negative capacitance technique is proposed to extend its bandwidth. Fabricated in 130-nm SiGe BiCMOS technology, our SE transceiver front-end demonstrates a data rate of 112-Gb/s PAM-4 at a 20-dB channel loss with an FoM of 0.09 pJ/bit/dB and BER of$3.21e$-4.

This paper presents a high-efficiency continuous-output-current buck-boost (COCBB) converter with a single buck-boost mode operation. The proposed COCBB comprises one flying capacitor ($\mathbf {C}_{\mathbf {F}}$), one power inductor ($\mathbf {L}$), and five power switches ($\mathbf {S}_{\mathbf {1}}$to$\mathbf {S}_{\mathbf {5}}$). With the help of a flying capacitor, the proposed COCBB converter allows its power inductor to continuously deliver output current while achieving a wide conversion ratio range of$\mathbf {D/(1-D)}$, without right-half-plane-zero (RHPZ). With the continuous output current delivery, the circuit exhibits a small output voltage ripple, good transient response and high efficiency. We employ a double clock timing (DCT) control method to obtain a smooth controller-mode transition between the DCT control and pulse-width-modulation (PWM) control for different load conditions. Fabricated in$0.18\mu \text{m}$CMOS, the prototype chip regulates an output voltage of 1.6 V from a 1.4 V to 1.8 V input range and revealing an undershoot/overshoot of 90/30 mV under the load transient steps between$100\mu \text{A}$and 900mA. The measured output ripple is only 10 mV with a loading current of 400 mA. Also, the converter manifests a peak efficiency and a current density of 95.5% and 0.46 A/mm2, respectively.

This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to periodically realign the clock phase to the rising edge of data. The frequency information is extracted by comparing the rising edge of the data and the clock after aligning the phase using a bang-bang phase detector (BBPD). Additionally, a low power injection-locked two-stage ring digitally controlled oscillator (ILDCO) is employed to provide four-phase quadrature clock and significantly reduce the power consumption. Based on the proposed architecture, the fabricated CDR consumes only 5.8 mW from a 0.9 V supply, while being able to extract the clock signal from 6.15 to 10.9 Gb/s input data with a measured jitter tolerance (JTOL) of 0.15 UIpp at the highest frequency, indicating that the CDR meets the OC-192 mask. Furthermore, the proposed CDR demonstrates a substantial improvement in the power efficiency of 0.58 pJ/bit.

A Power-area-efficient output-capacitorless low- dropout (OCL-LDO) regulator with fast transient response is presented in this paper. The proposed technique permits the regulator to achieve small undershoot (overshoot) when the load steps up (down) and consumes little extra power. The proposed LDO regulator has been implemented and fabricated in a 0.18- μm CMOS process. It occupies an active area of0.0071mm2. The simulated results have shown that the proposed circuit consumes a quiescent current of 0.7 μ at no load, regulating the output at 0.7 V from a voltage supply of 0.9 V. The simulated transient output voltage is 47 mV when load current is stepped from 1 mA to 20 mA in 400 ns with Cl=3D10 pF. Meanwhile, this circuit shows a good of flgure-of-merit (FOM).

A CMOS sub-bandgap voltage reference (sub-BGR) with single BJT and two resistors is presented in this paper. The proposed sub-BGR structure generates the complementary-to-absolute-temperature (CTAT) voltage not only occupying small chip area and consuming nA-level current, but also achieving low sensitivity to the current mirror mismatches. The CTAT voltage is a scaled emitter-base voltage of a BJT and the proportional-to-absolute-temperature (PTAT) voltage is based on the stacking of ΔVGS of sub-threshold MOSFETs. The proposed sub-BGR circuit is implemented in a standard 0.18μm CMOS process, and the active area is 0.059 mm2. The measured results show that the sub-BGR circuit can work with a supply voltage down to 0.9 V and the power consumption is only 66 nW. An average TC of 22.7 ppm/°C with a temperature range of -40 °C ~125 °C and a line sensitivity of 0.059%/V are achieved.

Trans-inductor can be applied in a transient enhancement topology that uses the secondary windings of transformers to connect each phase of a multi-phase voltage regulator. The connection makes all the phases have a response when there is a load transient. Based on this, the resultant transinductor voltage regulator (TLVR) can achieve a significantly improved current slew rate. The current ripple maintains reasonable for each phase, making the design feasible to implement. In this paper, analysis of TLVR is presented and verified. For an eight-phase TLVR with COT, the current slew rate can be improved by 5.041 times in one case. It can reduce the undershoot from 50 mV to 17 mV for a load step from 40 A to 360 A in 160 ns. Overall, TLVR is a very suitable topology to be used in server CPU applications with extremely large load current slew rate.

A 0.6-V 100-mA fully-integrated digital low-dropout regulator (DLDO) with adaptive current step size control is presented in this paper. By dividing the main power PMOSs into ten blocks with different unit-cell sizes, the proposed DLDO can turn-on/-off small power PMOSs in light load and large ones in heavy load conditions. High regulation accuracy in a wide load range and fast transient response are hence achieved. In addition, an auxiliary power MOS block, which consists of both PMOS and NMOS transistors, is adopted to eliminate the limit cycle oscillation (LCO) in light load condition and to further accelerate the response speed. The proposed DLDO is fabricated in a 65-nm low-power CMOS technology with an active area of 0.17 mm2including an on-chip output capacitor of 1nF. The measured undershoot and overshoot voltages are only 53 mV and 37 mV, respectively, when the load current changes between 0 and 100 mA. The quiescent current is 34.6 μα, while the maximum current efficiency is 99.96%.

A transient-enhanced output-capacitor-free low-dropout regulator (LDR) based on dynamic Miller compensation (DMC) is presented in this brief. By utilizing different Miller capacitors to compensate the LDR at different load ranges, the proposed DMC technique can extend the loop bandwidth and enhance the transient performances. The DMC scheme is simple and effective. A proof-of-concept LDR with DMC is designed in a 0.18-μm CMOS process. It has a 100-mA maximum load capability with a quiescent current of 8.5 μA. Measurement results show that the output undershoot/overshoot and recovery time of the proposed LDR with DMC are only 38 mV/0.4 μs and 37 mV/1.22 μs when the load current changes between 100 μA and 100 mA, respectively, whereas they are 45 mV/1.3 μs and 200 mV/4.97 μs without DMC. Line transient responses are also significantly improved by the DMC technique.

This paper presents a single-stage wireless charger using a current-mode active rectifier with accurate output current regulation for efficient wireless charging. As we know, the rectifier processes an AC input voltage/current and a pulsing output current which are difficult to be accurately sensed on chip with small area and power overheads. The proposed current sensing technique uses a replica sensing stage in parallel with the main power stage. It consists of two small cross-connected sensing PMOS transistors, a small filtering capacitor, and a dynamic replica load. In addition, by adaptively tuning the delay of the power NMOS driving signal, the charging current is regulated precisely. This single-stage wireless charger operates at 6.78MHz, and is designed in a 0.35μm CMOS process. Simulation results show a minimum 97.5% current regulation accuracy over a 10× (from 100mA to 1A) output-current range. The peak efficiency of 94% is achieved with 4.2W output power.

A low-power CMOS voltage reference with active-feedback frequency compensation is proposed for power-constrained IoT applications whereby power supply ripple rejection (PSRR) performance is critical for the survival of the devices. The proposed voltage reference consists of MOS transistors operating in the sub-threshold region to allow for low-voltage and low-power operations. An active-feedback frequency compensation technique has been used to make the loop stable and improve the PSRR with a very small compensation capacitor while allowing a relatively large output capacitor. The circuit is fabricated in a standard 0.18-μm CMOS process. The measured power consumption is 22nW at 0.7V power supply. The measured temperature coefficient (TC) is 38ppm/°C in a range from -40 to +110°C, and the line regulation is 200μV/V in a supply voltage range of 0.7~2V. The measured PSRR at 10 Hz, 1 kHz, and 100 kHz is -64dB, -56dB, and -52dB, respectively. The active chip area is 0.04mm2.

This brief presents a novel ultralow power CMOS voltage reference (CVR) with only 4.6-nW power consumption. In the proposed CVR circuit, the proportional-to-absolute-temperature voltage is generated by feeding the leakage current of a zero-Vgs nMOS transistor to two diode-connected nMOS transistors in series, both of which are in subthreshold region; while the complementary-to-absolute-temperature voltage is created by using the body diodes of another nMOS transistor. Consequently, low-power operation can be achieved without requiring resistors or bipolar junction transistors, leading to small chip area consumption. The proposed CVR circuit is fabricated in a standard 0.18-μm CMOS process. Measurement results show that the prototype design is capable of providing a 755 mV typical reference voltage with 34 ppm/°C from -15 °C to 140 °C. Moreover, the typical power consumption is only 4.6 nW at room temperature and the active area is only 0.0598 mm2.

This paper presents a 2×VDD-enabled fully-integrated CMOS low-dropout (LDO) regulator with fast transient response for cost-effective SoC power management applications with elevated-VDD supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high-voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate 1×Vdd voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18-μm CMOS process which achieves 3.3~3.6V nominal input, 3.1V nominal output and 100mA loading capability with all the transistors being 1.8V MOSFETs.

A low-dropout regulator (LDR) using a matching-enhanced error amplifier (ME-EA) and a multi-threshold-controlled unity-gain buffer (MTC-UGB) is proposed in this work. With the majority of transistors being high-voltage devices of the process, the regulator tolerates a high in put voltage range, which alleviates the reliability concern caused by low-voltage transistors. The ME-EA allows for tight line and load regulations. The MTC-UGB, by using low-voltage input transistors with locally regulated terminal voltage, enables large loop bandwidth and fast load transient responses without using compensation capacitor or large ESR of the output capacitor for compensation. Fabricated in a 0.13μm CMOS process, the proposed LDR occupies 0.035 mm2of active area and consumes 18 μA of quiescent current and achieves 6 mV of voltage dip for 150 mA of load transient.

A low-dropout regulator (LDR) using an ultra-fast error amplifier (EA) and ultra-fast unity-gain buffer (UGB) is proposed in this paper. By inserting a UGB between the EA and the inverting second stage, the non-dominant poles are pushed to high frequencies to achieve large loading capability and wide loop bandwidth with good stability. High power supply rejection (PSR) up to very high frequencies is hence achieved. Moreover, transient-enhancement techniques employed by the EA and UGB enable very fast load transient responses. The proposed LDR was designed in a 0.13μm mixed-mode CMOS process. Simulation results show that the quiescent current is 4μA and it achieves 7mV voltage dip for a load current step of 400mA with 1ns edge times. The PSR for all load range are better than -28dB at 10MHz and -9dB at 50MHz, respectively.

In this work, an output-capacitor-free (OCF) low-dropout regulator (LDR) employing fully differential input stage is proposed. By using a fully differential input stage, the proposed OCF LDR is able to improve the transient responses without the help of any additional transient boosting circuitry. This design is stabilized with a 0.37pF compensation capacitor. It is able to provide a maximum load current of 100mA at 0.7V to 1.2V supply with less than 200mV dropout voltage. Implemented in 0.13μm CMOS technology, it consumes a quiescent current of 4μA and occupies an active area of 0.0132mm2.

An output-capacitor-free adaptively biased low-dropout regulator with transient enhancement (ABTE LDR) is proposed. Techniques of Q-reduction compensation, adaptive biasing, and transient enhancement achieve low-voltage high-precision regulation with low quiescent current consumption while significantly improving the line and load transient responses and power supply rejections. The features of the ABTE LDR are experimentally verified by a 0.35-μm CMOS prototype.

This paper presents an output-capacitor-free adaptively biased low-dropout regulator with sub-threshold undershoot-reduction (ABSTUR LDR) for SoC power management applications. Techniques of Q-reduction compensation and adaptive biasing (AB) are employed to achieve low-voltage high-recision regulation with enhanced loop bandwidth while maintaining low quiescent current and high current efficiency. A symmetrically matched current-voltage mirror is used to implement the AB scheme, enabling an accurate load current sensing even with the pass transistor working in the linear region that is beneficial for chip-area saving. The dedicated STUR circuit, which is low-voltage compatible and consumes very low current in the steady state, is inserted to momentarily increase the gate discharging current of the pass transistor when the LDR output has a large undershoot due to a large step up of the load current. Features of the proposed ABSTUR LDR are experimentally verified by a prototype fabricated in a standard 0.35-μm CMOS process.

A high-precision low-voltage low dropout regulator (LDR) using adaptive biasing to extend the loop bandwidth is proposed for system-on-chip power management applications. The multi-stage output-capacitor-free LDR is stabilized by miller compensation and Q-reduction technique to reduce the requirement of minimum load current. By using direct current feedback from a simple current mirror, the adaptively-biased LDR achieves higher loop bandwidth, faster load and line transient responses, higher power supply rejection and lower output impedance. The load and line regulations are also improved. Designed in a standard 0.35µm CMOS technology (Vtn≈ 0.52V and Vtp≈ −0.72V ), the 1.2V input 1.0V output LDR requires a minimum load current of 50µA and delivers a maximum current of 100mA. Both theoretical analysis and simulation results are presented to demonstrate the advantages of the proposed LDR.