Gate-level clock gating is to synthesize clock gating structure (grouping of registers and extracting gating function of each group) from a netlist. We note that a simpler gating function can be derived from a cyclic logic path that connects the input and output of the same register. Another benefit comes from the fact that simplifying the cyclic paths using the derived gating function as don't-care is straightforward. A key problem in this approach is to extract a set of cyclic paths of each register, such that power consumption is minimized and circuit timing is left intact. Experiments demonstrate that power consumption is reduced by 49% on average of test circuits (with initial ungated netlist as a reference), while a sample previous gate-level clock gating achieves 34% of power saving.

Clock tree synthesis (CTS) is performed in a very late stage of design. Power estimation, therefore, can only be done without clock network in most design stages, which is not desirable given that clock network is usually the biggest power consumer. One may adopt an estimate of clock power, but its dynamic nature arising from clock gating brings a challenge in the estimation of clock power in a pre-CTS design. In this paper, we (1) estimate the clock tree components (clock gating cells (CGCs) and buffers as well as their wireloads) by using artificial neural networks (ANNs) and (2) use them while gating or ungating of each CGC is identified from a netlist cycle-by-cycle to estimate transient clock power consumption. Experiments with a few test circuits indicate that (1) the estimation of clock tree components causes the error of 13% on average, and (2) the estimated clock power waveform is very close to the actual waveform with average error of only 2%.

The area required by combinational logic of a sequential circuit based on standard flip-flops can be reduced by identifying subcircuits that are identical. Pairs of matching subcircuits can then be replaced by circuits in which dual-edge-triggered flip-flops operate on multiplexed data at the rising and falling edges of the clock signal. We show how to modify the Boolean network describing a combinational logic to increase the opportunities for folding, without affecting its function. Experiments with benchmark circuits achieved an average reduction in circuit area of 18%.

Buffer insertion to remove hold violations at multiple process corners is addressed for the first time. The problem is formulated as integer linear programming (ILP); it is combined with circuit partitioning heuristic so that larger circuits can also be handled. A heuristic buffer insertion algorithm is then proposed and compared to ILP, which demonstrates only a slight increase of the number of buffers (2.4% on average). Two additional intuitive methods are implemented to demonstrate why new heuristic algorithm is needed: conventional buffer insertion at each process corner one by one and conventional buffer insertion at all process corners simultaneously followed by combining insertion results.

Gate-level clock gating starts with a netlist, with partial or no gating applied; some flip-flops are then selected for further gating to reduce the circuit's power consumption, and a gating logic of the smallest possible size must then be synthesized. We show how to do this by factored form matching, in which gating functions in factored forms are matched, as far as possible, with factored forms of the Boolean functions of existing combinational nodes in the circuit; additional gates are then introduced, but only for the portion of gating functions that are not matched. Strong matching identifies matches that are explicitly present in the factored forms, and weak matching seeks matches that are implicit in the logic and thus are more difficult to discover. Factored form matching reduces gating logic by an average of 24%, over a few test circuits, for which Boolean division only achieves an average reduction of 8%.

Pulsed-latch circuits, in which latches are triggered by a short pulse, can reduce power consumption as well as increasing performance; and they can largely be designed using conventional computer-aided design tools. We explore the automatic synthesis of clock-gating logic for pulsed-latch circuits in which gating is implemented by enabling and disabling several pulse generators. The key problem is to arrange that each group of latches contains physically close latches, so that a short pulse from a pulse generator is delivered safely, and to ensure that the latches in a group have similar Boolean gating conditions because their clock is gated and ungated together. The resulting gating conditions should be implemented using as little extra logic as possible; for this purpose we rely on Boolean division, with an internal node of existing logic being used as the divisor. The proposed clock gating synthesis is assessed in 45-nm technology.

A pulsed-latch is an ideal sequencing element for low-power ASIC designs due to its smaller capacitance and simple timing model. Clock gating of pulsed-latch circuits can be realized by gating a pulse generator (or pulser), which we call pulser gating. The problem of pulser gating synthesis is formulated for the first time. Given a gate-level netlist with location of latches, we first extract the gating function of each latch; the gating functions are merged to reduce the amount of extra logic while gating probability is not sacrificed too much. We also have to take account of proximity of latches, because a pulser, which is gated by merged gating function, and its latches have to be physically close for safe delivery of pulse. The heuristic algorithm that considers all three factors (similarity of gating functions, literal count to implement gating functions, and proximity of latches) is proposed and assessed in terms of power saving and area using 45-nm technology.

A floorplanning has a potential to reduce chip temperature due to the conductive nature of heat. If floorplan optimization, which is usually based on simulated annealing, is employed to reduce temperature, its evaluation should be done extremely fast with high accuracy. A new thermal index, named thermal signature, is proposed. It approximates the temperature calculation, which is done by taking the product of Green's function and power density integrated over space. The correlation coefficient between thermal signature and temperature is shown to be quite high, more than 0.7 in many examples. A floorplanner that uses thermal signature is constructed and assessed using real design examples in 32-nm technology. It produces a floorplan whose maximum temperature is 11.4°C smaller than that of standard floorplan, on average, in reasonable amount of runtime.