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Jacobo Lobeiras

dblp:03/9378 · also Jacobo Lobeiras Blanco · DBLP profile ↗
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6ranked-venue papers
4as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
High-performance computing · 48% GPUs and heterogeneous computing · 37% Parallel and multicore computing · 15%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing
fast fourier transform
0.312018
Solving Large Problem Sizes of Index-Digit Algorithms on GPU: FFT and Tridiagonal System Solvers · IEEE Trans. Computers 2018
GPUs and heterogeneous computing
GPU computing
0.312018
Solving Large Problem Sizes of Index-Digit Algorithms on GPU: FFT and Tridiagonal System Solvers · IEEE Trans. Computers 2018
Parallel and multicore computing › parallel algorithms › PRAM algorithms
parallel prefix computation
0.312018
Solving Large Problem Sizes of Index-Digit Algorithms on GPU: FFT and Tridiagonal System Solvers · IEEE Trans. Computers 2018
High-performance computing
scientific computing systems
0.312018
Solving Large Problem Sizes of Index-Digit Algorithms on GPU: FFT and Tridiagonal System Solvers · IEEE Trans. Computers 2018
High-performance computing › sparse linear solver
tridiagonal solver
0.312018
Solving Large Problem Sizes of Index-Digit Algorithms on GPU: FFT and Tridiagonal System Solvers · IEEE Trans. Computers 2018
GPUs and heterogeneous computing › GPU programming
CUDA
0.212016
Designing Efficient Index-Digit Algorithms for CUDA GPU Architectures · IEEE Trans. Parallel Distributed Syst. 2016
GPUs and heterogeneous computing › GPU computing
GPU algorithms
0.212016
Designing Efficient Index-Digit Algorithms for CUDA GPU Architectures · IEEE Trans. Parallel Distributed Syst. 2016
High-performance computing › performance optimization
shared memory optimization
0.112018
Solving Large Problem Sizes of Index-Digit Algorithms on GPU: FFT and Tridiagonal System Solvers · IEEE Trans. Computers 2018

Methods — techniques the papers use, named apart from their topics

tuning strategies · 0.3multi-stage algorithm · 0.3performance tuning · 0.2operator string manipulation · 0.2
YearPublicationVenuePosition
2018 Solving Large Problem Sizes of Index-Digit Algorithms on GPU: FFT and Tridiagonal System Solvers
abstract
Current Graphics Processing Units (GPUs) are capable of obtaining high computational performance in scientific applications. Nevertheless, programmers have to use suitable parallel algorithms for these architectures and usually have to consider optimization techniques in the implementation in order to achieve said performance. There are many efficient proposals for limited-size problems which fit directly in the shared memory of CUDA GPUs, however, there are few GPU proposals that tackle the design of efficient algorithms for large problem sizes that exceed shared memory storage capacity. In this work, we present a tuning strategy that addresses this problem for some parallel prefix algorithms that can be represented according to a set of common permutations of the digits of each of its element indices [1], denoted as Index-Digit (ID) algorithms. Specifically, our strategy has been applied to develop flexible Multi-Stage (MS) algorithms for the Fast Fourier Transform (FFT) algorithm (MS-ID-FFT) and a tridiagonal system solver (MS-ID-TS) on the GPU. The resulting implementation is compact and outperforms other well-known and commonly used state-of-the-art libraries, with an improvement of up to 1.47x with respect to NVIDIA's complex CUFFT, and up to 33.2x in comparison with NVIDIA's CUSPARSE for real data tridiagonal systems.
Adrián Pérez Diéguez, Margarita Amor, Jacobo Lobeiras, Ramón Doallo
IEEE Trans. Computers3
2016 Designing Efficient Index-Digit Algorithms for CUDA GPU Architectures
abstract
Modern graphics processing units (GPUs) offer very high computing power at relatively low cost. Nevertheless, designing efficient algorithms for the GPUs normally requires additional time and effort, even for experienced programmers. In this work we present a tuning methodology that allows the design for CUDA-enabled GPU architectures of index-digit algorithms, that is, algorithms where the data movement can be described as the permutations of the digits comprising the indices of the data elements. This methodology, based on two-stages identified as GPU resource analysis and operators string manipulation, is applied to FFT and tridiagonal systems solver algorithms, analyzing the performance features and the most adequate solutions. The resulting implementation is compact and outperforms other well-known and commonly used state-of-the-art libraries, with an improvement of up to 19.2 percent over NVIDIA's complex CUFFT , and more than 3000 percent over the NVIDIA'sCUDPP for real data tridiagonal systems.
Jacobo Lobeiras, Margarita Amor, Ramón Doallo
IEEE Trans. Parallel Distributed Syst.1
2013 SPLG: A Tuned Signal Processing Library for GPU Architectures
abstract
In order to increase the efficiency of existing software many works are incorporating GPU processing. However, despite the current advances in GPU languages and tools, taking advantage of their parallel architecture is still far more complex than programming standard multi-core CPUs. Performance profiling and analysis of known applications provides a useful insight of the hardware architecture and memory hierarchy. Afterwards, this analysis can be used to identify potential bottlenecks and tune other software so it can make a more efficient usage of the available resources. In this work we implement a small signal processing library which will be used to characterize the performance of most recent NVIDIA GPU architectures. The methodology used in our signal processing library is based on a series of building blocks that enable us to easily design several well-known algorithms with little effort. The library was built paying special attention to flexibility and adaptability. In this work we also show how a generic approach can be used to easily design these GPU algorithms while obtaining competitive performance, which results specially interesting from the productivity standpoint.
Jacobo Lobeiras, Margarita Amor, Ramón Doallo
SBAC-PAD1
2013 A multi-GPU shallow-water simulation with transport of contaminants
abstract
SUMMARY This work presents cost‐effective multi‐graphics processing unit (GPU) parallel implementations of a finite‐volume numerical scheme for solving pollutant transport problems in bidimensional domains. The fluid is modeled by 2D shallow‐water equations, whereas the transport of pollutant is modeled by a transport equation. The 2D domain is discretized using a first‐order Roe finite‐volume scheme. Specifically, this paper presents multi‐GPU implementations of both a solution that exploits recomputation on the GPU and an optimized solution that is based on a ghost cell decoupling approach. Our multi‐GPU implementations have been optimized using nonblocking communications, overlapping communications and computations and the application of ghost cell expansion to minimize communications. The fastest one reached a speedup of 78 × using four GPUs on an InfiniBand network with respect to a parallel execution on a multicore CPU with six cores and two‐way hyperthreading per core. Such performance, measured using a realistic problem, enabled the calculation of solutions not only in real time but also in orders of magnitude faster than the simulated time.Copyright © 2012 John Wiley & Sons, Ltd.
Moisés Viñas, Jacobo Lobeiras, Basilio B. Fraguela, Manuel Arenaz, Margarita Amor, José A. García, Manuel Jesús Castro Díaz, Ramón Doallo
Concurr. Comput. Pract. Exp.2
2013 Influence of memory access patterns to small-scale FFT performance
Jacobo Lobeiras, Margarita Amor, Ramón Doallo
J. Supercomput.1
2011 FFT Implementation on a Streaming Architecture
abstract
Fast Fourier Transform (FFT) is a useful tool for applications requiring signal analysis and processing. However, its high computational cost requires efficient implementations, specially if real time applications are used, where response time is a decisive factor. Thus, the computational cost and wide application range that requires FFT transforms has motivated the research of efficient implementations. Recently, GPU computing is becoming more and more relevant because of their high computational power and low cost, but due to its novelty there is some lack of tools and libraries. In this paper we propose an efficient implementation of the FFT with AMD's Brook+ language. We describe several features and optimization strategies, analyzing the scalability and performance compared to other well-known existing solutions.
Jacobo Lobeiras, Margarita Amor, Ramón Doallo
PDP1