Fully Homomorphic Encryption (FHE) allows one to outsource computation over encrypted data to untrusted servers without worrying about data breaching. Since FHE is known to be extremely computationally intensive, application-specific accelerators emerged as a powerful solution to narrow the performance gap. Nevertheless, due to the increasing complexities in FHE schemes per se and multi-scheme FHE algorithm designs in end-to-end privacy-preserving tasks, existing FHE accelerators often face the challenges of low hardware utilization rates and insufficient memory bandwidth. In this work, we present APACHE, a layered near-memory computing hierarchy tailored for multi-scheme FHE acceleration. By closely inspecting the data flow across different FHE schemes, we propose a layered near-memory computing architecture with fine-grained functional unit design to significantly enhance the utilization rates of both computational resources and memory bandwidth. In addition, we propose a multi-scheme operator compiler to efficiently schedule high-level FHE computations across lower-level functional units. In the experiment, we evaluated APACHE in various FHE applications, such as Lola MNIST, HELR, fully packed bootstrapping, and fully homomorphic processors. The results illustrate that APACHE outperforms state-of-the-art ASIC FHE accelerators by 10.63× to 35.47× over a variety of operator and application benchmarks.

Software-defined Networking (SDN) is an emerging network architecture. The decoupled data and control plane provide flexible manageability and programmability to the network. One of the core components in SDN switches to direct traffic forwarding is the flow table, which is usually stored in the ternary content addressable memory (TCAM) with limited space and high power consumption, making the flow table a potential target for attacks. This paper examines the Low-Rate Flow Table Overflow (LRFTO) attacks, which fill the flow table and render it unavailable by continuously sending attack rules to occupy the space. We propose a quantitative model of LRFTO attacks to describe the attack behavior, analyze its difference from legitimate traffic, and summarize some key aspects and features to distinguish attack rules from legitimate rules. We also propose LRFTO-ADMS, a system that utilizes machine learning-based classification as its core to evict suspicious rules, thereby ensuring flow table availability. Experimental results show that the threat model can adapt correctly to the network environment. The proposed LRFTO-ADMS can evict attack rules with an accuracy of more than 95% and low overhead while protecting the flow table and the legitimate rules from being unavailable.

DNS recursive resolver plays the role of intermediary agent in domain name query service, making it easy to observe various DNS flooding attack behaviors. The programmable data plane has promoted innovation in in-band attack detection, but previous work has not concentrated on DNS services, and there are concerns with mistakenly killing benign traffic and low classification accuracy. In this paper, we propose DNSGreen, a comprehensive defense system against bounce-style DNS DDoS attacks in the programmable data plane. DNSGreen discusses flow and packet characteristics under anomalous behavior, employing a “flow-detection and packet-filtering” pattern to ensure effective defense while allowing benign traffic to pass through as much as possible. Furthermore, DNSGreen designs a whitelist collection module, which eliminates the need to inspect trusted streams in subsequent filtering and thereby reducing the occurrence of false positives. Finally, DNSGreen improves the allocation method of the statistical structure to enhance the accuracy of system alarms. We deploy DNSGreen on BMv2 switches and conduct tests in three attack scenarios, demonstrating that DNSGreen safeguards normal users with excellentF0:5score while filtering attack traffic.

As a vital security primitive, the true random number generator (TRNG) is a mandatory component to build trust roots for any encryption system. However, existing TRNGs suffer from bottlenecks of low throughput and high area-energy consumption. Additionally, the EDA design of TRNG for specific applications remains an unexplored area. To address these issues, in this work, we propose compact and high-throughput TRNGs based on dynamic hybrid, reinforcement strategies, and automated exploration. First, we present a dynamic hybrid entropy unit and reinforcement strategies to provide sufficient randomness. On this basis, we propose a high-efficiency dynamic hybrid TRNG (DH-TRNG) architecture. It exhibits portability to distinct process FPGAs and passes both NIST and AIS-31 tests without any post-processing. The experiments show it incurs only 8 slices with the highest throughput of 670Mbps and 620Mbps on Xilinx Virtex-6 and Artix-7, respectively. Compared to the state-of-the-art TRNGs, DH-TRNG has the highest Throughput/Slices∙ Power with 2.63× increase. In addition, we propose an automated exploration scheme as a preliminary EDA design for TRNG to better apply to resource-constrained scenarios. This scheme automatically explores TRNGs to meet the design requirements and further reduces the hardware overhead, indicating broad application prospects in TRNG automation design. Finally, we apply the proposed DH-TRNG and the results of automated exploration to stochastic computing for edge detection, achieving promising outcomes.

Stochastic computing (SC) generally suffers from long latency. One solution is to apply proper random number sources (RNSs) to generate the bit streams. However, existing RNS designs either have low accuracy or high hardware cost. To address this drawback, motivated by the fact that a uniform spatial distribution generally leads to high accuracy for an SC circuit, we propose a basic architecture to produce a uniform spatial distribution and a further detailed implementation of it. For the implementation, we further propose a method to optimize its hardware cost and an algorithm following a guiding principle to improve its accuracy. The method for hardware cost optimization allows hardware cost reduction while keeping the accuracy. Our experimental results show that the proposed implementation achieves both high accuracy and low hardware cost. For example, compared to a state-of-the-art stochastic number generator design, our design can reduce hardware cost by over 80%, while achieving higher accuracy

The lattice-based digital signature algorithm CRYSTALS-Dilithium has been standardized as ML-DSA following the NIST post-quantum cryptography (PQC) competition. Due to the high computational complexity and data interaction in ML-DSA, its hardware implementation faces problems of large area overhead and low efficiency. This work invokes multiple optimizations to achieve an area-efficient hardware accelerator for ML-DSA. Specifically, we employ a multi-clock strategy in the architecture to maximize module performance and introduce interleaved and dynamic execution techniques to improve parallelism and minimize wait delays between modules. Moreover, several optimized modules are designed to improve the efficiency of the proposed architecture, including a multimodal polynomial arithmetic module, a unified SHA-3 module with preload functionality, and a BRAM-based Usehint module. Compared to the state-of-the-art, our implementation achieves an improvement of$1.21 \sim 4.62 \times $,$1.25 \sim 5.31 \times $, and$1.37 \sim 5.49 \times $in area-time product (ATP) metric at three security strengths, respectively. This establishes our design as the most area-efficient ML-DSA accelerator to date.

The unpredictable inherent error behavior of approximate computing introduces both new security threats and opportunities to design novel security primitives/strategies. This work proposes a methodology that exploits stochastic timing errors of a pipelined datapath caused by voltage scaling to design an optimized processor-based physical unclonable function (PUF) for approximate computing. To verify the effectiveness of this method, a pipelined arithmetic architecture is implemented at a 45 nm technology node, and voltage scaling is applied to extract PUF bits. With reduced supply voltage, harvested PUF bits show increased uniqueness. Moreover, proposed divergent delay path selection based on intermediary error behavior exhibits improved PUF uniqueness vs an unmodified datapath. A design optimization methodology is applied introducing new PUF metrics - gain (G) and performance power ratio (PPR). Using these metrics, the optimum scaled voltage range is identified for enhanced PUF performance. The optimized PUF shows maximum uniqueness of 49%, and reliability of 92% with a temperature range of -20${\circ }$C to 70${\circ }$C. Further, the proposed PUF with approximate computing achieves markedly improved G and PPR relative to the exact case. With better uniqueness, reliability, and low resource utilization, the proposed PUF methodology is highly suitable for securing approximate computing applications.

Software-Defined Network (SDN) revolutionizes traditional network structures by isolating the data plane and the control plane, which offers greater flexibility in managing network resources. Nevertheless, SDN remains vulnerable to certain threats inherited from the traditional network, including Distributed Low-rate Denial-of-Service (DLDoS) attack. This attack is more subtle and harder to detect than traditional Distributed Denial-of-Service (DDoS) attacks, because it employs a lower average attack rate. We design a real-time detection and mitigation system named DOE-DTL specifical for the DLDoS attack in SDN. For the DLDoS attack detection, we utilize Machine-Learning (ML) methods to construct a detection model and introduce it in DOE-DTL. In the construction, we leverage Extreme Learning Machine (ELM) and make a dual optimization using Whale Optimization Algorithm (WOA). For the DLDoS attack mitigation, we use double thresholds to determine the attack sources and make corresponding mitigation rules. DOE-DTL innovatively combines the Programmable Data Plane (PDP) in detection and mitigation, shifting some control plane tasks to the data plane. Performance assessments reveal that DOE-DTL ensures fast, accurate attack identification and low-latency mitigation while maintaining low resource usage.

The decoupling of SDN control plane and data plane allows control to be carried out independently, enhancing the programmability and manageability of the whole network. However, though this new architecture brings convenience for control, it also sets a pool for attacks. Due to the expensive and resource-consumption characteristics, SDN switches usually have a limited ternary content addressable memory to cache the flow rules in the data plane. Attackers can launch a space-consuming attack to maliciously preempt the flow table, forcing switches to reduce the quality of service. Among them, DDoS attacks should be taken seriously, especially the low-rate ones that have a lower attack rate with stronger concealment. In this paper, an architecture named MWD-CFM is proposed to protect against low-rate DDoS attacks in the switch flow tables. Multi-windows work collaboratively to improve detection performance. The feature of flow rules is corrected to do better classification, improving the effectiveness of attack traffic removal. Experiments based on real network topology and datasets are conducted to verify the deployment of MWD-CFM. Results prove that our architecture can greatly reduce the survival time of attack flows and ensure the availability of flow tables for legitimate services.

True random number generators (TRNGs) extract randomness from physical phenomena to produce inherently unpredictable bitstreams. Owing to their strong cryptographic properties, TRNGs are fundamental components for establishing trusted roots in secure systems. However, the throughput of current TRNGs falls short of meeting the increasing demands posed by high-speed encryption and rapidly growing data volumes. To solve this issue, in this article, we propose a multi-channel tetrahedral TRNG (MCT-TRNG) via metastability-enhanced entropy with ultra-high throughput. We first propose a novel entropy source structure of a metastability-enhanced ring oscillator, which extracts randomness in unstable signals by switching transmission paths. Then, we introduce a feedback XOR ring to improve the degree of signal chaos. On this basis, we propose a tetrahedral post-processing structure with four channels to produce independent parallel outputs. The experiments show that the generated random sequences have successfully passed the NIST and AIS-31 tests. The MCT-TRNG incurs only 18 LUTs with a throughput of 2.2 Gbps on Xilinx Artix-7 FPGA. Compared with existing works, our design has the highest throughput, yielding promising application potential.

Intel SGX is susceptible to intra-enclave software vulnerabilities. Existing automated bug-finding methods primarily focus on fuzzing enclave boundaries for SGX applications in simulated, rather than actual hardware-protected enclaves. This limits the ability to identify potential security violations originating from within SGX application code. This paper presents IntraFuzz, the first system that enables efficient fuzzing of SGX applications inside actual hardware enclaves. We evaluated IntraFUZZ with 21 real-world SGX applications, running on Intel Xeon scalable processors with up to 256 GB of enclave page cache. IntraFuzz successfully detected all vulnerabilities in SGX application code previously identified by the state-of-the-art tool EnclaveFuzz, as well as 6 previously undiscovered vulnerabilities. These results highlight the importance of hardware-based fuzzing in securing SGX applications.

Runahead execution is an effective microarchitectural level performance boosting technique. It removes the blocking load instruction with long latency and speculatively executes the subsequent instructions with little pipeline modifications. However, the nature of prefetching data and instructions creates potential security risks similar to Spectre and Meltdown. In this work, we present the first comprehensive analysis of the security implications of runahead execution and report a novel attack, named SPECRUN. SPECRUN exploits the unresolved branch predictions within nested speculative execution during runahead execution. It can manipulate the speculative execution window and hence eliminates the major limitation of Spectre-type attacks: the number of executable transient instructions is limited by the small reorder buffer size. Therefore, SPECRUN can improve the exploitability of transient attacks significantly. To demonstrate this, we implement a proof-of-concept attack that can successfully extract secrets from a victim process.We analyze existing defense techniques and propose new ones against SPECRUN. The effectiveness and overhead of these mitigation mechanisms are carefully discussed to shed light on the security vulnerabilities and defense before the adoption of runahead execution on current and future processors.

Physical Unclonable Functions (PUFs) serve as lightweight hardware security primitives that leverage chip fabrication process variations for key generation and device authentication. However, the lack of reliable Challenge-Response Pairs (CRPs) and unrestricted query capabilities in current PUF-enabled applications introduces security vulnerabilities in resource-constrained devices. This paper introduces a novel Dual-State Analog PUF (DA PUF) design that is capable of operating as either a leakage PUF or an inverter PUF to represent the low-and high-state PUF, respectively. Our proposed Bit Configuration Strategy (BCS) significantly improves the reliability of PUF, achieving a reliability rate exceeding 99.98% in various working environments and voltage conditions. Additionally, the aggregate of reliable bits for both states is 1.88 (for the high state) and 2.13 (for the low state) times greater than that of a singular state. Within a temperature range of -40 to 125∘C, the temperature sensitivity is measured at 0. 000356%/∘C (high state) and 0.000417%/∘C (low state); and within a voltage range of 0.96 to 1.44 V, the voltage sensitivity is recorded at 0.05546%/V (high state) and 0.03342%/V (low state). In addition, we developed a lightweight and secure DA PUF-based authentication protocol that significantly increases the number of possible device certifications. Through the random oracle model, we demonstrate that our proposed protocol meets essential security and resistance requirements. Compared to recent relevant protocols, our approach offers lower computational and communication overhead, making it highly suitable for Internet of Things (IoT) devices.

Plasticity is key to the trainability of neural networks and has long been a focus in the field of brain-inspired research. Currently, neuromorphic networks primarily achieve plasticity through synaptic and myelin structures. However, these two are often studied separately, limiting further enhancement of neuronal node plasticity. This paper proposes a neuron model that incorporates both synapses and myelin, designs the corresponding neuronal circuit, and introduces a method for quantifying its discharge characteristics. Through theoretical analysis, simulations, and physical experiments, we validate the effectiveness of this quantification method. Furthermore, we summarize the formation mechanisms of synaptic and myelin plasticity, clarify the differences in their respective plasticity effects, and use the quantification method to compute the response speed, power consumption, and spike firing frequency of neuronal circuits. We also analyze the impact of synaptic and myelin plasticity and their synergistic effects on these three factors. Results demonstrate that the plasticity of synapses and myelin, as well as their synergistic interaction, can significantly optimize the performance of neuron nodes: the response duration is reduced to 2.9% of its initial value, the energy consumption per spike decreases to 38.4%, and the spike firing frequency increases to 1982.6% of the baseline level. This synergy contributes to improving the computational efficiency and energy management capabilities of neuromorphic networks.

Polynomial multiplication (PM) is the computational bottleneck of lattice-based cryptography, such as post-quantum cryptography (PQC). Designing dedicated hardware accelerators for polynomial multiplication is an effective solution to improve the execution speed. However, current mainstream designs ignore the impact of computing array size, resulting in poor design flexibility and low memory utilization. To address these issues, we propose Meta, a memory-efficient tri-stage PM accelerator. Our proposed tri-stage PM algorithm fuses all isolated substages into a unique stage named fused coefficient-wise multiplication (FCWM), ensuring efficient computation. Meanwhile, in different stages of the algorithm, the circuit of two-dimensional reconfigurable coupled butterfly units (2D-RCBFUs) is fine-grained reconfigured to improve resource utilization. Moreover, the low-complexity memory mapping scheme simplifies the address control logic and reduces the hardware overhead. Meta can efficiently support the PM of an arbitrary power of two, which is impossible for previous designs using a 2D computing array. Compared with the state-of-the-art designs, our Meta demonstrates the best memory utilization, achieving up to$10.0\times $performance improvement.

The Low-Rate Denial of Service (LDoS) attack poses a significant threat to Internet services. Exploiting vulnerabilities in adaptive mechanisms embedded within network protocols, LDoS attacks are covert and exhibit legal behavior, making defense challenging. Existing LDoS attack solutions cannot perform real-time LDoS attack defense at line speed. With the emergence of P4, users can program the per-packet processing logic of the P4 switch, which offers us the chance to propose PLUTO, the first data plane-aware LDoS attack defense system built upon the P4 switch, possessing line-speed execution capacity. To meet the resource constraints of the P4 switch, we propose the time window-based pre-inference strategy to detect LDoS attacks and the time-limited per-flow state management to filter the LDoS attack flows. For the practical deployment, we develop the P4 Function Tool to extend the P4 primitives for more function operations. We also adopt an encoding-based mapping method to deploy the pre-inference model. Furthermore, we develop the async-updated hash table for quickly filtering LDoS attack flows. Compared with the baseline, PLUTO reduces the equal error rate (EER) by 27.96% and the average mitigation response time by 12.749 s, increasing the AUC by 1.83%, the F1 Score by 7.27%, and the Recall by 9.58%.

The TCP protocol’s inherent lack of built-in security mechanisms has rendered it susceptible to various network attacks. Conventional defense approaches face dual challenges: insufficient line-rate processing capacity and impractical online deployment requirements. The emergence of P4-based programmable data planes now enables line-speed traffic processing at the hardware level, creating new opportunities for protocol protection. In this context, we present MARS -a data plane-native TCP abuse detection and mitigation system that synergistically combines the Beaucoup traffic monitoring algorithm with artificial neural network (ANN) based anomaly detection, enhanced by adaptive heuristic mitigation rules. Through comprehensive benchmarking against existing TCP defense mechanisms, our solution demonstrates 12.95% higher throughput maintenance and 25.93% improved congestion window recovery ratio during attack scenarios. Furthermore, the proposed framework establishes several novel evaluation metrics specifically for TCP protocol protection systems.

Rowhammer has drawn much attention from both academia and industry in the past years as rowhammer exploitation poses severe consequences to system security. Since the first comprehensive study of rowhammer in 2014, a number of rowhammer attacks have been demonstrated against dynamic random access memory (DRAM)-based commodity systems to break software confidentiality, integrity and availability. Accordingly, numerous software defenses have been proposed to mitigate rowhammer attacks on commodity systems of either legacy (e.g., DDR3) or recent DRAM (e.g., DDR4). Besides, multiple hardware defenses (e.g., Target Row Refresh) from the industry have been deployed into recent DRAM to eliminate rowhammer, which we categorize as production defenses.

As a core arithmetic operation and security guarantee of Fully Homomorphic Encryption (FHE), Number Theoretic Transform (NTT) of a large degree is the primary source of computational and time overhead. In this paper, we propose a scalable and conflict-free memory mapping algorithm that breaks the memory bound and releases a large amount of on-chip resources. A flexible and no-stall hardware/software pipeline architecture is designed to boost the throughput of NTT/INTT of N = 216 to over 48,543 operations per second with area efficiency, which 4× and 10× speed up the FPGA-based (HPCA'23) and GPU-based (HPCA'23) schemes.

The reliability of physical unclonable function (PUF) has become the biggest challenge for key generation. Existing reliability improvement technologies incur high hardware overhead or testing costs. This paper proposes S2RAM-PUF, a novel, highly reliable and energy-efficient subthreshold SRAM PUF fabricated in 65nm process, with zero bit error rate (BER) across all voltage/temperature corners from 0.5V to 0.8V and from -40°C to 120°C. The 20480 bits generated by the fabricated 5 S2RAM PUF chips pass the NIST 800-22 randomness test and exhibit almost ideal uniqueness with a mean inter-die hamming distance of 0.5007. The total energy per bit is as low as 3.12fJ at 0.5V supply voltage. Both stabilization BER and energy outperform the two state-of-the-art SRAM-type PUFs reported in JSSC 2020 and 2021.

Runahead execution is a continuously evolving microarchitectural technique for processor performance. This paper introduces the first transient execution attack on the runahead execution, called SPECRUN, which exploits the unresolved branch prediction during runahead execution. We show that SPECRUN eliminates the limitation on the number of transient instructions posed by the reorder buffer size, enhancing the exploitability and harmfulness of the attack. We concretely demonstrate a proof-of-concept attack that causes leaking secrets from a victim process, validate the merit of SPECRUN, and design a secure runahead execution scheme. This paper highlights the need to consider the security of potential optimization techniques before implementing them in a processor.

As a vital security primitive, the true random number generator (TRNG) is a mandatory component to build roots of trust for any encryption system. However, existing TRNGs suffer from bottlenecks of low throughput and high area-energy consumption. In this work, we propose DH-TRNG, a dynamic hybrid TRNG circuitry architecture with ultra-high throughput and area-energy efficiency. Our DH-TRNG exhibits portability to distinct process FPGAs and passes both NIST and AIS-31 tests without any post-processing. The experiments show it incurs only 8 slices with the highest throughput of 670Mbps and 620Mbps on Xilinx Virtex-6 and Artix-7, respectively. Compared to the state-of-the-art TRNGs, our proposed design has the highest Throughput/Slices Power with 2.63× increase.

Cryptographic Hardware Engineering (CHE) is an emerging field that amalgamates cryptography principles with hardware design and implementation. It plays an increasingly important role as secure and trustworthy computing and communication is needed in all applications. In order to introduce CHE into undergraduate curriculum to prepare the next generation workforce, students must have a solid theoretical foundation in cryptography, be proficient in digital circuit design, and have access to commercial design tools and equipment. In this paper, we report our experience in developing and teaching a CHE course for junior students. The course consists of three components that are complementary to each other: digital circuits and FPGA design fundamentals, hardware implementation of cryptographic algorithms, and security analysis of cryptographic hardware. Through this course, students get a good comprehension of CHE principles and gain hands-on experience in secure cryptographic hardware design and analysis.

Interrupts are critical hardware resources for OS kernels to schedule processes. As they are related to system activities, interrupts can be used to mount various side-channel attacks (i.e., monitoring keystrokes, inferring website visits, detecting GPU activities, and fingerprinting processes). Given that all these attacks rely on system file interfaces or architectural timers to probe interrupts, various countermeasures have been proposed to either remove the unprivileged access to the file interfaces or detect/cripple architectural timers. In this work, we propose SegScope, a new technique that abuses segment protection to provision fine-grained interrupt observations without any timer. As segment protection is widely used on x86, SegScope works across a wide range of Intel-and AMD-based CPUs. Particularly, we observe that while segment protection preserves the confidentiality of high privileged domain, it leaves a footprint via the data segment registers values when an interrupt occurs. With this key observation, SegScope is crafted by capturing the footprints. To show its security implications, we evaluate it in four case studies. First, SegScope has inferred website visits with a respective success rate of 92.4% on Chrome and 87.4% on Tor Browser in default system settings. Second, SegScope successfully extracts the keys from Cloudflare's Interoperable Reusable Cryptographic Library (CIRCL) vl.l. Third, SegScope steals DNN model architectures with an accuracy of over 80%. Last, SegScope effectively reduces the noise of interrupts to improve the performance of other side channels. As an example, SegScope reduces the error rate of Spectral side channel by 56×. Compared with existing timer-based interrupt-probing techniques, SegScope is fine-grained without introducing false-positives. Further, we leverage SegScope to craft a fine-grained timer, as regular timer interrupts as clock edges contain timestamps. Our evaluation shows that it achieves the same level of timing granularity as the high-resolution timer, i.e., rdtsc and rdpru. We then leverage the timer to break KASLR in about 10 seconds and mount a Flush+Reload based Spectre attack.

Kalman Filter (KF) algorithm, which can solve the state estimation problem of multi-variable and complex dynamical system, plays a pivotal role in a multitude of engineering scenarios. However, the traditional digital computing architecture represented by the von-Neumann architecture are currently confronted with high overhead challenges in terms of latency, energy, and area when executing KF algorithm. Aiming at the problem, we propose CIM-KF, the first Computing-in-memory (CIM) circuits for KF algorithm. CIM-KF can efficiently carry out the entire process of KF algorithm by capitalizing on the large-scale parallel computation inherent in the CIM architecture. The evaluation shows that CIM-KF has average 96.15% accuracy for 32-th order parameter matrix in KF algorithm, and can be 13.89 × ∼ 55.21 × faster than existing ASIC and FPGA implementations of KF algorithm. The results also demonstrate that CIM-KF can deliver up to 3.52 × energy efficiency improvement and 54.79 × area efficiency improvement, and reduce over 90% latency overhead, compared with the SOTA counterparts. Furthermore, we propose a novel design of ReRAM-CIM architecture, underpinned by the CIM-KF, aimed at precise and rapid calculation of the state of capacity and terminal voltage in Battery Management Systems. By evaluation, our proposed architecture boasts the estimation accuracy within 2% error for the individual battery cell of state of capacity and terminal voltage. With the strengths of the parallel computing intrinsic to CIM architecture and the speed of analog circuit, our architecture facilitates speed up to 70.6 × in accurate estimation when bench-marked against the SOTA work.

In the space environment, satellites operate within various cosmic radiation and charged particle environments, making it difficult to avoid Single Event Effects (SEE). Among these errors, soft errors represented by SEE occur relatively frequently and receive more attention. This paper presents a highly fault-tolerant operating system architecture (FOSA) implemented solely in software, utilizing Commercial Off-The-Shelf (COTS) chips. It effectively balances cost, fault tolerance, and performance overhead, while also offering scalability and portability. Additionally, it is backward compatible with hardware fault tolerance mechanisms such as Error Correcting Code (ECC), enabling high reliability of satellite payload business software. The experimental results indicate that the fault detection rate of FOSA reaches as high as 99%, with an overhead of 48% for IO-intensive tasks, while the fault recovery time is less than 2 seconds.

Stochastic computing (SC) is a promising computing paradigm for circuit design in the post-Moore era. It encodes data through stochastic bit streams (SBSs) and employs a randomizer to generate them, where the randomizer converts binary-encoded variables into stochastic formats and can optionally provide some SBSs of constant values. Owing to this, the randomizer generally plays a critical role in determining the accuracy of SC circuits and occupies a significant portion of their hardware cost. Therefore, it is crucial to apply proper randomizers to enhance the overall performance and efficiency of SC circuits. However, recent SC circuit designs often suffer from complex randomizers to ensure high accuracy. To address this issue, several efficient designs and optimization methods of randomizers have been proposed. In this paper, we review the common designs, the optimization methods, and the efficient application of randomizers, while discussing current challenges and future directions. By providing a brief overview, this survey underscores the critical role of randomizer design and optimization for efficient SC.

This paper presents the design and implementation of a systematic Inter-Component Communications (ICCs) dynamic Analysis Technique (SIAT) for detecting privacy-sensitive data leak threats. SIAT’s specific approach involves the identification of malicious ICC patterns by actively tracing both data flows and implicit control flows within ICC processes during runtime. This is achieved by utilizing the taint tagging methodology, a technique utilized by TaintDroid. As a result, it can discover the malicious intent usage pattern and further resolve the coincidental malicious ICCs and bypass cases without incurring performance degradation. SIAT comprises two key modules: Monitor and Analyzer. The Monitor makes the first attempt to revise the taint tag approach named TaintDroid by developing the built-in intent service primitives to help Android capture the intent-related taint propagation at multi-level for malicious ICC detection. Specifically, we enable the Monitor to perform systemwide tracking of intent with five abstraction functionalities embedded in the interactive workflow of components. By analyzing the taint logs offered by the Monitor, the Analyzer can build the accurate and integrated ICC patterns adopted to identify the specific leak threat patterns with the identification algorithms and predefined rules. Meanwhile, we employ the patterns’ deflation technique to improve the efficiency of the Analyzer. We implement the SIAT with Android Open Source Project and evaluate its performance through extensive experiments on a particular dataset consisting of well-known datasets and real-world apps. The experimental results show that, compared to state-of-the-art approaches, the SIAT can achieve about 25% ∼200% accuracy improvements with 1.0 precision and 0.98 recall at negligible runtime overhead. Apart from that, the SIAT can identify two undisclosed cases of bypassing that prior technologies cannot detect and quite a few malicious ICC threats in real-world apps with lots of downloads on the Google Play market.

Modern advanced CPU designs are frequently exposed to transient execution vulnerabilities, which allow attackers to harness microarchitectural side effects for data exfiltration. The leaked data may encompass direct target data, such as RSA keys, or indirect information, like physical page mappings. Thus, transient execution attacks can be divided into data-leakage and address-leakage, depending on the specific targets that are exposed. Existing studies have developed practical defenses and detection mechanisms against the microarchitectural attacks. However, almost all of them focus solely on data leakage and are thus unable to detect and counter address-leakage attacks, like Spoiler, due to their unique mechanisms. This paper introduces AALERT, the first detection mechanism specifically designed for address-leakage transient execution attacks. AALERT integrates a Cuckoo filter module within the CPUs Memory Order Buffer (MOB) to screen buffered addresses on the fly. We further optimize the filtering algorithm to minimize false positives. We discuss and implement several countermeasures to defeat the detected attacks. Finally, we evaluate the effectiveness and performance of AALERT based on prototype implementations, demonstrating a detection rate of 99.99% with negligible performance overhead.

Memristive neuromorphic networks have great potential and advantage in both technology and computational protocols for artificial intelligence. Efficient hardware design of biological neuron models forms the core of research problems in neuromorphic networks. However, most of the existing research has been based on logic or integrated circuit principles, limited to replicating simple integrate-and-fire behaviors, while more complex firing characteristics have relied on the inherent properties of the devices themselves, without support from biological principles. This paper proposes a memristor-based neuron circuit system (MNCS) according to the microdynamics of neurons and complex neural cell structures. It leverages the nonlinearity and non-volatile characteristics of memristors to simulate the biological functions of various ion channels. It is designed based on the Hodgkin-Huxley (HH) model circuit, and the parameters are adjusted according to each neuronal firing mechanism. Both PSpice simulations and practical experiments have demonstrated that MNCS can replicate 24 types of repeating biological neuronal behaviors. Furthermore, the results from the Joint Inter-spike Interval(JISI) experiment indicate that as the background noise increases, MNCS exhibits pulse emission characteristics similar to those of biological neurons.

The rapid development of artificial intelligence has brought a huge amount of data, and the traditional image processing architecture that separates sensing, storage and computation will face the problems of high power consumption and processing latency. Focusing on these problems, this paper proposed a design scheme of memristor-based optoelectronic sensing circuit, which can integrate image perception, storage, and processing into one entity. Without large-scale data transmission and conversion, the corresponding energy consumption can be avoided effectively. Firstly, an optoelectronic sensing circuit based on memristive crossbar array is proposed, which realizes the acquisition and in situ storage of image information by embedding the photoelectric converters into the memristive array. On this basis, the corresponding peripheral circuit is designed to accomplish the in situ edge feature extraction for the stored image. The extraction process is large-scale parallel computing in the analog domain, and the speed is significantly improved compared with the traditional solution. Moreover, the extraction accuracy of the circuit can reach more than 99%, and it also can withstand a certain degree of programming error and has strong robustness.

Due to their low latency and high privacy preservation, there is currently a burgeoning demand for deploying deep learning (DL) models on ubiquitous edge Internet of Things (IoT) devices. However, DL models are often large in size and require large-scale computation, which prevents them from being placed directly onto IoT devices, where resources are constrained, and 32-bit floating-point (float-32) operations are unavailable. Commercial framework (i.e., a set of toolkits) empowered model quantization is a pragmatic solution that enables DL deployment on mobile devices and embedded systems by effortlessly post-quantizing a large high-precision model (e.g., float-32) into a small low-precision model (e.g., int-8) while retaining the model inference accuracy. However, their usability might be threatened by security vulnerabilities. This work reveals that standard quantization toolkits can be abused to activate a backdoor. We demonstrate that a full-precision backdoored model which does not have any backdoor effect in the presence of a trigger—as the backdoor is dormant—can be activated by (i) TensorFlow-Lite (TFLite) quantization, the onlyproduct-readyquantization framework to date, and (ii) thebeta releasedPyTorch Mobile framework. In our experiments, we employ three popular model architectures (VGG16, ResNet18, and ResNet50), and train each across three popular datasets: MNIST, CIFAR10 and GTSRB. We ascertain that all trained float-32 backdoored models exhibit no backdoor effecteven in the presence of trigger inputs. Particularly, four influential backdoor defenses are evaluated, and they fail to identify a backdoor in the float-32 models. When each of the float-32 models is converted into an int-8 format model through the standard TFLite or PyTorch Mobile framework's post-training quantization, the backdoor is activated in the quantized model, which shows a stable attack success rate close to 100% upon inputs with the trigger, while it usually behaves upon non-trigger inputs. This work highlights that a stealthy security threat occurs when an end-user utilizes the on-device post-training model quantization frameworks, informing security researchers of a cross-platform overhaul of DL models post-quantization even if these models pass security-aware front-end backdoor inspections. Significantly, we have identified Gaussian noise injection into the malicious full-precision model as an easy-to-use preventative defense against the PQ backdoor. The attack source code is released athttps://github.com/quantization-backdoor.

As the core operation of lattice cipher, large-scale polynomial multiplication is the biggest computational bottleneck in its realization process. How to quickly calculate polynomial multiplication under resource constraints has become an urgent problem to be solved in the hardware implementation of lattice ciphers. Therefore, an analog in-memory circuit for fast polynomial multiplication calculation is proposed. First, an in-memory computing circuit for Discrete Fourier Transform and Inverse Discrete Fourier Transform based on memristor array is designed. On this basis, a fully analog circuit that can realize polynomial multiplication in one step is designed. Compared with traditional hardware implementation, the in-memory calculation method used in this article decreases the calculation time of polynomial multiplication to the microsecond level, which greatly improves the speed of lattice cipher encryption and decryption. For the specific examples in this article, PSPICE simulation shows that the average accuracy of the calculation result is above 99.90%.

Memory-disk synchronization is a critical technology for ensuring data correctness, integrity, and security, especially in systems that handle sensitive information like financial transactions and medical records. We propose Write+Sync, a group of attacks that exploit the memory-disk synchronization primitives. Write+Sync works by subtly varying the timing of synchronization on a software cache (i.e., the write buffer), offering two advantages: 1) implemented purely in software, enabling deployment on any hardware devices; 2) resilient against existing countermeasures. We present the principles of Write+Sync through the implementation of two write covert channel protocols, using either a single file or page, and introduce three enhanced strategies that utilize multiple files and pages. The feasibility of these channels is demonstrated in both cross-process and cross-sandbox scenarios across diverse operating systems (OSes). Experimental results show that, the average rate can reach 2.036 Kb/s (with a peak rate of 14.762 Kb/s) and the error rate is 0% on Linux; when running on macOS, the average rate achieves 10.211 Kb/s (with a peak rate of 253.022 Kb/s) and the error rate is 0.004%. To show its security implications, we evaluate it using two case studies-website fingerprinting and performance degradation attacks. To the best of our knowledge, Write+Sync is the first high-speed write covert channel for software cache.

Interference alignment can overcome the shortcomings in traditional interference management. How to quickly and efficiently eliminate interference by using interference alignment is an important question. Aiming at this problem, we propose an analog in-memory circuit based on memristors for accelerating the opposite directional interference alignment algorithm, which is achieved by solving complex-valued matrix equation and multiple complex-valued matrix multiplication. The circuits can adapt to any numbers of antennas condition and adjust the memconductance to map with the channel matrix in communication systems. The evaluation shows that the circuits not only have 99% high accuracy in executing a$2\times 2$channel state but also have good robustness against some nonideal factors from wireless communication that the corresponding accuracy can exceed 95% under the 10% noise impact. Moreover, the circuits accelerate the algorithm which is three orders of magnitude faster than software.

To overcome the energy efficiency bottleneck of the von Neumann architecture and scaling limit of silicon transistors, an emerging but promising solution is neuromorphic computing, a new computing paradigm inspired by how biological neural networks handle the massive amount of information in a parallel and efficient way. Recently, there is a surge of interest in the nematode worm Caenorhabditis elegans (C. elegans), an ideal model organism to probe the mechanisms of biological neural networks. In this article, we propose a neuron model for C. elegans with leaky integrate-and-fire (LIF) dynamics and adjustable integration time. We utilize these neurons to build the C. elegans neural network according to their neural physiology, which comprises: 1) sensory modules; 2) interneuron modules; and 3) motoneuron modules. Leveraging these block designs, we develop a serpentine robot system, which mimics the locomotion behavior of C. elegans upon external stimulus. Moreover, experimental results of C. elegans neurons presented in this article reveals the robustness (1% error w.r.t. 10% random noise) and flexibility of our design in term of parameter setting. The work paves the way for future intelligent systems by mimicking the C. elegans neural system.

Distributed Reflection Denial-of-Service (DRDoS) attacks have caused significant destructive effects by virtue of emerging protocol vulnerabilities and amplification advantages, and their intensity is increasing. The emergence of programmable data plane supporting line-rate forwarding provides a new opportunity for fine-grained and efficient attack detection. This paper proposed a light-weight DRDoS attack detection and mitigation system called FAPM, which is deployed at the victim end with the intention of detecting the amplification behavior caused by the attack. It places the work of collecting and calculating reflection features on the data plane operated by “latter window assisting former window” mechanism, and arranges complex identification and regulation logic on the control plane. This approach avoids the hardware constraints of the programmable switch while leveraging their per-packet processing capability. Also, it reduces communication traffic significantly through feature compression and state transitions. Experiments show that FAPM has (1) fast response capability within seconds (2) a memory footprint at the KB level and communication overhead of 1 Kbps, and (3) good robustness.

With the rapid development of integrated circuits and the continuous progress of computing capability, higher demands have been placed on the security and speed of data encryption in security systems. As a basic hardware security primitive, the true random number generator (TRNG) plays an important role in the encryption system, which requires higher throughput and randomness with lower hardware overhead. However, the throughput of TRNG is related to the entropy source’s quality and the randomness extraction methodology. To quantify the randomness of the entropy source with higher efficiency and quality, we utilize the independent jitter of the self-timed ring (STR) to generate original entropy and propose a high throughput jitter-based TRNG which can extract random information at the pulse of oscillation signal by jitter precise quantization superposing and random oscillation sampling. The proposed TRNG has been implemented on Artix-7 and Virtex-6 FPGAs. The generated true random number successfully passes the NIST SP800-22 and NIST SP800-90B tests while also exhibiting a minimum entropy greater than 0.9947. The most prominent superiority of our proposed TRNG is that it achieves a high throughput of 330 Mbps with an ultra-low hardware overhead of only 35 LUTs and 12 DFFs.

Deep neural network (DNN)-based transformer models have demonstrated remarkable performance in natural language processing (NLP) applications. Unfortunately, the unique scaled dot-product attention mechanism and intensive memory access pose a significant challenge during inference on power-constrained edge devices. One emerging solution to this challenge is computing-in-memory (CIM), which uses memory cells for logic computation to reduce data movement and overcome the memory wall. However, existing CIM designs do not support high-precision computations, such as floating-point operations, which are essential for NLP applications. Furthermore, CIM architectures require complex control modules and costly peripheral circuits to harness the full potential of in-memory computation. Hence, this article proposes a scalable RRAM-based in-memory floating-point computation architecture (RIME) that uses single-cycle NOR, NAND, and minority logic to implement in-memory floating-point operations. RIME features efficient parallel and pipeline capabilities with a centralized control module and a simplified peripheral circuit to eliminate data movement during computation. Furthermore, the article proposes pipelined implementations of matrix–matrix multiplication (MatMul) and softmax functions, enabling the construction of a transformer accelerator based on RIME. Extensive experimental results show that compared with GPU-based implementation, the RIME-based transformer accelerator improves timing efficiency by$2.3\times $and energy efficiency by$1.7\times $without compromising inference accuracy.

Confidential computing technologies, such as that enabled by Intel SGX (Software Guard eXtensions), have been widely deployed in various commercial cloud platforms. Specifically, SGX uses hardware-isolated compartments named enclaves to shield user applications from Operating Systems (OSes) and hypervisors, thus providing confidentiality and integrity guarantees for code and data. However, some crucial problems are not fully analyzed yet, especially for the compatibility with binary applications. This work first delivers an overview of Intel SGX and reviews its five design constraints that may affect compatibility. Subsequently, we revisit three distinct compatibility solutions from the internals and analyze their impact on security, performance, and flexibility. At last, we lay out some fundamental lessons learned from prior SGX studies.

Greetings and a warm welcome to the 2023 32nd IEEE Asian Test Symposium (ATS 2023)!

SRAM-based FPGAs have been widely deployed in aerospace applications in recent years. However, the embedded RAM and user logic are vulnerable to Single Event Upset (SEU), which will result in misconnection or misrouting. This paper proposes a comprehensive survey on fault-tolerance methods for SRAM-based FPGAs in harsh radiation environments. First, the architecture of the Xilinx 7 serial FPGAs is provided to explain how SEU happens and why it causes malfunction. Second, we elaborate on the approaches to evaluate the reliability of SRAM-based FPGAs against SEU. Third, representative fault-tolerance methods are introduced, including Triple Module Redundancy (TMR) and configuration scrubbing. In sum, this survey can serve as a tutorial for engineers and scientists who major in designing fault-tolerance methods for SRAM-based FPGAs in aerospace devices.

Learning parity with noise (LPN) is under intensive research in building advanced cryptography suites and protocols. However, in LPN-based cryptography, the transmission of the large matrices between the memory and the processor units generally incurs a significant latency overhead. In this work, we propose PIMA-LPN, a processing-in-memory (PIM) accelerator for LPN cryptography. Specifically, our PIM architecture can carry out the entire computations of LPN in memory. In this experiment, we demonstrate that PIMA-LPN can be 20.86× ~ 216.8× faster than existing CPU and FPGA implementations of LPN cryptography. Furthermore, we show that using PIMA-LPN, LPN cryptography can achieve similar computational efficiency compared to the post-quantum cryptography standard (i.e., CRYSTALS-Kyber) with 15.4x fewer memory units.

In this paper, we design an energy-efficient true random number generator with ultra-high throughput for FPGA. Only four ring oscillators constructed using eight LUTs are sampled by multiple sampling points to fully exploit the randomness of the entropy source, which provides high-quality and over 275 Mbps random sequences while consuming 13 slices. An end-to-end implementation and testing framework is tailored for easy deployment and portability on Xilinx 7 serials FPGAs. The proposed architecture passes the NIST SP 800-22 and 800-90B tests without post-processing and outperforms the state-of-the-art in terms of minimum entropy and energy efficiency.

Multi-process concurrency is effective in improving program efficiency and maximizing CPU utilization. The correct execution of concurrency is ensured by the mutual exclusion and synchronization mechanism (MESM) that manages the shared hardware and software resources. We propose MES-Attacks, a new set of software-controlled covert channel attacks based on MESM to transmit confidential information. MES-Attacks offer several advantages: 1) the covert channels are constructed at software level and can be deployed on any hardware; 2) the closed share of resource ensures the quality of the channels with low interference and makes them hard to be detected; and 3) the attack utilizes system’s software resources which are abound and hence difficult to isolate. We report the covert channels we have built with the following MESMs on Linux and Windows: flock, FileLockEX, Mutex, Semaphore, Event and WaitableTimer. Experimental results demonstrate that these covert channels can achieve transmission rate of 13.105 kb/s, 12.383 kb/s, and 6.552 kb/s, respectively in the scenarios of local, cross-sandbox and cross-virtual machine, all with bit error rate under 1%.

Spoiler attacks leak physical address information, which is exploited to accelerate reverse engineering of virtual-to-physical address mapping, thus greatly boosting Rowhammer and cache attacks. However, existing approaches that detect data-leakage attacks no longer suit the requirements of identifying Spoiler. This paper proposes Spoiler-alert,the first hardware-level mechanism to detect the address-leakage Spoiler attacks in real time. It leverages a cuckoo filter module embedded into Memory Order Buffer component to screen buffer addresses on-the-fly. We further optimise the filtering algorithm to reduce false positives. We assess the effectiveness and performance based on prototype implementations, which achieve a detection rate of 99.99% and negligible performance loss. Finally, we discuss potential reactions of our detection mechanism after a Spoiler attack was discovered.

Complex-valued neural networks have better optimization capabilities, stronger robustness, and richer characterization capabilities compared with real-valued neural networks, which has achieved good results in the field of portrait restoration. However, there is almost no circuit implementation of complex-valued neural networks. Based on this, this article proposes an in-memory computing circuit implementation of a complex-valued Hopfield neural network (CHNN) for the first time, which provides a highly accurate and efficient processing circuit for portrait restoration. First, a new memristive array is proposed, which can realize parallel complex-valued multiplication and complex-valued vector–matrix multiplication. On the basis, a CHNN circuit that can perform large-scale recursive computations is designed. Due to the characteristics of in-memory computation, the computation speed and robustness have been improved when realizing portrait restoration. Different portrait restoration scenarios can be realized based on the programmability of the memristive array. Pspice simulation results show that the recovery speed of CHNN can reach the level of 0.1 ms, and the accuracy can reach above 97.00%. Robustness analysis shows that the circuit can tolerate a certain degree of programming error and has strong anti-noise performance.

The mutual exclusion and synchronization mechanism (MESM) is a basic process management mechanism in modern operating systems. However, we first found that MESM has serious vulnerabilities. In this article, a new set of MESM-based software covert channels, named Mex+Sync, are proposed to transmit confidential information. Mex+Sync offer several advantages: 1) the covert channels are constructed at the software level and can be deployed on any hardware; 2) the closed shared resource ensures the quality of the channels with low interference and makes them hard to be detected; and 3) the attack utilizes the system’s software resources which abound and hence difficult to isolate. We build the covert channels on Linux and Windows with the following MESMs:flock,FileLockEX,Mutex,Semaphore,Event, andWaitableTimer. Experimental results demonstrate that these covert channels can achieve transmission rate of 13.105, 12.383, and 6.552 kb/s, respectively, in the scenarios of local, cross-sandbox and cross-virtual machine, all with bit error rate under 1%. Meanwhile, we carefully analyze and verify the impact of noise on channel performance.

Matrix operations are widely used in practical engineering, but the traditional processing methods rely on the loop iterations and neural network algorithm on the software, requiring a long time to calculate. To address such problem, this paper proposes full hardware in-memory computing circuits based on programmable memristor unit array that can solve combinatorial matrix operations of any order in just one step. First, two basic circuit modules are introduced, which can respectively solve matrix multiplication and matrix equation. Further, the basic modules can be linked to solve combinatorial matrix operations with different forms. It’s worth noting that every module can parallel program the value of each memristor in the memristor unit array and complete one-step computation by hardware. Then, some matrix operations are given in the paper as examples to prove the high accuracy of proposed method, where the average accuracy rate achieves 99%. The PSPICE simulation results demonstrate that the processing speed is improved enormously according to the comparison of hardware and software. Moreover, the proposed method has broad application prospect in practical engineering, such as using designed combinational circuit to solve domain shift problem in zero-shot learning, which greatly accelerates the training process of zero-shot learning.

Training a Deep Learning (DL) model requires proprietary data and computing-intensive resources. To recoup their training costs, a model provider can monetize DL models through Machine Learning as a Service (MLaaS). Generally, the model is deployed at the cloud, while providing a publicly accessible Application Programming Interface (API) for paid queries to obtain benefits. However, model stealing attacks have posed security threats to this model monetizing scheme as they steal the model without paying for future extensive queries. Specifically, an adversary queries a targeted model to obtain input-output pairs and thus infer the model’s internal working mechanism by reverse-engineering a substitute model, which has deprived model owner’s business advantage and leaked the privacy of the model. In this work, we observe that the confidence vector or the top-1 confidence returned from the model under attack (MUA) varies in a relative large degree given different queried inputs. Therefore, rich internal information of the MUA is leaked to the attacker that facilities her reconstruction of a substitute model. We thus propose to leverage adversarial confidence perturbation to hide such varied confidence distribution given different queries, consequentially against model stealing attacks (dubbed as APMSA). In other words, the confidence vectors returned now is similar for queries from a specific category, considerably reducing information leakage of the MUA. To achieve this objective, through automated optimization, we constructively add delicate noise into per input query to make its confidence close to the decision boundary of the MUA. Generally, this process is achieved in a similar means of crafting adversarial examples but with a distinction that the hard label is preserved to be the same as the queried input. This retains the inference utility (i.e., without sacrificing the inference accuracy) for normal users but bounded the leaked confidence information to the attacker in a small constrained area (i.e., close to decision boundary). The later renders greatly deteriorated accuracy of the attacker’s substitute model. As the APMSA serves as a plug-in front-end and requires no change to the MUA, it is thus generic and easy to deploy. The high efficacy of APMSA is validated through experiments on datasets of CIFAR10 and GTSRB. Given a MUA model of ResNet-18 on the CIFAR10, our defense can degrade the accuracy of the stolen model by up to 15% (rendering the stolen model useless to a large extent) with 0% accuracy drop for normal user’s hard-label inference request.

Software-defined networking (SDN) faces challenges in efficiently forwarding packets across the network due to the limited capacity of flow tables in the switches. Ternary content addressable memory (TCAM) is typically used to store flow tables, but its limited capacity makes it vulnerable to attacks. Specifically, the Low-rate Flow Table Overflow (LFTO) attack is an attack against the flow table capacity limit, which can occupy massive space in the flow table to decrease the forwarding performance of normal flow rules by slowly sending packets that cannot match the flow table. To address this, we propose the FTMaster, a system to monitor, detect and mitigate LFTO attacks based on machine learning. FTMaster monitors and detects the flow table state by analyzing the features of flow tables. Once the LFTO attack is detected, FTMaster will activate the mitigation module to extract and analyze the features of each flow rule, evict attack flows, and ultimately block the attack source, thereby protecting flow tables and normal flows. Experimental results demonstrate that FTMaster enables real-time LFTO attack detection and mitigation, ensuring normal forwarding and availability of flow tables.

Discrete Hartley transform is a core component of digital signal processing because of its advantages of fast computing speed and less power consumption. Traditional FPGA-based implementation methods have the disadvantage of high latency, which cannot meet the needs of energy-efficient computing in the Internet of Things era. Therefore, A programmable analog memory computing circuit is proposed to accelerate FHT and IFHT calculations for large-scale one-step matrix computation. By adjusting the weight of memristor, different scales of FHT calculation can be achieved. PSPICE simulation results show that the average accuracy of the proposed circuit can reach 99.9%, and the speed can also reach the level of 0.1 μs. The robustness analysis shows that the circuit can tolerate a certain degree of programming error and resistance tolerance. The designed analog circuit is applied to image compression processing, and the image compression accuracy can reach 99.9%.

Software defined networking (SDN), a highly regarded architecture, enhances the programmability and manageability of the network by decoupling the data plane and the control plane. It has emerged to bring more possibilities to the Internet, but at the same time, its inherent shortcomings have become a pool for malicious attackers. Low-rate denial of service (LDoS) attacks, a variant of denial of service attacks, also pose a threat to the SDN architecture. In this article, we replicate LDoS attacks for the SDN data plane and propose a detection and mitigation framework called GASF-IPP based on multiple traffic and IP-port data by analyzing the network anomalies. By leveraging the OpenFlow protocol, the traffic of switches is monitored. We use Gramian angular summation field (GASF) transformation based on timing analysis to analyze the traffic and combine it with other features to determine whether an attack has occurred. By locating the attacker and the victim, flow rules can be constructed for mitigation. Experiments prove that our proposed framework is correct and effective, the detection and mitigation module can perform real-time work with a low false positive rate (FPR) and respond in average 6.77 s.

Spectre attacks endanger most of CPUs, operating systems and cloud services due to the sharing of branch predic- tors in modern processors, while existing defenses fail to balance the security and overhead. This paper designs a lightweight and secure branch predictor (LS-BP), which provides lightweight hardware isolation for different branch entries of same-address- space and cross-address-space. Therefore, it is difficult for the attacker to establish branch conflicts. Experimental results show the average performance overhead is less than 3% while providing strong protection.

Physical unclonable function (PUF) is a promising lightweight hardware security primitive that exploits process variations during chip fabrication for applications such as key generation and device authentication. Reliability of the PUF information plays a vital role and poses a major challenge for PUF design. In this paper, we propose a novel dual-state analog PUF (DA PUF) which has been successfully fabricated in 55nm process. The 40,960 bits generated by the fabricated DA PUF pass the NIST randomness test with reliability over 99.99% for working environment of -40 ~ 125° C (temperature) and 0.96 ~ 1.44V (voltage), outperforming the two state-of-the-art analog PUFs reported in JSSC 2016 and 2021.

Physical unclonable function (PUF) is a promising lightweight hardware security primitive for resource-limited Internet-of-Things (IoT) devices. Strong PUFs are suitable for lightweight device authentication because it can generate quantities of challenge-response pairs. Unfortunately, while the machine learning (ML) techniques have benefited various areas, such as Internet, industrial automation, robotics and gaming, they pose a severe threat to PUFs by easily modelling their behavior. This article first shows that even a recently reported dual-mode PUF can be cloned by ML (prediction accuracy of up to 95%). To solve this issue, we propose a configurable tristate (CT) PUF which can flexibly perform as an arbiter PUF, a ring oscillator (RO) PUF, or a bistable ring (BR) PUF with a bitwise XOR-based mechanism to obfuscate the relationship between the challenge and the response, hence resisting the ML attacks. An authentication protocol for the use in IoT security is presented. The CT PUF is implemented on Xilinx ZedBoard FPGAs with placement and routing details described. The experimental results show that the modelling accuracy of logistic regression (LR), support vector machine (SVM), covariance matrix adaptation evolutionary strategies (CMA-ES), and artificial neural network (ANN) is close to 60% (50% as the ideal number in theory) while meeting the PUF requirements for uniformity, reliability, and uniqueness. The hardware overhead and power consumption are slight. The entire project has been open sourced.

In recent years, micro-nano device characteristics like ferroelectrics and resistive switching are being used to build important security primitives such as Physical Unclonable Function (PUF). The micro-nano device-based hardware security primitives, although with higher security, energy efficiency, and integration density, suffer from serious reliability issues caused by process scaling. To mitigate this issue, this paper introduces a reconfigurable weak PUF based on spin-transfer torque magnetoresistive random-access memory (STT-MRAM), which adopts the crossing switches implemented with simple demultiplexes (DEMUXs) to improve the flexibility and reliability. Moreover, two algorithms,neighboring bit linesandtop-$n$n, are proposed to enlarge the gap between two parallel reading currents, thus further enhancing the reliability of PUF responses. Experimental results demonstrate that the proposed PUF scheme achieves good uniqueness (50.64 percent), uniformity (50.02 percent), and bit-aliasing ($\approx$49.80%). Particularly, the proposed method significantly improves the PUF reliability, achieving low bit error rate (BER$\leq$2.13%) within the range of -20$^\circ$C to 90$^\circ$C.

It is a challenging task to deploy lightweight security protocols in resource-constrained IoT applications. A hardware-oriented lightweight authentication protocol based on device signature generated during voltage over-scaling (VOS) was recently proposed to address this issue. VOS-based authentication employs the computation unit such as adders to generate the process variation dependent error, which is combined with secret keys to create a two-factor authentication protocol. In this article, machine learning (ML)-based modeling attacks to break such authentication is presented. We also propose achallengeself-obfuscationstructure (CSoS) which employs previous challenges combined with keys or random numbers to obfuscate the current challenge for the VOS-based authentication to resist ML attacks. Experimental results show that ANN, RNN, and CMA-ES can clone the challenge-response behavior of VOS-based authentication with up to 99.65 percent prediction accuracy, while the prediction accuracy is less than 51.2 percent after deploying our proposed ML resilient technique. In addition, our proposed CSoS also shows good obfuscation ability for strong PUFs. Experimental results show that the modeling accuracy is below 54 percent when 106challenge-response pairs (CRPs) are collected to model the CSoS-based Arbiter PUF with ML attacks based on LR, SVM, ANN, RNN, and CMA-ES.

Central Processing Unit (CPU) is considered as the brain of a computer. If the CPU has vulnerabilities, the security of software running on it is difficult to be guaranteed. In recent years, various micro-architectural cache side-channel attacks on the CPU such as Spectre and Meltdown have appeared. They exploit contention on internal components of the processor to leak secret information between processes. This newly evolving research area has aroused significant interest due to the broad application range and harmfulness of these attacks. This article reviews recent research progress on micro-architectural cache side-channel attacks and defenses. First, the various micro-architectural cache side-channel attacks are classified and discussed. Then, the corresponding countermeasures are summarized. Finally, the limitations and future development trends are prospected.

Recent studies have shown that neural networks are vulnerable to adversarial example (AE) attacks. However, the existing AE generation techniques restrict the pixel perturbation to improve imperceptibility, resulting in low attack success rates. Although increasing perturbations can improve the attack success rate, the imperceptibility of AEs will be reduced. In order to mitigate this contradiction, we propose a new attack method, named AttAdvGAN, which uses adversarial-consistency loss for unpaired image-to-image translation to generate semantic-based AEs for faces, encouraging the generated image contains important features of the original image and hiding adversarial perturbations into shared feature in the target domain. Experiment results show that the proposed approach can generate imperceptible face AEs on the CelebA dataset with high attack success rate in fooling the state-of-the-art face recognition model. In addition, our proposed method can also be used for facial privacy protection.

Approximate computing techniques for error-tolerant machine learning applications are gaining interest, promising a energy-accuracy balance for modern digital computing systems. As an ubiquitous step in machine learning, iterative solvers have been widely used for training neural networks and accelerating feedforward computations. In this paper, we provide three novel information hiding techniques that use properties of redundant number systems, most-significant digit-first arithmetic and the forward error analysis of stationary iterative methods, to secure approximate computing systems. We demonstrate that three different security signatures are encoded through redundant representation, function-equivalence arithmetic replacement and algorithmic optimisation. Our illustrative security enhancement countermeasures can be used to prevent potential attacks, such as privacy leakage, out-of-control systematic error and error injection in approximate computing.

Strong physical unclonable function (PUF) is a promising solution for device authentication in resource-constrained applications but vulnerable to machine learning (ML) attacks. In order to resist attack, many defenses have been proposed in recent years. However, these defenses incur high hardware overhead, degenerate reliability and are inefficient against advanced ML attacks such as approximation attacks. To address these issues, we propose a Random Set-based Obfuscation (RSO) for Strong PUFs to resist ML attacks. The basic idea is that several stable responses are derived from the PUF itself and pre-stored as the set for obfuscation in the testing phase, and then a true random number generator is used to select any two keys to obfuscate challenges and responses with XOR operations. When the number of challenge-response pairs (CRPs) collected by the attacker exceeds the given threshold, the set will be updated immediately. In this way, ML attacks can be prevented with extremely low hardware overhead. Experimental results show that for a 64 × 64 Arbiter PUF, when the size of set is 32 and even if 1 million CRPs are collected by attackers, the prediction accuracies of the several ML attacks we use are about 50% which is equivalent to the random guessing.

Taint-propagation and X-propagation analyses are important tools for enforcing circuit design properties such as security and reliability. Fundamental to these tools are effective models for accurately measuring the propagation of information and calculating metadata. In this work, we formalize a unified model for reasoning about taint- and X-propagation behaviors and verifying design properties related to these behaviors. Our model are developed from the perspective of information flow and can be described using standard hardware description language (HDL), which allows formal verification of both taint-propagation (i.e., security) and X-propagation (i.e., reliability) related properties using standard electronic design automation (EDA) verification tools. Experimental results show that our formal model can be used to prove both security and reliability properties in order to uncover unintended design flaw, timing channel and intentional malicious undocumented functionality in circuit designs.

The development of integrated circuit technology is accompanied by potential threats. Malicious modifications to circuits, known as hardware Trojans, are major security concerns. This paper gives a survey of hardware Trojan detection methods towards gate-level netlists. The detection methods are divided into search-based, threshold-based, and machine learning-based ones. This paper compares and analyzes existing works from aspects of feature selection, data balancing techniques, classification criterion, detection range. The experimental results are also selected for comparison.

With the rapid advancements of the artificial intelligence, machine learning, especially neural networks, have shown huge superiority over humans in image recognition, autonomous vehicles and medical diagnosis. However, its opacity and inexplicability provide many chances for malicious attackers. Recent researches have shown that neural networks are vulnerable to adversarial example (AE) attacks. In the testing stage, it fools the model by adding subtle perturbations to the original sample to misclassify the input, which poses a serious threat to safety-critical areas such as autonomous driving. In order to mitigate this threat, this paper proposes a hardware-assisted randomization method against AEs, where an approximate computing technique in hardware, voltage over-scaling (VOS), is used to randomize the training set of the model, then the processed data are used to generate multiple neural network models, finally multiple redundant models are used for the integrated classification and detection of the AEs. Various AE attacks on the proposed defense are evaluated to prove its effectiveness.

With the improvement of computing power and storage level, Machine Learning (ML), especially Deep Learning (DL), has shown its capabilities beyond humans in areas such as image recognition, speech processing, and content recommendation. However, the data collected to build ML models often contains sensitive information, and models may have high commercial value. Compared with the security problem of model prediction errors caused by malicious external influences, privacy threats have not attracted widespread attention, and they have characteristics that are difficult to define and detect. This article reviews recent research progress on ML privacy. First, the privacy threats on data and models in different scenarios are described in detail. Then, typical privacy protection methods are introduced. Finally, the limitations and future development trends of ML privacy research are discussed.

In many realistic applications, the collected inputs of DNN face a big challenge: perturbations. Although the perturbations are imperceptible, they may cause incorrect prediction results. This paper proposes prediction stability to quantitatively evaluate whether the prediction result of an input is instable and easy to be perturbed. Prediction stability can guide the DNN system to cope with the situation where the prediction result has a high confidence but with a low stability. Experimental result shows that, using the proposed metrics to evaluate the stability of prediction results, over 99.8 cases are consistent with the real stable/instable conditions.

Strong physical unclonable function (PUF) is a promising lightweight hardware security primitive for device authentication. However, it is vulnerable to machine learning attacks. This paper demonstrates that even a recently proposed dual-mode PUF is still can be broken. In order to improve the security, this paper proposes a highly flexible machine learning resistant configurable tristate (CT) PUF which utilizes the response generated in the working state of Arbiter PUF to XOR the challenge input and response output of other two working states (ring oscillator (RO) PUF and bitable ring (BR) PUF). The proposed CT PUF is implemented on Xilinx Artix-7 FPGAs and the experiment results show that the modeling accuracy of logistic regression and artificial neural network is reduced to the mid-50%.

Physical unclonable function (PUF) is a promising lightweight hardware security primitive for resource-constrained systems. It can generate a large number of challenge-response pairs (CRPs) for device authentication based on process variations. However, attackers can collect the CRPs to build a machine learning (ML) model with high prediction accuracy for the PUF. Recently, a lot of ML-resistant PUF structures have been proposed, e.g., a multiplexer-based PUF (MPUF) was introduced to resist ML attacks and its two variants (rMPUF and cMPUF) were further proposed to resist reliability-based and cryptanalysis modeling attacks, respectively. In this article, we propose a general framework for ML attacks on strong PUFs, then based on the framework, we present two novel modeling attacks, named logical approximation and global approximation, that use artificial neural network (ANN) to characterize the nonlinear structure of MPUF, rMPUF, cMPUF, and XOR Arbiter PUF. The logical approximation method uses linear functions to approximate logical operations and builds a precise soft model based on the combination of logical gates in the PUF. The global approximation method uses the function sinc with filtering characteristics to fit the mapping relationship between the challenge and response. The experimental results show that the proposed two approximation attacks can successfully model the (n, k)-MPUF (k = 3,4), (n, k)-rMPUF (k = 2,3), cMPUF (k = 4,5), and l-XOR Arbiter PUF (l = 3, 4, 5) (n = 32, 64) with the average accuracies of 96.85%, 95.33%, 94.52%, and 96.26%, respectively.

Deep neural networks (DNNs) have shown huge superiority over humans in image recognition, speech processing, autonomous vehicles, and medical diagnosis. However, recent studies indicate that DNNs are vulnerable to adversarial examples (AEs), which are designed by attackers to fool deep learning models. Different from real examples, AEs can mislead the model to predict incorrect outputs while hardly be distinguished by human eyes, therefore threaten security-critical deep-learning applications. In recent years, the generation and defense of AEs have become a research hotspot in the field of artificial intelligence (AI) security. This article reviews the latest research progress of AEs. First, we introduce the concept, cause, characteristics, and evaluation metrics of AEs, then give a survey on the state-of-the-art AE generation methods with the discussion of advantages and disadvantages. After that, we review the existing defenses and discuss their limitations. Finally, future research opportunities and challenges on AEs are prospected.

Since the threat of malicious software (malware) has become increasingly serious, automatic malware detection techniques have received increasing attention, where machine learning (ML)-based visualization detection methods become more and more popular. In this paper, we demonstrate that the state-of-the-art ML-based visualization detection methods are vulnerable to Adversarial Example (AE) attacks. We develop a novel Adversarial Texture Malware Perturbation Attack (ATMPA) method based on the gradient descent and L-norm optimization method, where attackers can introduce some tiny perturbations on the transformed dataset such that ML-based malware detection methods will completely fail. The experimental results on the MS BIG malware dataset show that a small interference can reduce the accuracy rate down to 0% for several ML-based detection methods, and the rate of transferability is 74.1% on average.

Recently, code reuse attacks (CRAs), such as return-oriented programming (ROP) and jump-oriented programming (JOP), have emerged as a new class of ingenious security threats. Attackers can utilize CRAs to hijack the control flow of programs to perform malicious actions without injecting any codes. Many defenses, classed into software-based and hardware-based, have been proposed. However, software-based methods are difficult to be deployed in practical systems due to high performance overhead. Hardware-based methods can reduce performance overhead but may require extending instruction set architectures (ISAs) and modifying the compiler or suffer the vulnerability of key leakage. To tackle these issues, this paper proposes a new hardware-assisted control flow checking method to resist CRAs with negligible performance overhead without extending ISAs, modifying the compiler or leaking the encryption/decryption key. The key technique involves two control flow checking mechanisms. The first one is the encrypted Hamming distances matching between the physical unclonable function (PUF) response and the return addresses, which prevents attackers from returning between gadgets so long as the PUF response is secret, thus resisting ROP attacks. The second one is the linear encryption/decryption operation (XOR) between the PUF response and the instructions at target addresses of call and jmp instructions to defeat JOP attacks. Advanced return-based full-function reuse attacks will be prevented with the dynamic key-updating method. Experimental evaluations on benchmarks demonstrate that the proposed method introduces negligible 0.95% runtime overhead and 0.78% binary size overhead on average.

Field-programmable gate array (FPGA) is a kind of programmable chip that is widely used in many areas, including automotive electronics, medical devices, military and consumer electronics, and is gaining more popularity. Unlike the application specific integrated circuits (ASIC) design, an FPGA-based system has its own supply-chain model and design flow, which brings interesting security and trust challenges. In this survey, we review the security and trust issues related to FPGA-based systems from the market perspective, where we model the market with the following parties: FPGA vendors, foundries, IP vendors, EDA tool vendors, FPGA-based system developers, and end-users. For each party, we show the security and trust problems they need to be aware of and the associated solutions that are available. We also discuss some challenges and opportunities in the security and trust of FPGA-based systems used in large-scale cloud and datacenters.

Control-flow integrity (CFI) plays a very important role in defending against code reuse attacks by protecting the control flows of programs from being hijacked. However, previous CFI methods suffer from performance overheads, cost, or security issues. In this paper, we propose a new CFI based on a lightweight encryption architecture with advanced encryption standard (LEA-AES) to address the challenges above. The LEA exploits AES to encrypt and decrypt return addresses and instructions at indirect jump destinations, which protects function calls and indirect jumps from being reused by return-oriented programming (ROP) and jump-oriented programming (JOP) attacks. For ROP, the encryption and decryption of return addresses are performed when the call and ret instructions are executing; for JOP, the encryption of instructions are performed when programs are loading into memory and the decryption of instructions are performed right before they are executing. The LEA-AES does not need to revise instruction sets of CPU and its security is also guaranteed by the encryption mechanism in addition to its high performance. Experimental results showed that the run-time and loading time overheads of LEA-AES are both less than 4% and the memory overhead is 0.62%.

Watermarking as a novel intellectual property (IP) protection technique can protect field-programmable gate array IPs from infringement. However, existing watermarking techniques may give away sensitive information during the public verification, which enables malicious verifiers or third parties to remove the embedded watermark and resell the design. Current zero-knowledge watermarking verification schemes can address the sensitive information leakage issue but are vulnerable to embedding attacks, which makes them ineffective in preventing the infringement denying of untrusted buyers (verifiers). This paper proposes a new publicly verifiable watermarking detection technique based on chaos-based zero-knowledge interaction and time stamping to resiliently resist the sensitive information leakage and embedding attacks, and is thus robust to the cheating from the prover, verifier, or third party. Experimental results and analysis show that the proposed method has better robustness than the most recent related literature.

Recently, code reuse attacks (CRAs) have emerged as a new class of ingenious security threatens. Attackers can utilize CRAs to hijack the control flow of programs to perform malicious actions without injecting any codes. Existing defenses against CRAs often incur high memory and performance overheads or require extending the existing processors' instruction set architectures (ISAs). To tackle these issues, we propose a hardware-based control flow integrity (CFI) that employs physical unclonable functions (PUF)-based linear encryption architecture (LEA) to protect against CRAs with negligible hardware extending and run time overheads. The proposed method can protect ret and indirect jmp instructions from return oriented programming (ROP) and jump oriented programming (JOP) without any additional software manipulations and extending ISAs. The pre-process will be conducted on codes once the executable binary is loaded into memory, and the real-time control flow verification based on LEA can be done while ret and jmp instructions are executed. Performance evaluations on benchmarks show that the proposed method only introduces 0.61% run-time overhead and 0.63% memory overhead on average.

Concerns have been raised about our recently published article on a PUF-FSM binding scheme for FPGA IP protection and Pay-per-Device licensing. In a comment, the authors first analyzed the simple 4-bit license example we used in the article and claimed that the low overhead configuration of the FSM binding does not provide sufficiently high level of security. Then they analyzed the FSM binding structure and claimed that when a 128-bit long license is used to provide high security, the PUF-FSM scheme will incur unacceptable overhead. Both the analyses seem correct. However, they focus on some illustrative examples of our proposed binding scheme, not the main contribution which is a non-encryption based binding mechanism and its application to FPGA IP protection and pay-per-device licensing. The first claim on the low security of the 4-bit license example is true, but it is just a simple example, in reality, the key/license will be much longer. For the second claim, the balance of overhead and security can be addressed by some simple tricks such as adding few black holes used in FSM binding and the augment of number of inputs of STG. In this rebuttal, we will elaborate these.

A number of studies of hardware security aim to thwart piracy, overbuilding, and reverse engineering (RE) by obfuscating and/or camouflaging. However, these techniques incur high overheads, and integrated circuit (IC) camouflaging cannot provide any protection for the gate-level netlist of the third party intellectual property (IP) core or the single large monolithic IC. In order to circumvent these weaknesses, this brief elaborately analyzes these hardware security techniques and proposes a practical logic obfuscation method with low overheads to prevent an adversary from RE both the gate-level netlist and the layout-level geometry of IP/IC and protect IP/IC from piracy and overbuilding. Experimental evaluations demonstrate the low area, power, and zero performance overhead of the proposed obfuscation technique.

Ring oscillator Physical Unclonable Function (RO PUF) is a popular silicon PUF due to its ease of implementation on both ASIC and FPGA. However, RO PUFs have severe reliability issues when the operating environment deviates from the nominal condition and security issues as cloning attacks have been reported. In this work, we propose to build configurable RO PUFs based on the notions of configurable RO PUF [6, 16] and highly flexible RO PUF [22] to address these concerns. First, we demonstrate how to build RO PUF from single flexible ROs, which improves both the reliability and hardware efficiency of RO PUFs. Then we propose a novel dual voltage based configurable RO PUF to mitigate the cloning attacks. Our experimental results show that our configurable RO PUFs are more reliable and hardware efficient than the existing RO PUF designs. Using the flexible RO PUF [22] as baseline, we have reduced the bit flip rate by 69% and improve the hardware utilization by 136%. In addition, the anti-cloning approach generates PUF data significantly different from the original PUF secret (average 47.5% Hamming distance) which makes potential cloning attacks very difficult.

Hardware Trojans (HTs) can be implanted in security-weak parts of a chip with various means to steal the internal sensitive data or modify original functionality, which may lead to huge economic losses and great harm to society. Therefore, it is very important to perform hardware Trojan detection and diagnosis, find potential safety hazards and apply protection techniques in the whole IC design cycle, in order to enhance the security of chips. In this paper, we elaborate an IC market model, and describe the potential HT threats faced by the parties involved in the model. Then we survey the recent research advances in the countermeasures against HT attacks, which are classified into HT detection, diagnosis and prevention. Finally, the challenges and prospects for HT defense are illuminated.

In this letter, a target tracking approach, which combines short-time Fourier transform (STFT) and linear predictive coding (LPC), is proposed for a Doppler through-wall radar. The LPC is applied to extend the known echo data in each STFT sliding window, thus helping in improving the estimation accuracy of target instantaneous frequency. Compared with the traditional LPC process which determines the prediction data size empirically, the proposed approach takes advantage of the fitting error array as a control parameter to intelligently adjust the data size and reduce the prediction error. Moreover, the proposed approach can also enhance the radar processing efficiency by preventing the unqualified prediction data, which is of great importance for real-time detecting applications. Series of experimental measurements are presented as a preliminary assessment of the proposed approach.

With its reprogrammability, low design cost, and increasing capacity, field-programmable gate array (FPGA) has become a popular design platform and a target for intellectual property (IP) infringement. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require permanent secret key storage in the FPGA. In addition, they cannot provide a commercially popular pay-per-device licensing solution. In this paper, we propose a novel IP protection mechanism to restrict IP's execution only on specific FPGA devices in order to efficiently protect IPs from being cloned, copied, or used with unauthorized integration. This mechanism can also enforce the pay-per-device licensing, which enables the system developers to purchase IPs from the core vendors at the low price based on usage instead of paying the expensive unlimited IP license fees. In our proposed binding-based mechanism, FPGA vendors embed into each enrolled FPGA device with a physical unclonable function (PUF) customized for FPGAs; IP vendors embed augmented finite-state machines (FSM) into the original IPs such that the FSM can be activated by the PUF responses from the FPGA device. We propose protocols to lock and unlock FPGA IPs, demonstrate how PUF can be embedded onto FPGA devices, and analyze the security vulnerabilities of our PUF-FSM binding method. We implement a 128-bit delay-based PUF on 28-nm FPGAs with only 258 RAM-lookup tables and 256 flipflops. The PUF responses are unique and reliable against environment changes. We also synthesize a variety of FSM benchmark circuits. On large benchmarks, the average timing overhead is 0.64% and power overhead in 0.01%.

The FPGA replay attack, where an attacker downgrades an FPGA-based system to the previous version with known vulnerabilities, has become a serious security and privacy concern for FPGA design. Current FPGA intellectual property (IP) protection mechanisms target the protection of FPGA configuration bitstreams by watermarking or encryption or binding. However, these mechanisms fail to prevent replay attacks. In this article, based on a recently reported PUF-FSM binding method that protects the usage of configuration bitstreams, we propose to reconfigure both the physical unclonable functions (PUFs) and the locking scheme of the finite state machine (FSM) in order to defeat the replay attack. We analyze the proposed scheme and demonstrate how replay attack would fail in attacking systems protected by the reconfigurable binding method. We implement two ways to build reconfigurable PUFs and propose two practical methods to reconfigure the locking scheme. Experimental results show that the two reconfigurable PUFs can generate significantly distinct responses with average reconfigurability of more than 40%. The reconfigurable locking schemes only incur a timing overhead less than 1%.

Physical unclonable function (PUF) is a promising hardware security primitive that can be applied to various security related areas. The ring oscillator (RO) PUF is one of the most popular PUFs that can generate the volatile key by comparing the frequency between ROs. Previous RO PUFs incur unacceptable hardware overheads to improve the reliability in order to eliminate the effect of environment factors. In this paper, we propose a frequency offset algorithm (FOA) to enhance the reliability and low the hardware overhead. The key idea is to make the frequency difference larger than a given threshold by offsetting the frequencies of RO pairs. Experimental results show that our proposed FOA method has the better reliability and lower hardware overhead than the temperature-aware cooperative (TAC). Especially, our proposed method can achieve the 100% utilization of ROs.

This survey reviews the security and trust issues related to FPGA-based systems from the market perspective. For each party involved in FPGA supply and demand, we show the security and trust problems they need to be aware of and the solutions that are available.

Physical Unclonable Function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA Intellectual Property (IP) protection, key generation and digital rights management. Ring Oscillator (RO) based PUF and Arbiter-based PUF are the most popular PUFs, but they are not specially designed for FPGA. RO-based PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires ``hard macros'' to implement on FPGA. The arbiter-based PUF brings low resource overhead, but its structure is hard to be mapped on FPGA. Anderson'PUF can address these weaknesses of current Arbiter-based and RO-based PUFs. However, it cannot be directly implemented on the new generation FPGAs, and therefore it has the scalability issue. In order to address these problems, this paper presents a delay-based PUF using the intrinsic structure of FPGA (look-up table and multiplexer). The proposed delay-based PUF is completely realized on 28nm FPGAs. The experimental results show its high uniqueness and reliability. Moreover, we test the proposed PUF in the high temperature, and the results show its availability. Finally, the prospect of the proposed PUF in the FPGA IP protection is discussed.

The continuous growth in both capability and capacity for FPGA now requires significant resources invested in the hardware design, which results in two classes of main security issues: 1) the unauthorized use and piracy attacks including cloning, reverse engineering, tampering etc. 2) the licensing issue. Binding hardware IPs (HW-IPs) to specific FPGA devices can efficiently resolve these problems. However, previous binding techniques are all based on encryption and hence have three main drawbacks: 1) encryption-based proposals in commercial are limited to protect the single large FPGA configuration, 2) many encryption-based proposals depend on a trusted third party to involve the licensing protocol, and 3) the encryption-based binding methods use costly mechanisms such as secure ROM or flash memory to store FPGA specific cryptographic keys, which is not only expensive but also vulnerable to side-channel attacks, and the management and transport of secret keys became a practical issue. In this work, we propose a PUF-FSM binding technique completely different from the traditional encryption-based methods to address these shortcomings.

In this paper we propose a novel binding mechanism that can protect FPGA IP from being cloned, tampered, or misused; and facilitate the pay-per-use licensing to limit the FPGA IP's execution to specific FPGA devices only. In this mechanism, the FPGA vendors will provide each enrolled device with a Physical Unclonable Function (PUF) that can be deployed securely during fabrication process. The core vendor will embed an augmented Finite State Machine (FSM) into the original FSM structure of the hardware IP (HW-IP) to react on the PUF response to a given challenge. The proposed binding method does not need any Trusted Third Party (TTP) or block cipher for key management and exchange. We analyze several known attacks to hardware IP and show that our method is secure against these attacks. Experimental results on MCNC benchmarks show that the proposed method incurs small design overhead in terms of area, power and delay.