Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are critical elements susceptible to undergoing defects at steps, such as fabrication and bonding or during their lifetime. Resistive open defects have become one of the most frequent failure mechanisms affecting TSVs. They include microvoids, underfilling, misalignment, pinholes in the oxide, or misalignment during bonding, among others. Although considerable research effort has been made to improve the coverage of TSV testing, little attention has been paid to weak (resistive) open defects causing small delays. In this work, a postbond oscillation test strategy to detect such small delay defects is proposed. Variations in the duty cycle of transmitted signals after unbalanced logic gates are shown to help in the detection of weak open defects in TSVs. HSPICE simulations, including process parameter variations, have been considered, and results show the effectiveness of the method in the detection of weak open defects above 1 kΩ. Experimental work on a 65-nm IC also corroborates the detection capability of the proposal.

In this paper we propose a methodology for reliability evaluation, failure prediction, and failure mitigation of a STT-MRAM memory under different supply voltage conditions (i.e., DVS scenarios). The methodology is based on the design of read/write failure predictor registers which are able to predict the memory failure probability for a given DVS scenario. The predicted results are used to re-tune the supply voltage such that the memory reliability is assured.

Binning after volume production is a widely accepted technique to classify fabricated integrated circuits (ICs) into different clusters depending on different degrees of specification compliance. This allows the manufacturer to sell nonoptimal devices at lower rates, so adapting to customer's quality-price requirements. The binning procedure can be carried out by measuring every single circuit performances, but this approach is costly and time-consuming. On the contrary, if alternate measurements are used to characterize the bins, the procedure is considerably enhanced. In such a case, the specification bin boundaries become arbitrary shape regions due to the highly nonlinear mappings between the specifications space and the alternate measurements space. The binning strategy proposed in this paper functions with the same efficiency regardless of these shapes. The digital encoding of the bins in the alternate measurements space using octrees is the key idea of the proposal. The strategy has two phases: 1) the training phase and 2) the binning phase. In the training phase, the specification bins are encoded using octrees. This first phase requires sufficient samples of each class to generate the octree under realistic variations, but it only needs to be performed once. The binning phase corresponds to the actual production binning of the fabricated ICs. This is achieved by evaluating the alternate measurements in the previously generated octree. The binning phase is fast due to the inherent sparsity of the octree data structure. In order to illustrate the proposal, the method has been applied to a band-pass Butterworth filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages as compared to a support vector machine (SVM)-based classifier. Similar bin misclassifications are obtained with both methods, 1.68% using octrees and 1.83% using SVM, while binning time is 5x faster using octrees than using the SVM-based classifier.

Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process to prevent stacking yield loss. Thus, the development of effective prebond testing techniques becomes of great importance. In this direction, recent research effort has been devoted to the development of two main prebond techniques: 1) prebond probing and 2) built-in self-test (BIST) techniques. The prebond probing poses economic and technological challenges, whereas current BIST proposals have disadvantages for certain solutions. Hence, there is still a need for an effective methodology in terms of fault coverage, area overhead, and test time. This paper proposes a BIST technique based on a simple unbalanced circuit comparing the behavior of two TSVs. Electrical simulation results show the viability of the proposal to detect weak defects, i.e., resistive opens and resistive bridges, adding reasonable area overhead in a short-test application time. Furthermore, an experimental design is built on a 65-nm technology, where resistive open defects are intentionally injected. Automated test equipment measurements confirm the simulation results.

Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.

One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper, we estimate the STT-MRAM cell reliability under fabrication- and aging-induced process variability, by evaluating its failure probability. We analyze the effect of control voltage tuning on the fresh and aged cell failure probabilities and, as a result, we propose a power- and aging-aware circuit level variability mitigation technique based on control voltage tuning. We observed that increasing the values of control voltages, the cell failure probability is reduced at different extends (according to the control voltage under variation), but also that the power consumption is increased. As a result, we have identified the control voltage with the highest impact on the fresh cell reliability, and on the endurance of the cell under study. Subsequently, by performing a power/reliability trade-off analysis, the appropriate value of this control voltage is determined.

Binning of IC circuits after volume fabrication is widely used to separate tested circuits in different classes depending on different degrees of specifications compliance. When the specifications are directly measured, the boundaries of the classes are usually linear functions in the specification space. For alternate testing strategies the indirect measures generate more complicated regions in the measure space due to the non linear mapping between the specification space and the measure space. The binning strategy proposed in this paper works with the same efficiency regardless of the shape of the boundaries of each binning region. A digital encoding of the measure space using octrees is the key idea of the proposal. The strategy has two phases: (1) The training to generate the digital codes for the binning subsets and (2) the actual production binning of the fabricated ICs. The first phase is performed only once and requires sufficient samples of each binning class to generate the octree under realistic variations. The second phase is fast and requires only to evaluate the octree using the measures of the tested IC. In order to illustrate the proposal, the method has been applied to a Biquad filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages in terms of binning speed. In addition, the method has been compared to a SVM classifier revealing substantial benefits.

Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent failure mechanism affecting TSVs. Although there is considerable research effort dedicated to improve TSVs testing, no much attention has been paid to weak defects, especially to weak open defects (resistive opens) causing small delays. In this work, a testing strategy is proposed to detect small delay defects by means of a post-bond oscillation test. Variations in the Duty Cycle of transmitted signals after unbalanced logic gates are shown to detect weak open defects in TSVs. HSPICE simulations including process parameter variations show the effectiveness of the method in the detection of weak open defects above 1 kΩ.

Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and may undergo defects during the fabrication process and also during their life time. The detection of defective TSVs in the earliest process step is of major concern. For this reason, testing TSVs is usually done at different stages of the fabrication process. In fact, effective pre-bond testing is a key factor to prevent stacking yield loss. Extensive research effort has been devoted to develop efficient pre-bond techniques. In this direction, two main approaches have been explored: pre-bond probing and built-in self test (BIST) techniques. Pre-bond probing is challenging since TSVs are too small for standard test probes and the number of probe pads for testing is not affordable. Present BIST proposals have some disadvantages depending on the particular solution considered, namely: the detection of certain types of defects solely, inability to detect weak defects, large area overhead and long test application time. In this context, this work proposes a simple solution, adding low area overhead and fast application test procedure. Simulation results confirm the proposal viability.

Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects.

Testing M-S circuits is a difficult task demanding high amount of resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure metrics. In this work, a testing technique using octrees in the measure space is presented. Octrees have been used in computer graphics with successful results for rendering, image processing and space clustering applications. In this paper are used to encode the test acceptance region with arbitrary precision after an statistical training phase. Such representation allows an efficient way to test a candidate circuit in terms of test application time. The method is applied to test a Biquad filter with encouraging results. Test escapes and test yield loss caused by parametric variations have been estimated.

Accurate diagnosis of open defects is key to identifying process problems and achieving fast yield improvement. Current diagnosis methodologies for interconnect full open defects have demonstrated their efficiency, assuming that the defective line voltage is mainly determined by neighboring lines and downstream transistor parasitic capacitances. However, the continuous reduction of oxide thickness with every technology node increases gate leakage current significantly, even for high-kdielectrics. In this context, in nanometer CMOS technologies, the defective line cannot be assumed to be electrically isolated because of the impact of gate leakage currents, which may invalidate diagnosis results provided by present methodologies. In this paper, a new methodology is proposed to diagnose interconnect full open defects under the influence of gate leakage currents in CMOS technologies. To the authors' knowledge, such influence has not been previously considered by any of the existing methodologies. Simulation and experimental results demonstrate the proposal efficiency.

The efficiency of different assist techniques for SRAM cell functionality improvement under the influence of random process variation is studied in this paper. The sensitivity of an SRAM cell functionality metrics when using control voltage level assist techniques is analyzed in read and write operation modes. The efficiency of the assist techniques is estimated by means of parametric analysis. The purpose is to find the degree of functionality metric improvement in each operation mode. The Acceptance Region concept is used for parametric analysis of SRAM cell functionality under random threshold voltage variations. In order to increase the reliability of the SRAM several assist techniques, chosen among the most efficient ones for each operation mode, are considered. This analysis offers a qualitative indication of the cell's functionality improvement by means of the efficient computation of a metric in parameter domain analysis. The results are proven to have high correlation with the ones obtained by means of the classical Monte Carlo simulations with significant savings in comparing different assist techniques.

Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise.

Process variability is becoming a major challenge in CMOS design of general and embedded SRAMs in particular due to continuous device scaling. The main problems are the increased static power and reduced operating margins, robustness and reliability. A common way to reduce the static power consumption of an SRAM memory array is to decrease its supply voltage when in memory retention mode. However, this leads to a further reduction in memory robustness. The most common tool for statistical analysis of circuits under process variability is standard Monte Carlo simulation which has been proven to be too expensive when applied on an ultra dense SRAM. In this paper a statistical robustness analysis method is proposed based on decoupling statistical integration from robustness region determination in the parameter domain. The robustness is estimated with a ~ 556X speed up relation to Monte Carlo and an error of ~ 1%.

One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRAM cell. This paper statistically analyzes the behavior of the 6T SRAM cell in data retention mode, under process variability. The failure probabilities under various supply voltages are determined for different technology nodes, and the Data Retention Voltage is determined. For the 45nm PTM SRAM cell under random threshold voltage variation, the Data Retention Voltage is found to be 423mV while for the 16nm PTM SRAM, the DRV is 649mV.

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to user's requirements.

A novel family of codes for the detection, localization and correction of unidirectional errors for DRAMs in proposed. For DRAM memories, multi-bit soft and hard errors are a growing concern, as the cell sizes continue to decrease with aggressive scaling down. As a result, the classical error detection/correction codes become less efficient to deal with multiple errors in a single word [16]. Berger codes are effective in detecting 100% of the unidirectional errors, but introduce considerable delay and does not provide any error correction feature. In order to decrease the computing time of the code check bits and, at the same time, to provide the possibility to localize the segment(s) where single or multiple errors have occurred, a modification of the Berger code is proposed, called Carry Save K Berger code (CS-K Berger). Basically consists in using Carry Save representations of the partial additions of the word segments. The number of check bits increases as compared with Berger code and consequently the code redundancy overhead increases but the delay in computing the check bits and the corresponding checking is drastically reduced. In addition, some patterns of unidirectional errors become correctable. The proposed CS-K Berger codes for different values of K are analyzed for different word lengths. The hardware required for code generation and verification is discussed as well, as the possibility of using this code for word segment replacement in online applications of DRAMs.

The development of accurate diagnosis methodologies is important to identify process problems and achieve fast yield improvement. As open defects are becoming dominant in some CMOS technologies, their accurate diagnosis is key to improving the quality of new very large-scale integrated circuits. Widely used interconnect full open diagnosis procedures are based on the assumption that neighboring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, where the influence of transistor capacitances is significant. This paper presents a diagnosis methodology for interconnect full open defects which considers and models the impact of transistor parasitic capacitances on the defective node accurately. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behavior. Diagnosis results for real defective devices from different technology nodes are also provided.

An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies.

Production verification of analog circuit specifications is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A digital signature is obtained using the digital code and its time duration. A metric defining a discrepancy factor is used to verify circuit parameters. The method is applied to detect possible deviations in the natural frequency of a Biquad filter. Simulated and experimental results show the possibilities of the proposal.

The development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes a key factor. Widely used interconnect full open diagnosis procedures are based on the assumption that neighbouring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, when the influence of transistor capacitances becomes important. This work presents a diagnosis methodology for interconnect full open defects where the impact of transistor parasitic capacitances is included. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behaviour. Diagnosis results for real defective devices from different technology nodes are presented.

Increased die-to-die and on-die variations in scaled technologies can lead to parametric failures (Read/Write/Access) in embedded SRAMs. Conventionally, SRAM bit-cell failure analysis is based on the Static Noise Margin (SNM), a metric that leads to conservative estimate of design yield. In this paper we present a method of dynamic noise margin (DNM) estimation based on the modeling technique developed that can efficiently estimate failures in bit-cells under parameter variations. The proposed DNM estimation method is fast, and can accurately estimate the SRAM yield. Monte Carlo simulation results show that the proposed DNM closely matches the results from SPICE analysis.

Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

Full open defects on interconnect lines cause broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and trapped charge. However, in nanometer CMOS technologies gate oxide thickness is reduced below a few tens of A, resulting in the gate tunnelling leakage strongly influencing the behaviour of defective circuits with full open defects. Floating lines cannot be considered electrically isolated anymore and are subjected to transient evolutions until reaching a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of gate tunnelling leakage are expected to increase for future technologies. The transient response of full open defects on interconnect lines is analysed for nanometer technologies based on predictive technology models. A method to estimate the delay of defective circuits is proposed. Experimental evidence of this behaviour is presented for a test chip design of 0.18 mum technology.

Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and the trapped charge. However, in nanometric CMOS technologies, the oxide thickness is reduced below a few tens of Aring causing the gate tunnelling leakage to strongly impact the behaviour of defective circuits with full open defects. Floating lines can not be considered electrically isolated anymore and are subjected to transient evolutions until arriving at a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of the gate tunnelling leakage is expected to increase for future technologies. The analysis of full opens affecting basic CMOS gates is presented and their defective behaviour characterized. The prediction of the defective logic response of such basic gates is presented for nanometric technologies based on predictive technology models. The final steady state is found to be independent on the initial state of the floating node. Experimental evidence of this behaviour is presented for an industrial chip of 0.18 mum technology.

Open defects have been intentionally designed in a set of interconnect metal lines. In order to improve the controllability and the observability of the experimental design, a simple bus structure with a scan register followed by a hold register is used to manage the set of interconnect lines. The strength of the open defects has been varied within a realistic range of resistances ranging from a full (complete) open to a weak (low resistance) open by means of broken metal lines and transmission gates, respectively. Experiments performed with an automatic test equipment show the influence of coupling capacitances with adjacent lines on the electrical behavior of the defective line. Furthermore, experimental evidence of the history effect on the delay caused by resistive opens is investigated. Validation of the measured results by means of theoretical as well as simulation analysis is presented. Finally, some recommendations to generate stuck-at, IDDQand delay test are discussed in order to improve the detectability of such defects.

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. The authors demonstrate that the impact of downstream current is minimized at low power supply (Vdd) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at VVLVare used for the diagnosis of fifteen failing 0.18mum technology devices, which are demonstrated to contain a bridging defect.

A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.

Test-pattern generators (TPGs), based on arithmetic operations, are becoming cost-effective built-in self-test solutions for circuits with embedded processors. Similar to pseudorandom TPGs, arithmetic TPGs use reseeding to reach high levels of fault coverage (FC). In this paper, we propose a method of searching for an effective reseeding strategy, guaranteeing a specified FC level. The proposed methodology minimizes the total test time under the constraint of the total memory resource allocated to store the seeds. The minimization is performed by a binary search that speeds up the seed selection. Experiments with benchmark circuits have shown an average reduction of 43.47% in test time compared with the three previous methodologies.

Defective interconnect lines affected by open defects have been intentionally designed and introduced on a CMOS digital test circuit. A simple bus structure with a scan register followed by a hold register and two buffers is used to investigate the influence of the crosstalk capacitances of the adjacent lines to the open defect. The strength of the open defect has been varied within a realistic range of resistances going from a full (complete) open up to a weak (low-resistive) open. The static and dynamic behavior of the defective lines have been electrically characterized taking into account the location of the defect as well as its resistive value. This characterization allows the extraction of general information useful for the prediction and detection of the faulty behavior caused by the defect. Testability conditions of this defect in interconnect lines are discussed.

Signal integrity verification is becoming an important issue as technological process features continues to shrink and logic speed increases. Advanced technologies permit a large number of integrated devices onto chip, this characteristic enable to have high performance systems which request good levels of signal integrity. A monitoring technique for the verification of the signal integrity is presented. Two monitors are proposed in order to sense signal undershoots and overshoots at high and low logic levels respectively. The cost of the proposed verification strategy has been estimated in terms of area, extra pins and delay penalisation. Using coherent sampling, the monitors detect signal integrity violations for high speed critical signals.

Built-in self-test (BIST) strategies require the implementation of efficient test pattern generators (TPG) in order to excite and observe the potential faults of the circuit. Arithmetic additive TPGs (AdTPG) allow the reuse of existing internal datapaths to perform this operation without a penalty in the circuit area. As in pseudo-random generators, AdTPGs need reseeding to efficiently cover hard-to-detect faults. The test vectors targeting hard-to-detect faults are often difficult to be obtained from a simple iterative addition operation. In this paper, a strategy to generate the reseeding for an AdTPG based on a standard ALU is presented. The methodology benefits from the existence of don't-cares in the test vectors and from the insertion of dummy vectors in the test sequence. Thanks to this, a reduction of the memory requirements and the test length is achieved.

While high-quality BIST (built-in self test) based on deterministic vectors often has a prohibitive cost, pseudorandom based BIST may lead to low DC (defect coverage) values, requiring however very long test sequences with the corresponding energy waste and possible overheating due to extra switching activity caused by test vectors. The purpose of this paper is to discuss how a recently proposed RTL (register transfer level) test preparation methodology can be reused to drive innovative, high-quality/low-energy/low-power BIST solutions. RTL test generation is carried out through the definition of partially defined test vectors (masks) that, while targeting multiple detection of RTL faults lead to high DC values. An energy/power model is proposed to optimize the energy/power consumption of the test at RTL level. It is shown that the proposed method achieves better DC values with low-energy and low-power consumption, when compared to pseudo-random test excitation. The usefulness of the methodology is ascertained using the VERIDOS simulation environment in modules of the CMUDSP and TORCH ITC'99 benchmark circuits.

The estimation of maximum and minimum leakage consumption for nominal values of the processing parameters is addressed. Tight upper and lower bounds of both extremes are found. In addition, input vectors producing a consumption close to these extremes are obtained. To solve this NP-complete problem, a new hierarchical method based on automatic test pattern generation (ATPG) tools is proposed. The results obtained are compared with Monte Carlo simulations and alternative approaches based. on other heuristics. The results obtained show that the maximum and minimum leakage consumption is estimated with an error lower than 8%. For the largest circuits, c6288 and c7552, the maximum error is lower than 1.3%. The results show that the method compares favorably with alternative approaches.

Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.

The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault." Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.

A new BIST structure, based on the information provided by the XY-operation (Lissajous curves) is introduced in this paper. A digital signature is obtained which is used to discriminate catastrophic as well as parametric defects. High fault coverage is achieved when applying the proposed BIST on an ITC'97 benchmark circuit where 92% of the catastrophic defects and 87.5% of the parametric defects analyzed produced digital signatures clearly distinguishable from the golden signature.

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach is applied to the XILINX SPARTAN, 4000 and 3000 families. On these examples of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then for a single logic cell, and finally for the m/spl times/m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a single logic cell. An approach is then described to define a minimum number of test configurations for a logic cell knowing the test configurations of its logic modules. This approach gives only 4 test configurations for the XILINX Spartan, 5 for the 4000 and 4 for the 3000 while the previous published works concerning Boolean testing of these FPGA families give 8 for the 4000 and 5 for the 3000.

The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. In usual SRAM-based FPGAs, Configurable Interface Modules (CIMs) can be found between the global interconnect and inputs of the logic cells (input CIMs) or between output of the logic cells and the global interconnect (output CIMs). It is demonstrated that an input CIM that connects N/sup in/ segments to a logic cell input requires N/sup in/ test configurations and that an output CIM that connects a logic cell output to N/sup out/ segments requires 2 test configurations. Then, it is proven that a set of K/sup in/ input CIMs can be tested in parallel making the number of required test configurations equal to N/sup in/. In the same way, a set of K/sup out/ output CIMs is shown to require only 2 test configurations if N/sup out/>K/sup out/. Finally, it is shown that the complete mXm array of logic cells with K/sup in/ input CIMs and K/sup out/ output CIMs can be tested with only N/sup in/ test configurations using the XOR tree and shift register structures.

The feasibility of combining I/sub DDQ/ and and i/sub DDt/ testing to detect defective CMOS circuits by measuring the energy consumed by the tested circuit is considered. The energy chronogram of a circuit is used as an energy signature which makes it possible to distinguish between defect-free and defective circuits. Exploratory implementation of the proposed method is presented and experimental results obtained from in-house full custom circuits and commercially available circuits are discussed.

The purpose of this paper is to analyze an optimization method to improve the testability of structural defects, such as bridges and opens, in low-power low-voltage analog circuits. The approach consists of finding an optimum subset of tests which maximizes the fault coverage with minimum cost. An application example is given to illustrate the proposal by studying the fault coverage obtained using different test sets on a simple 2-stage Nested Transconductance Capacitance Compensated (NGCC) amplifier.

This paper address the problem of testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. The Configurable Interface Modules (CIMs) are assumed to be implemented with FPGA multiplexers but the results can be easily extended to any type of interface module. First, it is demonstrated that an address bit Configurable Interface Multiplexer requires N=2/sup n/ test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analysed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N=2/sup n/. Third, it is shown that the complete circuit, i.e. a m/spl times/m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N=2/sup n/ test configurations using the XOR tree and shift register structures.

This paper presents a novel technique for testing Field Programmable Gate Arrays (FPGAs), suitable for use in the case of frequent FPGA reuse and rapid dynamic modifiability of the implemented function.

This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic test configurations to fully test the whole matrix of CLBs. In the proposed test configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of test configurations 8 is fixed and independent of the FPGA size.

The defective I/sub DDQ/ in deep-submicron full complementary MOS circuits with shorts is estimated. High performance and also low power scenarios are considered. The technology scaling, including geometry reductions of the transistor dimensions, power supply voltage reduction, carrier mobility degradation and velocity saturation, is modeled. By means of the characterization of the saturation current of a simple MOSFET, a lower bound of I/sub DDQ/ defective consumption versus L/sub eff/ is found. Quiescent current consumption lower bound for shorts intragate, and shorts intergate affecting at least one logic node is evaluated. The methodology is used to estimate the I/sub DDQ/ distribution, for a given input vector, of defective circuits. This I/sub DDQ/ estimation allows the determination of the threshold value to be used for the faulty/fault-free circuit classification.

This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2/sup N/ memory cells is proposed taking into account the LUT and RAM modes. Concerning the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the march tests. We also propose a unique test configuration called 'pseudo shift register' for mxm arrays of modules. In this configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called 'shifted MATS++' is described. Concerning the LUT mode, we use the concept of non-redundant test that proposes to test in LUT mode the parts of the module not tested in RAM mode. Under this hypothesis, it is demonstrated that the test of a single module as well as the test of an mxm array of modules require only 3 test configurations. Using our solution, the test of a complete array of mxm LUT/RAM modules requires 4 test configurations independently of the size of the array and of the modules.

The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. Two techniques to test open defects producing data retention faults are proposed. In the first technique an initial condition is forced during the working phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (I/sub DDQ/) increases and the fault can be detected sensing the I/sub DDQ/. A second technique controlling the power supply level in conjunction with sequential access is proposed. This allows detection of open defects by I/sub DDQ/ testing. The cost of both proposed approaches is analyzed.

The test of the Configurable Logic Blocks of RAM based FPGAs under a Stuck-At fault model has been studied. The high cost of changing the configuration, by reprogramming the FPGA during testing, forces a strategy to reduce the number of different configurations used for testing purposes. After finding the optimal solutions for the elementary structures of the Logic block, Multiplexers and Look-Up Tables, the problem of testing interconnected elementary structures is addressed. The method is illustrated using an elementary structure and then applied to a popular FPGA (XILINX 3000 family) where a reduced set of configurations (5) and their corresponding test sequences is found to cover all (100%) the Configurable Logic Block faults modelled.

The effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and non-defective quiescent currents. Consequently, the interest in characterizing these currents is growing. In this paper we focus our attention on the non-defective I/sub DDQ/ current characterization. The dependence of I/sub DDQ/ on the channel length spread in scaled down devices is examined. The I/sub DDQ/ distribution of a subthreshold current dominant technology is obtained. Finally, I/sub DDQ/ test limits depending on acceptable yield loss and standard deviation of the channel length are determined.

This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.

The I/sub DDQ/-V/sub DD/ signature for sequential CMOS circuits with bridging defects is characterized. In combinational circuits with a bridging defect, an increase in V/sub DD/ results in a higher I/sub DDQ/ value flowing through the defect, however, the total current may decrease as it will be shown. In sequential circuits with bridging defects connecting control loop nodes, the V/sub DD/-I/sub DDQ/ signature may present intervals of constant non defective I/sub DDQ/ value. The signature may be used to diagnose certain types of bridging defects in sequential CMOS circuits.

The quiescent current (I/sub DDQ/) consumed by an IC is a good indicator of the presence of a large of defects. However, the effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and defect-free currents and hence it becomes necessary to estimate the currents involved in order to design the I/sub DDQ/ sensing circuitry. In this work, we present a method to estimate the non-defective I/sub DDQ/ consumption based on a hierarchical approach using layout (device), electrical (cell) and logic (circuit) information. The maximum of the defect-free I/sub DDQ/ is obtained with a technique based on ATPG. The results show that the proposed method gives the maximum defect-free I/sub DDQ/ for small circuits. For large circuits, heuristics to find lower and upper bounds of the maximum defect-free I/sub DDQ/ are presented. Uncertainty margins lower than 15% have been found in the circuits experimented on.

Parity prediction arithmetic operator schemes have been widely studied in the past. Recently, it has been demonstrated that this prediction scheme can achieve Fault-Secureness in arithmetic circuits for stuck-at and stuck-open faults. In this paper it is shown that the detection capability improves if a current monitoring technique is used in conjunction with the parity prediction scheme. With this scheme the fault-secure property extends to bridging faults. The technique is validated by the topological design and SPICE simulation of a multiplier circuit.

The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential circuit may be able to memorize one or two logic states depending on the values of the defect parameters. I/sub DDQ/ testing may detect a large class of floating gate defects including some defective transistors located in logically untestable branches. Good agreement is observed between the theoretical and simulated results with experimental measurements performed on a typical scan path cell designed intentionally with floating gate defects.

When disconnecting the power supply line of a CMOS circuit in its quiescent state, the capacitances present in the circuit hold the logic valves in all their nodes. In non defective circuits, these capacitances discharge very slowly due to the extremely small I/sub DDQ/ discharge current. On the other hand, in I/sub DDQ/ defective circuits the discharge is faster than in the previous case because the current involved is many orders of magnitude greater. Some time after the discharge starts, the logic state of some nodes may change, and when this change propagates to a primary output, the defect is detected. Experimental work has been performed to prove these effects and to evaluate their fault detection capabilities.

Functionally equivalent nodes may cause some bridging faults to become undetectable by I/sub DDQ/ testing. An efficient method for the identification of classes of functionally equivalent nodes in combinational circuits, based on OBDD comparison, is presented. To illustrate the methodology, the I/sub DDQ/ undetectable logic bridging faults have been identified in a set of benchmark circuits.>

The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect.>

Two test strategies for external and internal shorts in FCMOS combinational circuits, based on current consumption monitoring, are proposed and analysed: (a) pseudorandom test with a small number of vectors, and (b) a new strategy called current testing vector generation based on stuck at Faults (CUTEGENS). Both test strategies have been experimented on a set of combinational benchmark circuits. The pseudorandom test strategy has been found efficient when testing external shorts but coverages for internal shorts are not as satisfactory. CUTEGENS provides test sets with a reduced number of vectors, which have a very high coverage for both external and internal shorts. In most of the experimented circuits, the coverage has been shown to be the highest obtainable with current consumption monitoring.>

An efficient method for the analysis and detection of functionally equivalent nodes in combinational circuits is presented. In this work these nodes are called f-redundant nodes. The proposed method consists of two phases: First, a reduced set of pseudorandom input vectors is used to reduce the number of classes of nodes that are candidates for f-redundancy. In the second phase, ordered binary decision diagrams are used to check the equivalences between the logic functions of the remaining f-redundant node candidates. The efficiency of the proposed algorithm has been evaluated on the ISCAS'85 benchmark circuits.>

Measurements on process-related defect nionitwing ,wcijers are presented in order to euuluute the i,csisluiict. ,ualu,e of b ridyzng deJects zn CMOS VLSI circu~ts. 'I'he inethodoloyy u sed is dlustrated and statzstics OIL the 1.esistance values are p resented. As a result, the vast niajoi-zty of the measured brzdges have a 1o.w 7.eszsta.nce. Only a small percentage of the brzdges has U i.eszstunce va1u.e above 500 R, while the exact percentage cui1 vuq strongly from batch to batch. Tlirs high resisturict. does not seem to be the result of the materzal of the defect itself, but rather the result o f the form and locatzon of the defect. These circumstances can result rn one or two poor contacts between. the defect and the destgn,ed stlucture of the IC, and thus in a hrgh reszsizue defect.