The Computing-In-Memory (CIM) paradigm offers a promising solution to the memory-wall bottleneck that limits conventional Von Neumann architectures. By performing data processing at the same physical location where the data are stored, CIM-based architectures minimize costly data movement and drastically improve energy efficiency. When implemented with Ferroelectric Field Effect Transistors (FeFETs), additional advantages from the non-volatility, fast switching, and low operating voltage of FeFETs are added. However, the widespread adoption of FeFETs is limited by their poor endurance, which is overcome by a Back End of the Line (BEoL) integration of FeFET-2, where a ferroelectric capacitor (FeCAP) is wired to the gate of a CMOS transistor providing high endurance compatible with low-power edge applications. These properties enable dense, low-power, and high-speed matrix operations essential for AI workloads. As a result, FeFET-2-based CIM accelerators offer a promising solution for energy-efficient, high-performance AI at the edge. The Ferro4EdgeAI project aims to develop an ultra low-power, scalable edge accelerator for AI, targeting a significant gain in energy efficiency with respect to state-of-the-art AI hardware accelerators. To attain this, our project focuses on innovation all along the value chain from materials, physic concepts, device architecture, integration technologies, and accelerators in a holistic design space exploration approach.

International audience

The semiconductor industry is pivotal to Europe's economy, especially within the industrial and automotive sectors. However, Europe faces a significant shortfall in chip design capabilities, marked by a severe skilled labor shortage and lagging contributions in the design value chain segment. This paper explores the role of European universities and academic initiatives in enhancing chip design education and research to address these deficits. We provide a comprehensive overview of current European chip design initiatives, analyze major challenges in recruitment, productivity, technology access, and design enablement, and identify strategic opportunities to strengthen chip design capabilities within academic institutions. Our analysis leads to a series of recommendations that highlight the need for coordinated efforts and strategic investments to overcome these challenges.

Large-scale convolutional neural networks (CNNs) often rely on dedicated digital hardware, constrained by latency, throughput, and energy efficiency. Photonic hardware offers a promising alternative, but its analog nature and optical complexity pose challenges for electronic design automation (EDA) and design space exploration (DSE), limiting large-scale analysis. This work presents a novel parameterization methodology that quantifies the impact of noise, quantization, and kernel choice on a photonic convolution accelerator (CA), leveraging high-speed simulation tool. Using the MNIST dataset with $\mathbf{1 0}$ kernels, our results reveal up to a $3.5 \times$ difference in the root mean squared error (RMSE) between Blur and Laplacian kernels, demonstrating the critical role of kernel choice. The proposed simulation approach is also over $100 \times$ faster than conventional methods, making the analysis feasible, whereas performing it with traditional techniques would be impractical, if not impossible.

Ferroelectric memory devices have emerged as a promising class of non-volatile memory technologies, offering a unique combination of high-speed operation, low power consumption, and good endurance compared to conventional flash memory. These devices leverage the bistable polarization states of ferroelectric materials to store data, enabling nonvolatile retention while maintaining fast read/write capabilities. The discovery of hafnium-based ferroelectric materials that are fully CMOS compatible and exhibit robust ferroelectricity at nanoscale dimensions has further enhanced their integration and scalability potential. For IoT devices, which require non-volatile state retention under constrained power budgets and frequent interruptions, we propose a novel FeAND memory cell designed to serve as a non-volatile backup for volatile memory. Unlike conventional ferroelectric memories that rely on current sensing, our design directly outputs a voltage signal, eliminating the need for sensing circuits. The cell exhibits a logical AND-like behavior, enabled by an innovative read scheme based on a CMOS inverter. The cell can function as both a non-volatile memory element and a logic gate where one input is permanently stored as a polarization state. This dual functionality enables novel Computing-in-Memory architectures by embedding logic operations directly within the memory array. We validate our design using Cadence Spectre simulations with the GlobalFoundries 28SLP technology.

The promising features introduced by the integration of ferroelectric devices into conventional integrated circuit fabrication processes have spurred extensive research into device reliability, non-volatile memory circuits and system-level applicability. Their low-power operation makes them particularly suitable for Internet of Things applications, and their intrinsic memory properties position them as strong candidates for nonvolatile memory technologies and In-memory Computing. For such data-intensive applications, the need to ensure secure data storage, processing and transmission has motivated the adaptation of classic hardware security strategies to this emerging inmemory computing paradigm, demonstrating high effectiveness with ferroelectric designs. However, a variability analysis from a design perspective remains unexplored towards either implementing security primitives based on identity, e.g. Physical Unclonable Functions, or based on stochasticity, e.g. True Random Number Generators.In this work, we focus on the variations expected in a commercial 28 nm process and its compatibility with memory cell design, in view of the implementation of a Physical Unclonable Function in a ferroelectric memory array. In particular we show that while obtaining a sufficient output variability, which can be used for fingerprinting the device, a fair current ratio is maintained, allowing memory array implementations.

Non-volatile in-memory computing (iMC) has emerged as an energy-efficient paradigm well suited to AI workloads. Its implementation using 1T1C FeMFETs (Ferroelectric Memory Field Effect Transistors), a best-in-class emerging nonvolatile memory technology that integrates BEOL ferroelectric devices with FEOL transistors, is of particular interest. This interest stems from their potential to enable large-scale multiplyaccumulate (MAC) operations in both digital and analog domains. However, realizing tangible performance benefits requires comprehensive cross-layer exploration of both design and technology parameters, extending up to accelerator level. In this work, we propose a bitcell-level multi-objective optimization methodology to identify and extract optimal sizing solutions that provide tractable trade-offs between key performance indicators (KPI). We further demonstrate how this approach facilitates cross-stack exploration of accelerator architectures. Results are presented as Pareto fronts spanning $2-4 \mathrm{KPIs}$: a $2-\mathrm{KPI}$ problem illustrates the methodology, while a $\mathbf{4}$-KPI problem represents a realistic design scenario. Comparison is made between $\mathbf{1 3 0} \mathbf{n m}$ and 28 nm technologies demonstrating a decrease in the average of write energy and area up to 24 X and 30 X respectively.

As AI continues to grow in importance, in order to reduce its carbon footprint and utilization of computer resources, numerous alternatives are under investigation to improve its hardware building blocks. In particular, in convolutional neural networks (CNNs), the convolution function represents the most important operation and one of the best targets for optimization. A new approach to convolution had recently emerged using optics, phase-change materials (PCMs) and stochastic computing, but is thus far limited to unsigned operands. In this paper, we propose an extension in which the convolutional kernels are signed, using mixed-polarity bitstreams. We present a proof of validity for our method, while also showing that, in simulation and under similar operating conditions, our approach is less affected by noise than the common approach in the literature.

Multiple research vectors represent possible paths to improved energy and performance metrics at the application-level. There are active efforts with respect to emerging logic devices, new memory technologies, novel interconnects, and heterogeneous integration architectures. Of great interest is quantifying the potential impact of a given solution to prioritize research vectors accordingly. In this paper, we discuss two efforts - one focused on emerging memory technology, and another focused on heterogeneous integration technology - that speak to best practices for, and needed contributions from the design automation (DA) community to explore this vast design space. Furthermore, we highlight new research efforts that aim to develop the novel compiler abstractions and frameworks that are ultimately needed to derive maximum value from new memory and/or heterogeneous and monolithic integration architecture, and that can also play an important role with respect to design space exploration efforts.

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube$(N^{2}C^{2})$, which is specifically designed to execute complex machine learning tasks in a 3D technology, in order to provide the high computing power and ultra-high efficiency needed for future edgeAI applications. We showcase its effectiveness by targeting the challenging class of Transformer ANNs, tailored for Automatic Speech Recognition and Machine Translation, the two fundamental components of speech-to-speech translation. To gain the full benefit of the accelerator design, we develop disruptive vertical transistor technologies and execute design-technology-co-optimization (DTCO) loops from single device, to cell and compute cube level. Further, a hardware-software-co-optimization is executed, e.g. by compressing the executed speech recognition and translation models for energy efficient executing without substantial loss in precision.

State-of-the-Art (SotA) hardware implementations of Deep Neural Networks (DNNs) incur high latencies and costs. Binary Neural Networks (BNNs) are potential alternative solutions to realize faster implementations without losing accuracy. In this paper, we first present a new data mapping, called TacitMap, suited for BNNs implemented based on a Computation-In-Memory (CIM) architecture. TacitMap maximizes the use of available parallelism, while CIM architecture eliminates the data movement overhead. We then propose a hardware accelerator based on optical phase change memory (oPCM) called EinsteinBarrier. Ein-steinBarrier incorporates TacitMap and adds an extra dimension for parallelism through wavelength division multiplexing, leading to extra latency reduction. The simulation results show that, compared to the SotA CIM baseline, TacitMap and EinsteinBarrier significantly improve execution time by up to$\sim 154\times$and$\sim 3113\times$, respectively, while also maintaining the energy consumption within 60% of that in the CIM baseline.

The vertical nanowire field effect transistor (VN-WFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, such a technology enables designs with improved energy-efficiency as well as reduced footprint and thus interconnect capacitance. In this work, and based on the compact model of a real VNWFET device, we present the design flow for the generation of a standard cell library starting from the circuit and physical design of logic cells to logic synthesis based on the VNWFET technology. The results on the synthesized benchmark cells, as compared against 45nm and 65nm CMOS libraries, demonstrate a significant decrease in the average dynamic power consumption and delay values up to 71X and 34X respectively, with anaveragearea gain of up to 5X. However, an increase in leakage power consumption (up to 2X on average) was also observed.

Static Random Access Memories (SRAM) are fast and efficient circuits used as the main working memory of processing units. However, associating these volatile memories with external non-volatile memories leads to energy consumption and area penalties, while leading to security issues. Ferroelectric-based NVSRAMs are one of the most promising ways of combining the high efficiency of SRAMs with non-volatile operations to tackle these challenges. In this work, several design parameters of the bitcell are optimized to ensure error-less data transfer between 6T SRAM internal nodes and 4 ferroelectric capacitors (4C). The presented 6T4C bitcell presents STORE and RECALL energies of 161fJ/bit and 27fJ/bit, respectively, and STORE and RECALL times of 480ns and 245ns, respectively. A high reliability is achieved from −40°C to +85°C for SS, TT and FF fabrication corners. The integration of the four FeCAPs in the bitcell leads to a 46% area overhead, a 94% WRITE time degradation, and a 32% WRITE energy increase. However, an increase of less than 0.5% in both READ time and energy has been observed. A previously developed Fast-Erase system has also been integrated for countering cold-boot attacks. Combining design optimizations and Fast-Erase technique ensures cold-boot attack immunity of the memory and enables error-less RECALL with WRITE operations between STORE and RECALL, leading to new use-cases of NVSRAM circuits.

In this paper we propose a novel approach to multiply-accumulate (MAC) operations in photonics. This approach is based on stochastic computing and on the dynamic behavior of phase-change materials (PCMs), leading to the unique characteristic of automatically storing the result in non-volatile memory. We demonstrate that, even with perfect look-up tables, the standard approach to PCM scalar multiplication is highly susceptible to perturbations as small as 0.1% of the input power, causing repetitive peaks of 600% relative error. In the same operating conditions, the proposed method achieves an average of 7× improvement in precision.

There is great interest in “end-to-end” analysis that captures how innovation at the materials, device, and/or archi-tectural levels will impact figures of merit at the application-level. However, there are numerous combinations of devices and architectures to study, and we must establish systematic ways to accurately explore and cull a vast design space. We aim to capture how innovations at the materials/device-level may ultimately impact figures of merit associated with both existing and emerging technologies that may be employed for either logic and/or memory. We will highlight how collaborations with researchers at these levels of the design hierarchy - as well as efforts to help construct well-calibrated device models - can in-turn support architectural design space explorations that will help to identify the most promising ways to use new technologies to support application-level workloads of interest. For given compute workloads, we can then quantitatively assess the potential benefits of technology-driven architectures to identify the most promising paths forward. Because of the large number of potentially interesting device-architecture combinations, it is of the utmost importance to develop well-calibrated analytical modeling tools to more rapidly assess the potential value of a given (likely heterogeneous) solution. We highlight recent efforts and needs in this space.

This paper investigates the potential of a compute-in-memory core based on optical Phase Change Materials (oPCMs) to speed up and reduce the energy consumption of the Matrix-Matrix-Multiplication operation. The paper also proposes a new data mapping for Binary Neural Networks (BNNs) tailored for our oPCM core. The preliminary results show a significant latency improvement irrespective of the evaluated network structure and size. The improvement varies from network to network and goes up to ~1053x.

Nowadays, Deep Neural Networks (DNNs) are one of the most computationally-intensive algorithms because of the (i) huge amount of data to be transferred from/to the memory, and (ii) the huge amount of matrix multiplications to compute. These issues motivate the design of custom DNN hardware accelerators. These accelerators are widely used for low-latency safety-critical applications such as object detection in autonomous cars. Safety-critical applications have to be resilient with respect to hardware faults and Deep Learning (DL) accelerators are subjected to hardware faults that can cause functional failures, potentially leading to catastrophic consequences. Although DNNs possess a certain level of intrinsic resilience, it varies depending on the hardware on which they are run. The intent of the paper is to assess the resilience of a systolic-array-based DNN accelerator in the presence of hardware faults, in order to identify the architectural parameters that may mainly impact the DNN resilience.

This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases.

On-device learning is essential to achieve intelligence at the edge, where it is desirable to learn from few samples or even just a single sample. Memory-augmented neural networks (MANNs), which augment neural networks with an attentional memory, can draw on already learnt knowledge patterns and adapt to new but similar tasks. Implementing MANNs on conventional architectures can require a significant amount of costly data transfer, thereby limiting the practical use of MANNs at the edge. In this paper, we introduce algorithm/hardware co-design solutions which exploit compact designs of content addressable memories (CAMs) based on emerging non-volatile memories (e.g., FeFETs) to implement energy-efficient MANN accelerators. The design space of MANN accelerators is systematically analyzed by considering different circuit, architecture, and algorithm options. We further discuss how hyper-dimensional representations of data can be combined with MANNs to overcome the negative effect of device/circuit variabilities on learning quality, thus achieving not only energy-efficient but also accuracy-competitive on-device learning at the edge. We also investigate modeling of device-to-device (D2D) variation in FeFETs using the write-with-verify approach and detail its impact on the energy, delay, and accuracy of the MANN application.

Data-centric applications such as Artificial Intelligence and IoT are putting stringent performance and energy efficiency constraints on hardware implementations of computing architectures. Computing in Memory paradigm appears as a viable approach to to address such constraints and ferroelectric FETs (FeFETs) push this paradigm at a finer grain by enabling the design of true non-volatile logic gates, by implementing tight combination of memory and logic called Logic-in-Memory (LiM). From the basic non-volatile logic gate design up to the application-level evaluation, several challenges have to be addressed.In this paper, we present a methodology to design complex operations such as cryptographic operations using FeFET, integrate them into a complete computing architecture and evaluate its benefits. Current challenges related to logic synthesis and tools for synthesis of these LiM structures will also be discussed.

The computational workload involved in Convolutional Neural Networks (CNNs) is typically out of reach for low-power embedded devices. The scientific literature provides a large number of approximation techniques to address this problem. Among them, the Weight-Sharing (WS) technique gives promising results, but it requires carefully determining the shared values for each layer of a given CNN. As the number of possible solutions grows exponentially with the number of layers, the WS Design Space Exploration (DSE) time can easily explode for state-of-the-art CNNs. In this paper, we propose a new heuristic approach to drastically reduce the exploration time without sacrificing the quality of the output. The results carried out on recent CNNs (GoogleNet [1], ResNet50V2 [2], MobileNetV2 [3], InceptionV3 [4], and EfficientNet [5]), trained with the ImageNet [6] dataset, show over 5× memory compression at an acceptable accuracy loss (complying with the MLPerf [7] quality target) without any retraining step and in less than 10 hours. Our code is publicly available on GitHub [8].

In the literature, there are few studies describing how to implement Boolean logic functions as a memristor-based crossbar architecture and some solutions have been actually proposed targeting back-end synthesis. However, there is a lack of methodologies and tools for the synthesis automation. The main goal of this paper is to perform a Design Space Exploration (DSE) in order to analyze and compare the impact of the most used optimization algorithms on a memristor-based crossbar architecture. The results carried out on 102 circuits lead us to identify the best optimization approach, in terms of area/energy/delay. The presented results can also be considered as a reference (benchmarking) for comparing future work.

Today we observe amazing performance achieved by Machine Learning (ML); for specific tasks it even surpasses human capabilities. Unfortunately, nothing comes for free: the hidden cost behind ML performance stems from its high complexity in terms of operations to be computed and the involved amount of data. For this reasons, custom Artificial Intelligence hardware accelerators based on alternative computing paradigms are attracting large interest. Such dedicated devices support the energy-hungry data movement, speed of computation, and memory resources that MLs require to realize their full potential. However, when ML is deployed on safety-/mission-critical applications, dependability becomes a concern. This paper presents the state of the art of custom Artificial Intelligence hardware architectures for ML, here Spiking and Convolutional Neural Networks, and shows the best practices to evaluate their dependability.

Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator.

In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior is turned into a design implementation in terms of logic gates. Historically, logic synthesis was tightly related to the physical implementation of the logic gates. Nowadays, pushed by the forecasted end of Moore's law, several emerging technologies (e.g., nanodevices, optical computing, quantum computing) are candidates to either replace or co-exist with the de facto standard CMOS technology. The main consequence of the rising of those emerging technologies is that the logic synthesis has to face new issues and, at the same time, exploits new opportunities. The goal of this paper is thus to present three emerging technologies (Vertical Nanowire Field Effect Transistors, Ferroelectric Transistors, and Memristors), how to use them to implement logic gates, and the main challenges and issues for the logic synthesis.

The design and implementation of Convolutional Neural Networks (CNNs) for deep learning (DL) is currently receiving a lot of attention from both industrials and academics. However, the computational workload involved with CNNs is often out of reach for low power embedded devices and is still very costly when running on datacenters. By relaxing the need for fully precise operations, approximate computing substantially improves performance and energy efficiency. Deep learning is very relevant in this context, since playing with the accuracy to reach adequate computations will significantly enhance performance, while keeping quality of results in a user-constrained range. AdequateDL is a project aiming to explore how approximations can improve performance and energy efficiency of hardware accelerators in DL applications. This paper presents the main concepts and techniques related to approximation of CNNs and preliminary results obtained in the AdequateDL framework.

The paper addresses some of the opportunities and challenges related to test and reliability of three major emerging computing paradigms; i.e., Quantum Computing, Computing engines based on Deep Neural Networks for AI, and Approximate Computing (AxC). We present a quantum accelerator showing that it can be done even without the presence of very good qubits. Then, we present Dependability for Artificial Intelligence (AI) oriented Hardware. Indeed, AI applications shown relevant resilience properties to faults, meaning that the testing strongly depends on the application behavior rather than on the hardware structure. We will cover AI hardware design issues due to manufacturing defects, aging faults, and soft errors. Finally, We present the use of AxC to reduce the cost of hardening a digital circuit without impacting its reliability. In other words how to go beyond usual modular redundancy scheme.

This special session paper discusses recent advances on photonic physical unclonable functions (PUFs), providing a broader overview of and motivation for photonic PUFs. We discuss their potential advantages, such as a higher entropy, larger complexity, and possibly better resilience against machine learning attacks. We also deal with some recent implementations based on linear and non-linear optics, alongside with their main advantages and limitations.

In the last decade, Approximate Computing (AxC) has been studied as a possible alternative computing paradigm. It has been used to reduce the overhead cost of conventional fault tolerant schemes, such as the Triple Modular Redundancy (TMR). One of the most recent propositions is the concept of Quadruple Approximate Modular Redundancy (QAMR). QAMR reduces the overhead cost w.r.t. conventional TMR structures, while guaranteeing the same fault-tolerance capability. In this paper, we propose a new approximation technique to realize the QAMR and we perform a Design Space Exploration (DSE) to find QAMR Pareto-optimal implementations. Moreover, we provide the design of a new majority voter for the proposed architecture. Experimental results show that it is possible to find QAMR variants achieving area and/or delay gains compared to the TMR counterpart, for 85.4% and 97% of the examined circuits for FPGA and ASIC technologies respectively.

This paper deals with the frequency design of lossless passive electronic filters under magnitude constraints. With the huge increase in design complexity for mobile applications, new systematic and efficient methods are required. This paper focuses on the direct synthesis approach, an historical design approach that has not been recently updated. It consists in directly synthesizing the LC values of a pre-specified circuit until the spectral mask is satisfied. While beneficial in practice, this approach typically leads to an important computational time and requires an initial guess to reduce it. Based on recent developments of the System and Control community, that led to efficient methods for system design, the direct synthesis approach is revisited. To achieve this, the port-Hamiltonian Differential Algebraic Equation (pHDAE) representation, that particularly fits the design problem, is introduced. A synthesis method is then developed, leading to solve an optimization problem of moderate complexity. For particular cases, this complexity happens to be remarkably low. Based on this observation, a second method reveals how to obtain such complexity for the more general case, using an original combination between the pHDAE and the LFT representations. Finally, a numerical example shows the validity and illustrates the benefits of this work.

We consider existing and emerging neural workloads, and what hardware accelerators might be best suited for said workloads. We begin with a discussion of analog crossbar arrays, which are known to be well-suited for matrix-vector multiplication operations that are commonplace in existing neural network models such as convolutional neural networks (CNNs). We highlight candidate crosspoint devices, what device and materials challenges must be overcome for a given device to be employed in a crossbar array for a computationally interesting neural workload, and how circuit and algorithmic optimizations may be employed to mitigate undesirable characteristics from devices/materials. We then discuss two emerging neural workloads. We first consider machine learning models for one- and few-shot learning tasks (i.e., where a network can be trained with just one or a few, representative examples of a given class). Notably crossbar-based architectures can be used to accelerate said models. Hardware solutions based on content addressable memory arrays will also be discussed. We then consider machine learning models for recommendation systems. Recommendation models, an emerging class of machine learning models, employ distinct neural network architectures that operate of continuous and categorical input features which make hardware acceleration challenging. We will discuss the open research challenges and opportunities within this space.

Deep neural networks demonstrate impressive levels of performance, particularly in computer vision and speech recognition. However, the computational workload and associated storage inhibit their potential in resource-limited embedded systems. The approximate computing paradigm has been widely explored in the literature. It improves performance and energy-efficiency by relaxing the need for fully accurate operations. There are a large number of implementation options with very different approximation strategies (such as pruning, quantization, low-rank factorization, knowledge distillation, etc.). To the best of our knowledge, no automated approach exists to explore, select and generate the best approximate versions of a given convolutional neural network (CNN) according to the design objectives. The goal of this work in progress is to demonstrate that the design space exploration phase can enable significant network compression without noticeable accuracy loss. We demonstrate this via an example based on weight sharing and show that our method can obtain a 4x compression rate in an int-16 version of LeNet-5 (5-layer 1,720-kbit CNNs) without re-training and without any accuracy loss.

The following topics are dealt with: embedded systems; logic design; CMOS integrated circuits; neural nets; integrated circuit design; field programmable gate arrays; low-power electronics; formal verification; multiprocessing systems; Internet of Things.

Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices., which are well suited to pursue scaling beyond lateral scaling limitations around 7nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model., which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50nm. We used this model to simulate the projected performance of inverter logic gates based on passive load., active load and complementary topologies and carry out an performance exploration for the number of nanowires in transistors. In terms of compactness., through a dedicated full 3D layout design., we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7nm FinFET-based inverters.

Predictive models based on Pareto fronts are key tools to understand and leverage tradeoffs in electronic circuit and system design. However, their generation conventionally requires the extensive use of numerical simulation and multi-objective optimization methods, resulting in significant computational cost. This cost increases exponentially with the number of parameters, and visualization also becomes an issue as the number of performance metrics increases. In this paper, we present a method to extract predictive models efficiently for electronic subsystems based on Pareto fronts. We use a very fast design and migration software called ID-Xplore™ to generate the performance space of sub-blocks in order to generate Pareto fronts for any block, thereby circumventing the traditional use of numerical optimization and thus accelerating the generation of Pareto-fronts for n-performance. We also combine the Pareto fronts in order to obtain one single Pareto front that represents all specifications, and use the Hyper-Space Diagonal Counting (HSDC) methodology to visualize n-performance Pareto fronts and combine the overall approach to help the designer in the final choice of optimal design points in the design of a state of the art OTA.

No abstract available.

On-chip integrated lasers are key devices to deliver the high bandwidth expected from nanophotonic interconnects. However, lasers are highly sensitive to temperature variation, which influences the lasing efficiency and the wavelengths of emitted optical signals, both of which are key factors in interconnect power efficiency. It is, thus, necessary to develop techniques for efficient thermal-aware control of lasers. In this brief, we propose the grouping of lasers for efficient power control of their temperature. Laser grouping is carried out taking into account the layout symmetries, and a design method allows the definition of control laws.

Spintronics brings new features that make it a viable candidate technology to implement non-conventional processing for new computing paradigms in an efficient way. The first milestone of the spintronics roadmap was the fabrication of hybrid systems where the data processing relies mostly on charge-based electronics devices (CMOS), while the memory hierarchy is partially or totally replaced by MRAM. In the next step, spintronics can also be used for data processing, still in conjunction with CMOS. Nevertheless, replacing all the processing by pure spintronic circuits, without any charge current, remains the ultimate objective of spintronics. All spin logic (ASL) paves the way towards that goal, even if some CMOS control circuits are still necessary. However, as ASL does not rely on the same computing principle as CMOS, it is necessary to address some specific issues. Pure spin current propagates in every direction, including backwards in the presence of multiple inputs; and is divided when crossings are encountered. It combines mainly linearly, while logic operations require non-linear binary decisions. Interconnect between logic gates requires directionality from inputs to outputs, and fanout with negligible signal attenuation. In this context, we develop new strategies for ASL modeling and logic design. We propose an architecture and a design strategy based on a high-density array to address the specific issues of directionality, attenuation and linearity. Moreover, the feasibility is supported through the modeling and the simulation of its basic block. This implies modularity to simulate complex circuits, even when they are ahead of today's experimental demonstrations.

In this paper, we consider devices, circuits, and systems comprised of transistors with integrated ferroelectrics. Said structures are actively being considered by various semiconductor manufacturers as they can address a large and unique design space. Transistors with integrated ferroelectrics could (i) enable a better switch (i.e., offer steeper subthreshold swings), (ii) are CMOS compatible, (iii) have multiple operating modes (i.e., I-V characteristics can also enable compact, 1-transistor, non-volatile storage elements, as well as analog synaptic behavior), and (iv) have been experimentally demonstrated (i.e., with respect to all of the aforementioned operating modes). These device-level characteristics offer unique opportunities at the circuit, architectural, and system-level, and are considered here from device, circuit/architecture, and foundry-level perspectives.

Edge computing requires highly energy efficient microprocessor units with embedded non-volatile memories to process data at IoT sensor nodes. Ferroelectric non-volatile memory devices are fast, low power and high endurance, and could greatly enhance energy-efficiency and allow flexibility for finer grain logic and memory. This paper will describe the basics of ferroelectric devices for both hysteretic (non-volatile memory) and negative capacitance (steep slope switch) devices, and then project how these can be used in low-power logic cell architectures and fine-grain logic-in-memory (LiM) circuits.

Optical Network-on-Chip (ONoC) is a promising communication medium for large-scale multiprocessor systems-on-chips. Indeed, ONoC can outperform classical electrical NoCs in terms of energy efficiency and bandwidth density, in particular, because this medium can support multiple transactions at the same time on different wavelengths by using Wavelength Division Multiplexing (WDM). However, multiple signals sharing simultaneously the same part of a waveguide can lead to inter-channel crosstalk noise. This problem impacts the signal-to-noise ratio of the optical signals, which leads to an increase in the Bit Error Rate (BER) at the receiver side. If a specific BER is targeted, an increase of laser power should be necessary to satisfy the SNR. In this context, an important issue is to evaluate the laser power needed to satisfy the various desired communication bandwidths based on the BER performance requirements. In this article, we propose an off-line approach that concurrently optimizes the laser power scaling and execution time of a global application. A set of different levels of power is introduced for each laser, to ensure that optical signals can be emitted with just-enough power to ensure targeted BER. As a result, most promising solutions are highlighted for mapping a defined application onto a 16-core ring-based WDM ONoC.

Nanophotonic is an emerging technology considered as one of the key solutions for future generation on-chip interconnects. Indeed, this technology provides high bandwidth for data transfers and can be a very interesting alternative to bypass the bottleneck induced by classical NoC. However, their implementation in fully integrated 3D circuits remains uncertain due to the high power consumption of on-chip lasers. However, if a specific bit error rate is targeted, digital processing can be added in the electrical domain to reduce the laser power and keep the same communication reliability. This paper addresses this problem and proposesto transmit encoded data on the optical interconnect, which allows for a reduction of the laser power consumption, thus increasing nanophotonics interconnects energy efficiency. The results presented in this paper show that using simple Hamming coder and decoder permits to reduce the laser power by nearly 50% without loss in communication data rate and with a negligible hardware overhead.

Optical Network-on-Chip (ONoC) is a promising communication medium for large-scale Multiprocessor System on Chip (MPSoC). ONoC outperforms classical electrical NoC in terms of throughput and latency. The medium can support multiple transactions at the same time on different wavelengths by using Wavelength Division Multiplexing (WDM). Moreover multiple wavelengths can be used as high-bandwidth channel to reduce transmission time. However, multiple signals sharing simultaneously a waveguide can lead to inter-channel crosstalk noise. This problem impacts the Signal to Noise Ratio (SNR) of the optical signal, which leads to an increase in the Bit Error Rate (BER) at the receiver side. In this paper we first formulate the crosstalk noise and execution time models and then propose a Wavelength Allocation (WA) method in a ring-based WDM ONoC allowing to search for performance and energy trade-offs, based on the application constraints. As result, most promising WA solutions are highlighted for a defined application mapping onto 16-core WDM ONoC.

Single-layer optical crossbar interconnections based on Wavelength Division Multiplexing stand among other nanophotonic interconnects because of their low latency and low power. However, such architectures suffer from a poor scalability due to losses induced by long propagation distances on waveguides and waveguide crossings. Multi-layer deposited silicon technology allows the stacking of optical layers that are connected by means of Optical Vertical Couplers. This allows significant reduction in the optical losses, which contributes to improve the interconnect scalability but also leads to new challenges related to network designs and layouts. In this article, we investigate the design of optical crossbars using multi-layer silicon deposited technology. We propose implementations for Ring-, Matrix-, λ-router-, and Snake-based topologies. Layouts avoiding waveguide crossings are compared to those minimizing the waveguide length according to worst-case and average losses. The laser output power is estimated from the losses, which allows us to evaluate the energy efficiency improvement induced by multi-layer technology over traditional planar implementations (33% on average). Finally, networks comparison has been carried out and the results show that the ring topology leads to a 43% reduction in the laser output power.

On behalf of the Organizing and Program Committees, it is our great pleasure to welcome you to the 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC'16, in Tallinn/Estonia. The conference is held in the Radisson Park Inn Meriton Conference & Spa Hotel, just a couple of footsteps away from the beautiful Old Town of the city. VLSI-SoC 2016 is the 24th in a series of international conferences sponsored by the IFIP TC 10 Working Group 10.5, IEEE CEDA and IEEE CASS, which explores the state-of-the-art in the areas that surround Ultra Large Scale Integration (ULSI) and System-on-Chip (SoC) design and test as well as mixed-technology devices.

The many cores design research community have shown high interest in optical crossbars on chip for more than a decade. Key properties of optical crossbars, namely a) contention-free data routing b) low-latency communication and c) potential for high bandwidth through the use of WDM, motivate several implementations. These implementations demonstrate very different scalability and power efficiency ability depending on three key design factors: a) the network topology, b) the considered layout and c) the insertion losses induced by the fabrication process. The emerging design technique relying on multi-layer deposited silicon allows reducing optical losses, which may lead to significant reduction of the power consumption. In this paper, multi-layer deposited silicon based crossbars are proposed and compared. The results indicate that the proposed ring-based network exhibits, on average, 22% and 51.4% improvement for worst-case and average losses respectively compared to the most power-efficient related crossbars.

Optical interconnects are considered to be one of the key solutions for future generation on-chip interconnects. However, energy efficiency is mainly limited by the losses incurred by the optical signals, which considerably reduces the optical power received by the photodetectors. In this paper we propose a differential transmission of the modulated signals, which contributes to improve the transmission of the optical signal power on the receiver side. With this approach, it is possible to reduce the input laser power and increase the energy efficiency of the optical communication. The approach is generic and can be applied to SWSR-, MWSR-, SWMR- and MWMR-like architectures.

The next generation of MPSoC points to the integration of thousands of IP cores, requiring high performance interconnect for high throughput communications. Optical on-chip interconnect enables significantly increased bandwidth and decreased latency in MPSoC. However, the interface between electrical and photonic devices implies strong layout constraints that may impact the system performance and scalability. In this paper, we propose a novel optical interconnect named Chameleon. The interface simplifies the layout and allows the bandwidth between IP cores to be adapted according to the communication requirements. Compared to related networks, Chameleon demonstrates improved scalability and flexibility at the cost of minor increase in power consumption.

This paper presents design rule checking (DRC) methods to address challenges caused by non-Manhattan geometries that are widely present in photonic integrated circuit (PIC) physical designs. Verifying such layouts with traditional DRC tools results in a huge number of false errors that are impossible to debug; and some physical rules are simply uncheckable. We demonstrate the use of an extended DRC technique on photonic designs to tackle these issues. The results show that the technique is well-suited for silicon photonics DRC, enabling false errors to be filtered in a controllable manner, leading to easier debugging with layout annotation; multi-dimensional rule checking to be performed; and mathematical expressions to be used for more accurate descriptions of physical rules.

The Optical LUT (OLUT) has been proposed as a parallel and energy-efficient logic architecture for building prospective on-chip optical FPGAs in order to replace traditional power-hungry electronic computing circuits. In this paper, we present a new OLUT implementation that computes a pair of complementary Boolean logic functions through wavelength multiplexing, allowing the computational capacity to be doubled for a reasonable optical power and area overhead depending on the OLUT size. Worst-case evaluation of the optical laser power needed to perform reliable logic operations demonstrates the potential of the proposed OLUT for energy- and hardware-efficient photonic reconfigurable computing.

SUMMARY The many‐core design research community has shown high interest in optical crossbar on chip for more than a decade. Key properties of optical crossbars, namely (1) contention‐free data routing, (2) low latency communication, and (3) potential for high bandwidth through the use of wavelength division multiplexing, motivate several implementations of this type of interconnect. These implementations demonstrate very different scalability and power efficiency abilities depending on three key design factors: (1) network topology, (2) considered layout, and (3) insertion losses induced by the fabrication process. In this paper, the worst‐case optical losses of crossbar implementations are compared according to the factors mentioned earlier. The comparison results have the potential to help many‐core system designer to select the most appropriate crossbar implementation according to, for instance, the number of IP cores and the die size. Copyright © 2014 John Wiley & Sons, Ltd.

The computation capacity of conventional FPGAs is directly proportional to the size and expressive power of Look Up Table (LUT) resources. Individual LUT performance is limited by transistor switching time and power dissipation, defined by the CMOS fabrication process. In this paper we propose OLUT, an optical core implementation of LUT, which has the potential for low latency and low power computation. In addition, the use of Wavelength Division Multiplexing (WDM) allows parallel computation, which can further increase computation capacity. Preliminary experimental results demonstrate the potential for optically assisted on-chip computation.

Trends in SoC design are leading to 3D integration of thousands of high-performance computing resources and high-throughput interconnects, opening up new research directions for hybrid electronic/photonic architectures. In this paper, we introduce how state of the art silicon-photonic devices can realize elementary operations that are traditionally performed by electronic devices, e.g. circuit switching and Boolean function computation. We then highlight how these devices need to be assembled in order to realize more complex functions, taking into account the constraints specific to silicon-photonic technology. In the last part, we summarize the main research directions for the near future.

As a leading standard in wireless sensor networks, IEEE 802.15.4 based networks are well-adapted to various applications such as environment monitoring, building automation and medical/health care, in which sensor nodes are always densely deployed and with the intense channel competition. However, the use of 250Kbps low-rate based network that defined in the standard can be inefficiency for these applications. Therefore, in this paper with nRF24 transceiver that supports high data rate over the air transmission and reception, we analyse the packet loss and lifetime estimation of a high data rate network via SystemC simulations by using unslotted algorithm in 1Mbps and 2Mbps scenarios. The impact of macMinBE / macMaxBE (BE), macMaxCSMABackoffs(Backoff) and macMaxFrameRetries (Retries) are performed under different traffic loads and at 1Mbps and 2Mbps high rate along with 250Kbps low rate. Experimental results show that the use of greater BE under different traffic loads of three data rates,and smaller Backoff at high traffic loads under 250Kbps and 1Mbps are able to achieve better lifetime and less packet loss.For Retries, the use of a greater value under low traffic loads of 1Mbps and 2Mbps can provide a good trade-off between lifetime performance and packet loss. On the other hand, we also deepen the analysis to include the nRF24 transceiver's embedded communication protocol engine Enhanced ShockBurst (ESB) for comparison. Furthermore, we also provide suggestions on the trade-off between packet loss and lifetime after each scenario analysis.

FPGA performance is limited by transistor switching time and power dissipation defined by the CMOS technology. Similarly to the case of interconnects, silicon photonics can also be leveraged to replace traditional, slow and power consuming, electrical computing circuits. In this paper we propose an all Optical LUT, an optical core implementation of LUT, which has the potential for low latency and relatively low power computation. The OLUT unique feature is its compliant input and output optical interfaces, which allows assembly to realize complex functions. The use of Wavelength Division Multiplexing (WDM) allows both parallel communication and computation, which can further increase the system performance. Preliminary results illustrate how the proposed OLUT can be assembled, giving the trends to the design of an all optical FPGA.

We present in this paper a circuit design approach to achieve compact logic circuits with ambipolar double-gate devices, using the in-field controllability of such devices. The approach is demonstrated for complementary static logic design style. We apply this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology and show that, with respect to conventional CMOS-like static logic structures and for comparable power consumption, time delay and integration density can both be improved by a factor of 1.5x and 2x, respectively. Compared with a predictive model for 16nm CMOS technology, the gates built according to the design approach described in this work and based on DG-CNTFET offer a gain of 30% concerning Power-Delay-Product (PDP).

In nanoscale integrated circuit technologies, process parameter fluctuations gain increasingly in importance. Efficient methods are thus required during the design phase to evaluate the resulting variability. In this letter, we propose a new method to estimate the variation bounds of analog circuit performance. This method combines design of experiment techniques with the Cornish-Fisher expansion: process parameter variations are first mapped to circuit performance metrics by a quadratic model, and then an analytical approximation of the performance distribution's quantiles enables the enclosure of the performance variations. The proposed method demonstrates a better accuracy/efficiency ratio than Monte-Carlo-based methods.

Thanks to recent technology advances, the exploration of the vertical dimension has been shown to be more than a dream for designers. Among those technologies, the vertical transistor has not been exploited yet. This paper describes a novel implementation of logic gates fully benefiting of nanowire-based vertical transistors embedded within the metal lines. The logic design in this technology is explored and its performance is evaluated. A comparison made on an equivalent technology node shows that our cells reduce area and delay by a factor of 31x and 2x respectively. Large reconfigurable logic circuits have been benchmarked showing an improvement of area and delay by 46% and 48% on average.

State-of-the-art System-on-Chip (SoC) consists of hundreds of processing elements, while trends in design of the next generation of SoC point to integration of thousand of processing elements, requiring high performance interconnect for high throughput communications. Optical on-chip interconnects are currently considered as one of the most promising paradigms for the design of such next generation Multi-Processors System on Chip (MPSoC). They enable significantly increased bandwidth, increased immunity to electromagnetic noise, decreased latency, and decreased power. Therefore, defining new architectures taking advantage of optical interconnects represents today a key issue for MPSoC designers. Moreover, new design methodologies, considering the design constraints specific to these architectures are mandatory. In this paper, we present a contention-free new architecture based on optical network on chip, called Optical Ring Network-on-Chip (ORNoC). We also show that our network scales well with both large 2D and 3D architectures. For the efficient design, we propose automatic wavelength-/waveguide assignment and demonstrate that the proposed architecture is capable of connecting 1296 nodes with only 102 waveguides and 64 wavelengths per waveguide.

Three-dimensional (3D) integrated circuits (IC) are emerging as a viable solution to enhance the performance of Multi-processor System-On-Chip (MPSoC). The use of highspeed hardware and the increased density of 3D architectures present novel challenges concerning thermal dissipation and power management. Most approaches at power and thermal modeling use either static analytical models or slow low-level analog simulations. In this paper, we propose a novel thermal modeling methodology for evaluation of 3D MPSoCs. The integration of this methodology in a virtual platform enables effcient dynamic thermal evaluation of a chip. We present initial results for an architecture based on a 3D Network-On-Chip (NoC) interconnecting 2D processing elements (PE). Our methodology is based on the finite difference method: we perform an initial static characterization, after which high-speed dynamic simulation is possible.

This paper presents 2-inputs cells designed to perform reconfigurable operations in nanometric systems exploiting the ambipolar property of double-gate (DG) carbon nanotube (CNT) FETs. Previous work [1] described a dynamic logic cell generating only 14 functions instead of 16 normally performed by the multiplexer-based logic part of a CLB (Configurable Logic Block) of an FPGA for 2-inputs. In this work, a reconfigurable 2-input dynamic logic cell designed using DG-CNTFET devices is able to achieve the whole set of 16 functions exploiting a specific correlation between input and configuration signals to offer full functionality over previous version. We also built a reconfigurable 2-input static logic cell which performs 16 functions. Both cells demonstrate a significant reduction in circuit complexity with respect to conventional CMOS-based reconfigurable cells for equivalent functionality. Compared with a 2-LUT, the dynamic cell improve the time delay by a factor of 2X to the detriment of 2X increase in power consumption, while the static logic cell shows an improvement of 2X in term of power consumption and time delay.

Silicon Nanowire technology has been demonstrated to be a promising candidate to fabricate nanowire crossbars. The use of such devices in a real architectural as well as in a design environment is an ongoing research topic. In this paper, we investigate the use of a lithography-based industrial process for designing a 4-to-1 multiplexer in a crossbar circuit. We show that by considering the line parasitic, the crossbar demonstrates poor performance in a 65-nm technology, while the area and power savings are about 6× and 1.5× respectively vs. the CMOS implementation. However, extrapolation to the 9-nm node shows a 2× better performance and 67× area saving.

This paper presents IDEA1, a validated SystemC-based simulator for WSNs. It allows the system-level performance evaluation (e.g., packet transmission and energy consumption) with elaborate models of sensor nodes. IDEA1 uses a clock-based synchronization mechanism to support simulations with cycle accurate communication and approximate time computation. Its accuracy has been validated by a testbed of 9 nodes. The average deviation between the IDEA1 simulations and experimental measurements is 5.9%. The performances of IDEA1 have also been compared with NS-2, one of the most widely used simulators in WSN research. To provide a similar result (deviation less than 5%) at the same abstraction level, the simulation of IDEA1 is 2 times faster than NS-2. Moreover, with the hardware and software co-simulation feature, IDEA1 provides more detailed modeling of sensor nodes than NS-2.

Trends in design of the next generation of Multi-Processors System on Chip (MPSoC) point to 3D integration of thousand of processing elements, requiring high performance interconnect for high throughput and low latency communications. Optical on-chip interconnects enable significantly increased bandwidth and decreased latency. They are thus considered as one of the most promising paradigms for the design of such system. However, existence of interfaces between electronic and photonic signals implies strong constraints on the layout of the 3D architecture and may impact the architecture scalability. In this paper, we propose and evaluate a possible layout for an optical Network-on-Chip used to interconnect processing elements located on different electrical layers.

The introduction of 3D chip architectures is an increasingly attractive integration solution due to the potential performance improvement, power consumption reduction and heterogeneous integration. With another dimension to take into account, the complexity of 3D floorplan algorithms is increased. In this paper we discuss the implementation of such an algorithm and identify parameters that play a role in the solution quality. We then propose the use of a genetic algorithm to discover sets of parameters that guarantee good floorplan quality. The optimized floorplanner rivals existing state of the art tools, proving the efficiency of our method.

This article describes a novel computing architecture organization based on nanoscale logic cells. We propose the use of a cluster of matrix arrangements of cells. In order to interconnect such fine-grained logic cells within a matrix, conventional techniques are not suitable due to a large interconnect overhead. Therefore, we propose the use of static and incomplete interconnect topologies to create matrices of cells. We also propose a method to map functions onto such architectures. We then explore the main parameters of the structure (size of matrices and interconnect topologies) and their impact on the main performance metrics (packing efficiency, speed, and fault tolerance). A cluster packing method also allows the evaluation of the number of matrices used by complex functions and the fill factor for various matrix sizes. The analyses show that this approach is particularly suited for matrices of 16 cells interconnected by modified omega networks. We can conclude that this architecture could improve the scalability of traditional FPGAs by a factor of 8.5.

Back-end-of-line non-volatile resistive memories like Phase Change Memories (PCMs) are promising to solve memory issues in different architectures. In this paper, we investigate the usage of PCM to build an elementary configuration memory node for reconfigurable logic, such as Field-Programmable Gate Arrays (FPGAs). We propose an elementary circuit realized by 2 resistive memories and 1 programming transistor able to store a configuration voltage. We investigate the proposed node in terms of area and write time and we assess its impact on complex circuits. We show that the elementary memory node yields an improvement in area and write time of 1.5x and 16x respectively vs. a regular Flash implementation. Implemented in FPGAs, the memory node yields a delay reduction up to 51%, thanks to the reduction of dimensions and low on-resistance of PCMs.

Optical network-on-chip (ONoC) is a well accepted emerging technology for use as a communication platform for systems-on-chip (SoC). Its heterogeneous nature dictates developing a hierarchical model and tools for its design and analysis. This paper presents a reconfigurable ONoC model that can be used for analyzing the network at three hierarchical levels: system level, behavioral level, and physical level. At system level, the proposed ONoC model can be used to evaluate the network performance metrics (e.g. latency and throughput). At behavioral level, the model can be used to analyze the functionality of the whole ONoC from the interaction and the integration of its constituent building blocks. At the physical level, the model can be used to analyze the effect and verify the joint feasibility of optoelectronic and photonic devices specifications for reliable data communication and can further be used as a reference golden model during the design phase of the physical devices. The proposed model has been integrated successfully inside an industrial simulation environment (ST GenKit) using an industrial standard (VSTNoC) protocol.

6-8 July 2014

This paper describes a dynamically reconfigurable 8-function logic gate (CNT-DR8F) based on a double-gate carbon nanotube field effect transistor (DG-CNTFET). The design is based on a property specific to this device: ambivalence, enabling p-type or n-type behavior depending on the back-gate voltage. Using available models, CNT-DR8F is proposed, simulated and analyzed at 20 GHz operation. We also give an example functional block (full adder) to show how to construct logic circuits based on the association of physically identical reconfigurable logic cells.

This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimation of the maturity of design and modeling techniques with respect to various physical domains. Industry-level MEMS integration, and more prospective microfluidic biochip systems are considered at both technological and EDA levels. Finally, specific flows for signal abstraction heterogeneity in RF SiP and for functional co-verification are discussed

Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect limitations in future systems-on-chip. However, the multiphysics nature of the design problem and the lack of a mature integrated photonic technology have contributed to severe difficulties in assessing its suitability. This paper describes a systematic, fully automated synthesis method for integrated microsource-based optical interconnect capable of optimally sizing the interface circuits based on system specifications, CMOS technology data, and optical device characteristics. The simulation-based nature of the design method means that its results are relatively accurate, even though the generation of each data point requires only 5 min on a 1.3-GHz processor. This method has been used to extract typical performance metrics (delay, power, interconnect density) for optical interconnect of length 2.5-20 mm in three predictive technologies at 65-, 45-, and 32-nm gate length.

In this paper, we present a tool to analyze photonic devices that can be used to realize basic building blocks of an optical network-on-chip (ONoC). Co-design between electrical tools and optical tools is possible. The VHDL-AMS language has been used to implement behavioral models of photonic devices. For low-level simulation, a gateway between an optical simulator, based on the finite elements method, and a typical EDA layout editor has been realized.

For extremely low-power logic, three very new and promising techniques will be described. The first are methods on circuit and system level for reduced supply voltages. In large logic blocks, interconnect becomes a main issue, that could be solved by on-chip optical interconnect. Nano-devices will also be presented, as a possibility to compute with nearly zero power, and compared to future 10 nanometers transistors.

In this paper, we present a framework for the automated design of integrated multi-domain systems. The platform allows the designer to set optimization problems according to a hierarchical decomposition strategy, define complex specification functions for each block at a given hierarchical level, follow the progress of optimization and finally view results. Encapsulation of design methodologies is simplified through access to a library of optimization algorithms. The framework is demonstrated through the co-synthesis of a high-speed CMOS photoreceiver front-end comprised of a PIN photodiode and a transimpedance amplifier.

Internet success and ever-improving microprocessor performance have brought a need for new short range optical communications. The challenge is to integrate electronics, optoelectronic components and optical components on the same chip. Such assembly creates new constraints due to the interactions between different aspects (electronic, optical, thermal, mechanical) that designers have to deal with. Although specific tools have been used to design each module separately, there is no multi-domain simulator or design framework that can meet with such constraints. This paper describes how we can use VHDL-AMS to create a library of hierarchical models and to simulate optoelectronic devices and systems. These models can then be used to propagate specifications from the system down to the physical layer in a top-down approach and to predict the influence of physical parameters on the global performance in a bottom-up approach.

The switched current circuit technique allows mixed-signal integrated circuits including data-converters and filters to be fabricated in a conventional CMOS process. ASIMOV, described in this paper, is a computer-aided design tool to support the systematic design of such circuits. It is capable of topology selection and sizing of current memory cells from a set of user specifications, Analytical models, coupled with numerical optimization guided by a heuristic rule-base, are used for fast response time. Models for the most commonly used cells are implemented.