This paper presents a sub-1V delta-sigma modulator (DSM) with power and bandwidth (BW) scalability for IoT applications. It is built around a fully dynamic and low-voltage floating inverter amplifier (LVFIA). To extend the power and BW scalability of the LVFIA, its relatively supply-independent bias current is auto-controlled by DSM’s sampling frequency$f_{s}$. Dynamic techniques such as auto-zeroing and chopping are applied to achieve low noise. Fabricated in a 130nm CMOS, the proposed sub-1V DSM shows a near-consistent SNDR (~90dB) and linearly scalable power and BW (2.5nW/Hz) over a$\times 30$scaling range of$f_{s}$. It achieves Walden FoM and Schreier FoM of 51.3fJ/conv-step and 175.7dB, respectively.

This paper presents a power-efficient and quickly-settled chopper-stabilized capacitively coupled instrumentation amplifier (CCIA) for neural recording applications. To achieve a relatively-low high-pass corner frequency while achieving fast-settling, a duty-cycled resistor (DCR) based very-large time constant (VLT) integrator is proposed. By stacking inverters and splitting the input capacitor network, the input stage of the CCIA achieves four-time current reuse, significantly improving the power-efficiency. A prototype in 180-nm CMOS technology has 2.2µV input-referred noise (IRN) with 5kHz bandwidth (BW) while consuming only 2.92µA current from a 1.2V supply, achieving a noise efficiency factor (NEF) of 2.1 and a power efficiency factor (PEF) of 5.2. Simulations show that it can settle within 10ms after powering on with a maximum electrode DC offset of 50 mV.

A reconfigurable fully integrated automatic gain control (AGC) amplifier is presented which is based on a dual mode continuous gain adjustment variable-gain amplifier (VGA). The VGA is realized based on the current-steering structure, achieving a linear-in-dB gain tuned by AGC’s feedback voltage. A current division active load is proposed, which provides additional gain control range and realizes gain robustness to process and supply variations without extra calibration. Simulated with Cadence IC, the maximum gain variations due to process and supply variations are 3.5 dB and 2.6 dB, respectively. By using dual mode gain tuning technique, the VGA achieves a total gain range of 68.2 dB. Both bandwidth and gain of the VGA are adjusted independently. The AGC is realized in UMC 55-nm CMOS technology with 0.026 mm2core area. With the current division ratio K of 0.5, the proposed VGA achieves a linear-in-dB gain of 42.2 dB (−30.0 to 12.2 dB) with less than 0.79 dB error. The −3 dB bandwidth can be adjusted from 80 MHz to 140 MHz and is insensitive to gain variations. The power dissipation is from 2.9 mW to 4.5 mW. This design features bandwidth scalability and the gain independent of bandwidth to achieve various applications.

Sparse general matrix multiplication (SpGEMM) is a fundamental building block in numerous scientific applications. One critical task of SpGEMM is to compute or predict the structure of the output matrix (i.e., the number of nonzero elements per output row) for efficient memory allocation and load balance, which impact the overall performance of SpGEMM. Existing work either precisely calculates the output structure or adopts upper-bound or sampling-based methods to predict the output structure. However, these methods either take much execution time or are not accurate enough. In this paper, we propose a novel sampling-based method with better accuracy and low costs compared to the existing sampling-based method. The proposed method first predicts the compression ratio of SpGEMM by leveraging the number of intermediate products (denoted as FLOP) and the number of nonzero elements (denoted as NNZ) of the same sampled result matrix. And then, the predicted output structure is obtained by dividing the FLOP per output row by the predicted compression ratio. We also propose a reference design of the existing sampling-based method with optimized computing overheads to demonstrate the better accuracy of the proposed method. We construct 623 test cases with various matrix dimensions and sparse structures to evaluate the prediction accuracy. Experimental results show that the absolute relative errors of the proposed method and the reference design are 1.30% and 7.93%, respectively, on average, and 25% and 158%, respectively, in the worst case.

In this brief, an analytical model for the reliability-oriented design of injection-locked frequency divider (ILFD) is proposed. It is able to provide a clear evaluation of startup condition in the ring oscillator (RO)-based ILFD, which has not been clearly defined with the conventional zero-pole theory. A new startup condition analysis is presented and applied in designing an ILFD to achieve a reasonable compromise between a robust startup condition and a wide locking range. To verify this theory, a prototype is fabricated using a standard 0.18 μm CMOS process, maintaining a reliable startup over potential variations of manufacturing or working conditions. The experimental results at industrial temperature ranges under different supply voltages suggest that the proposed divider is able to work robustly from 0.19 to 1.24 GHz with a maximum power consumption of 0.246 mW from a 1.2-V supply, while occupying a silicon area less than 20 x 30 μm2.

A new time variant model for the time domain jitter in the TSPC frequency divider is proposed. The trade-off between the phase noise and power consumption in the prescaler design is analyzed. Based on the analysis, a new prescaler that has a better balance among the operating frequency, power consumption and phase noise is proposed. The analysis is verified by the simulation and measured results in this prescaler

The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and power consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 1.8 GHz for a 1.8 V supply voltage and a 5.8-mW power consumption. By using this counter, an ultra-wide range high resolution frequency divider is achieved with low power consumption for 5-6-GHz wireless LAN applications.