The semiconductor industry is steadily shifting toward disaggregated system design to overcome the scalability (yield and cost) limitations of monolithic integration. 2.5D integration offers a compelling pathway for realizing such systems, enabling the assembly of heterogeneous chiplets—compute, memory, analog & I/O, with dense interconnects and high bandwidth. Our previous work showcased experimental results from a multi-foundry chiplet design over a large passive silicon base. There were 20 chip slots (CS) on an interposer that can be configured with compute die (CD) or memory die (MD) chiplets. Building on this foundation, this paper introduces a methodology for system technology co-optimization (STCO) across several vectors. These include varying the number of chip slots, configuring slots with different numbers of MDs and CDs, sweeping the inter-die bandwidth, choosing between different technology nodes for the performance limiting MDs. This work demonstrates how the design and technology choices affect system performance, power, and cost across different workloads, empowering designers to select optimal configurations for their specific needs.

This work presents the utilization of rotary traveling wave oscillators (RTWOs) to implement an Ising machine. Ising machines utilizing ring oscillators have recently been demonstrated on silicon, for instance, for the solution of a max-cut problem. Rotary traveling wave oscillators scale better in frequency compared to ring oscillators, but have increased power consumption. Phase-based computing principles, implemented with the proposed RTWO-based Ising machines, are prime for high speed phase-based computation. The experiments reveal the proposed RTWO-based Ising machines provide significant reduction (5x) in runtime in the solution of the max-cut problem. The power dissipation is two orders of magnitude higher than the minuscule, low power ring-oscillators but RTWO-based Ising machines sub-linear increase with the demonstrated frequency increase from 2GHz to 32GHz for high speed phase-based computing. The accuracy of the solution is significantly improved as well, as demonstrated with respect to two of the D-Wave solvers (tabu and simulated annealing) acting as the baseline for ring oscillator and RTWO based Ising machines.

With the increasing adoption of robots across industries, it is crucial to focus on developing advanced algorithms that enable robots to anticipate, comprehend, and plan their actions effectively in collaboration with humans. We introduce the Robot Autonomous Motion (RoAM) video dataset, which is collected with a custom-made turtlebot3 Burger robot in a variety of indoor environments recording various human motions from the robot’s ego-vision. The dataset also includes synchronized records of the LiDAR scan and all control actions taken by the robot as it navigates around static and moving human agents. The unique dataset provides an opportunity to develop and benchmark new visual prediction frameworks that can predict future image frames based on the action taken by the recording agent in partially observable scenarios or cases where the imaging sensor is mounted on a moving platform. We have benchmarked the dataset on our novel deep visual prediction framework called ACPNet where the approximated future image frames are also conditioned on action taken by the robot and demonstrated its potential for incorporating robot dynamics into the video prediction paradigm for mobile robotics and autonomous navigation research.

Rotary traveling wave oscillators (RTWO) are designed to provide a high frequency clock signal through the silicon interposer to multiple chiplets in a heterogeneous 2.5D system. In particular, two different RTWO synchronization topologies are presented: 1) Active interposer RTWO and 2) passive interposer RTWO. The proposed topologies are evaluated across a silicon interposer with a dimension of 42 mm × 20 mm. Each topology is implemented with post-layout, parasitic extracted models for a clock frequency of ≈8 GHz. The performance metrics are presented for clock period, skew, rise time, fall time, and oscillation start-up and settling times across the multi-die system (MDS) with SPICE based simulations.

Predicting the motion of observed entities benefits humans almost seamlessly. The same benefits can be proliferated to mobile autonomous systems if we have a reliable, real-time solution to predict the motion of any object of interest, be it the host’s own motion or that of an observed foreign object. In this work, a novel Multi-Variable State Prediction (MVSP) methodology is devised for real-time trajectory prediction. MVSP incorporates cascaded stages of HMM with Viterbi algorithm and probabilistic quantization for accurately predicting the motion characteristics of the moving object. The overall scheme is employed to predict the motion of moving objects in a 3D space. The proposed approach is verified on both synthetically generated data sequences and data-sets captured from real-life experiments. For a practical scenario, the experiments resulted in an RMS error of 0.6m for a predicted distance of ~18m demonstrating the effectiveness and accuracy of the proposed methodology.

Path planning and smooth trajectory generation are critical capabilities for efficient navigation of mobile robots operating in challenging and cluttered environments. For real time and autonomous operations of mobile robots, intelligent algorithms, efficient and light-weight compute, and smooth trajectory are key components. In this work, we propose an intelligent, probabilistic Gaussian mixture model driven Bi-RRT (PG-RRT) algorithm which generates nodes in the most probable regions for faster convergence. The proposed algorithm is tested in various simulated environments including highly cluttered obstacles. The experimental results of PG-RRT are compared with state-of-the-art path planning algorithms. The results show significant improvement in the number of iterations (up to 26X) and runtime (up to 17.5X) demonstrating the superiority of the proposed PG-RRT algorithm.

Autonomous navigation through unknown and complex environments is a fundamental capability that is essential in almost all robotic applications. Optimal robot path planning is critical to enable efficient navigation. Path planning is a complex, compute and memory intensive task. Traditional methods employ either graph based search methods or sample based methods to implement path planning, which are sub-optimal and compute/memory-intensive. To this end, an Adaptive Directional Planner (ADP) algorithm is devised to achieve real-time, energy-efficient, memory-optimized, robust local path planning for enabling efficient autonomous navigation of mobile robots. The ADP algorithm ensures that the paths are optimal and kinematically-feasible. Further, the proposed algorithm is tested with different challenging scenarios verifying the functionality and robustness. The ADP algorithm implementation results demonstrate 40- 60X less number of nodes and 40 - 50X less execution time compared to the standard TP-RRT schemes, without compromising on accuracy. Finally, the algorithm has also been implemented as an accelerator for non-holonomic, multi-shape, small form factor mobile robots to provide a silicon solution with high performance and low memory footprint (28KB).

Optimal path planning and smooth trajectory planning are critical for effective navigation of mobile robots working towards accomplishing complex missions. For autonomous, real time and extended operations of mobile robots, the navigation capability needs to be executed at the edge. Thus, efficient compute, minimum memory utilization and smooth trajectory are the key parameters that drive the successful operation of autonomous mobile robots. Traditionally, navigation solutions focus on developing robust path planning algorithms which are complex and compute/memory intensive. Bidirectional-RRT(Bi-RRT) based path planning algorithms have gained increased attention due to their effectiveness and computational efficiency in generating feasible paths. However, these algorithms neither optimize memory nor guarantee smooth trajectories. To this end, we propose a kinematically constrained Bi-RRT (KB-RRT) algorithm, which restricts the number of nodes generated without compromising on the accuracy and incorporates kinodynamic constraints for generating smooth trajectories, together resulting in efficient navigation of autonomous mobile robots. The proposed algorithm is tested in a highly cluttered environment on an Ackermannsteering vehicle model with severe kinematic constraints. The experimental results demonstrate that KB-RRT achieves three times (3 X) better performance in terms of convergence rate and memory utilization compared to a standard Bi-RRT algorithm.

Resonant rotary clocking is a clocking technology for high frequency clock generation and distribution at a low power dissipation rate. It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation. In this paper, the feasibility of zero clock skew synchronization with the rotary clocking technology implemented on the ROA is shown. Design automation experiments are performed to demonstrate that the zero clock skew operation can be achieved with minimal change in the performance of rotary clock operation. In particular, a marginal ±1.5% change in the tapping wirelength and a negligible 0.38% average skew mismatch are reported in experiments on R1-R5 and ISPD 2010 benchmark circuits.

A novel rotary clock network routing method is proposed for the low-power resonant rotary clocking technology which guarantees: 1. The balanced capacitive load driven by each of the tapping points on the rotary rings, 2. Customized bounded clock skew among all the registers on chip, 3. A sub-optimally minimized total wirelength of the clock wire routes. In the proposed method, a forest of steiner trees is first created which connects the registers so as to achieve zero skew and greedily balance the total capacitance of each tree. Then, a balanced assignment of the steiner trees to the tapping points is performed to guarantee a balanced capacitive load on the rotary network. The proposed routing method is tested with the ISPD clock network contest and IBM r1-r5 benchmarks. The experimental results show that the capacitive load imbalance is very limited. The total wirelength is reduced by 64.2% compared to the best previous work known in literature through the combination of steiner tree routing and the assignment of trees to the tapping points. The average clock skew simulated using HSPICE is only 8.8ps when the bounded skew target is set to 10.0ps.

Rotary clocking is a resonant clocking technology for clock network design and distribution in high performance digital VLSI circuits. Rotary clocking technology offers an attractive alternative to the conventional clocking with high frequency clock signal generation at a low power dissipation rate. Traditionally, rotary clocking has been implemented using a regular array (grid) topology called rotary oscillatory arrays (ROA). In this paper, a custom rotary oscillatory array (CROA) topology is proposed for the generation and distribution of rotary clocking. The issues related to timing closure are addressed and the simulation-based analysis of the custom rotary rings is presented. The CROA design methodology is tested on the IBM R1-R5 benchmark circuits. Compared to the traditional ROA, custom ROA results in 39.25% of tapping wirelength savings. The parasitic effects due to the customization of the topology - computed with partial element equivalent circuit (PEEC) analysis - are incorporated and the CROA topologies are simulated in SPICE. The simulation results show that, with additional parasitics due to the topological factors, the resultant clock frequency is observed to be 8.79% slower (assuming the tapping wirelength remains the same) than the expected frequency of operation without considering the topological factors.

Rotary clocking is a traveling wave based high-speed resonant clocking technology with low-power and controllable-skew properties. Capacitive load balance and bounded clock skew are identified as the primary requirements to maintain a stable oscillation frequency across the rings and to achieve timing closure, respectively, in the rotary oscillatory array (ROA). Towards this end, two methodologies are proposed to achieve balanced capacitive loads across the rings of the ROA with a bounded skew constraint. Experiments performed on IBM R1-R5 benchmark circuits show a 5.62X improved capacitive balance and a 3.67% improved clock skew to a total skew of 6.55% of the clock period at 1.8GHz. SPICE simulations show that the frequency variation across the rings of the ROA is reduced from 10.14% to 2.12% as well. Power dissipated with the proposed optimization methodologies are within ±1.5% of the conventional design automation techniques for rotary synchronization.

Resonant rotary clocking is a low power-high speed clock distribution technology for the modern VLSI circuits. Alternative topological implementations of rotary clocking with non-regular custom rings have been proposed in literature. In this paper, the impact of parasitics of the non-regular topological geometries on the rotary operating characteristics is presented. In particular, partial element equivalent circuit (PEEC) analysis is used to show that the corner geometry in a custom ring increases the mutual inductance approximately by 80%. Also, SPICE simulations are performed where the parasitics due to the topological factors are incorporated for an 8% increased accuracy in simulation. Further, the power dissipation on the rotary ring is analyzed with varying number of corners. When tested with the IBM R1-R5 benchmark circuits, the total power dissipated on a custom ring (corners between 4 and 12) is within ±5% of the total power dissipated on a regular ring(4 corners).

Timing closure and power envelopes for contemporary multi-core chips with high speed clock networks make the clock distribution design a challenging task. Resonant rotary clocking is a novel clocking technology for multi-gigahertz rate clock generation that provides minimal power dissipation. Rotary clocking implementations can easily provide independent synchronization of multiple cores as well. The traditional rotary clock design involves a regular array topology of oscillatory rings. In this paper, the rotary clock networks are designed and implemented using a custom ring topology. Custom ring topologies are advantageous as they reduce the total tapping wirelength for the registers tapping onto the oscillatory rings. A maze router based algorithm is developed for the implementation of custom topology rotary rings. In experiments performed on UCLA IBM R1-R5 benchmark circuits with the Elmore delay model, an improvement of 11.04% for register tapping wirelength is achieved on average.