Energy consumption and the associated environmental impact are a pressing challenge faced by the transportation sector. Emerging electric-drive vehicles have shown promises for substantial reductions in petroleum use and vehicle emissions. Their success, however, has been hindered by the limitations of energy storage technologies. Existing in-vehicle lithium-ion battery systems are bulky, expensive, and unreliable. Energy storage system (ESS) design and optimization is essential for emerging transportation electrification. This paper presents an integrated ESS modeling, design, and optimization framework targeting emerging electric-drive vehicles. A large-scale ESS modeling solution is first presented, which considers major runtime and long-term battery effects, and uses fast frequency-domain analysis techniques for efficient and accurate characterization of large-scale ESS. The proposed design framework unifies design-time optimization and runtime control. This conducts statistical optimization for ESS cost and lifetime, which jointly considers the variances of ESS due to manufacture tolerance and heterogeneous driver-specific runtime usage. This optimizes ESS design by incorporating complementary energy storage technologies, e.g., lithium-ion batteries and ultracapacitors. Using physical measurements of battery manufacture variation and real-world user driving profiles, our experimental study has demonstrated that the proposed framework effectively explores the statistical design space and produces cost-efficient ESS solutions with statistical system lifetime guarantees.

While transistor performance and energy efficiency have dramatically improved in recent years, electrical interconnect improvements has failed to keep pace. Recent advances in nanophotonic fabrication have made on-chip optics an attractive alternative. However, system integration challenges remain. In particular, the parameters of on-chip nanophotonic structures are sensitive to fabrication-induced process variation and run-time spatial thermal variation across the die. This work addresses the performance and reliability challenges that arise from this sensitivity to variation. The paper first presents a model predicting the system-level effects of thermal and process variation in nanophotonic networks. It then shows how to optimize many-core system performance and reliability by using run-time techniques to compensate for the thermal and process variation effects.

Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization due to conflicts and pollution. Explicit motion of data in these architectures, such as message passing, can provide hints about program behavior that can be used to hide latency and improve cache behavior. However, to make these models attractive, synchronization overhead and data copying must also be offloaded from the processors. In this paper, we describe a Message Orchestration and Performance Enhancement Device (MOPED) that provides hardware mechanisms to support state-of-the-art message passing protocols such as MPI. MOPED extends the per-processor cache controllers and coherence protocol to support message synchronization and management in hardware, to transfer message data efficiently without intermediate buffer copies, and to place useful data in caches in a timely manner. MOPED thus allows full overlap between communication and computation on the cores. We extended a 16-core full-system simulator based on Simics and FeS2. MOPED interacts with the directory controllers to orchestrate message data. We evaluated benefits to performance and coherence traffic by integrating MOPED into the MPICH runtime. Relative to unmodified MPI execution, MOPED reduces execution time of real applications (NAS Parallel Benchmarks) by 17-45% and of communication microbenchmarks (Intel's IMB) by 76-94%. Off-chip memory misses are reduced by 43-88% for applications and by 75-100% for microbenchmarks.

The emergence of multi-electrode array enables the study of real-time neurophysiological activities across multiple regions of the brain. However, the real-time extracellular action potentials recorded on any electrode represent the simultaneous electrical activity of an unknown number of neurons which present a critical challenge to the accuracy of interpretation and identification of the neural circuitry in the subsequent analysis. In this paper, we present a principal component analysis approach utilizing Hebbian eigenfilter to identify the corresponding electrical activities of each neuron, namely spike sorting. The Hebbian eigenfilter greatly simplifies the computational complexity of eigen-projection. An efficient FPGA-based Hebbian eigenfilter is proposed. The performance, accuracy and power consumption of our Hebbian eigenfilter are thoroughly evaluated through synthetic spike trains. The proposal enables real-time spike sorting and analysis, and leads the way towards future motor and cognitive neuroprosthetics.

Recent advances in nanophotonic technology have made nano- photonic interconnect an attractive on-chip communication solution for emerging many-core systems. However, fabrication- induced process variation and run-time system thermal effects directly affect nanophotonic device operation, and introduce serious challenges, e.g., signal power loss and crosstalk, to the power, performance and reliability of nanophotonic communication.

On many-core chip designs, short, often-multicast, latency-critical messages, used extensively in high-level coherence and synchronization protocols, often become the bottleneck of parallel performance scaling. This paper presents Spectrum, a hybrid nanophotonic-electric on-chip network that optimizes both throughput and latency. Spectrum's novel planar nanophotonic subnetwork broadcasts latency-critical messages through a wavelength-division multiplexed (WDM) two-dimensional waveguide. Spectrum's throughput-optimized packet-switching electrical subnetwork handles high bandwidth traffic. Overall, Spectrum delivers an almost ideal CMOS-compatible interconnection network for many-core systems.

Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip data and protocol transactions. The main problem posed by this communication fabric is the potentially-high and nondeterministic network latency caused by router data buffering and resource arbitration. This paper describes a new method to minimize on-chip network latency, which is motivated by the observation that only a small percentage of on-chip data and protocol traffic is latency-critical. Existing work focusing on minimizing average network latency is thus suboptimal. Such techniques expend most of the design, area, and power overhead accelerating latency-noncritical traffic for which there is no corresponding application-level speedup. We propose run-time techniques that identify latency-critical traffic by leveraging network data-transaction and protocol information. Latency-critical traffic is permitted to bypass router pipeline stages and latency-noncritical traffic. These techniques are evaluated via a router design that has been implemented using TSMC 65nm technology. Detailed network latency simulation and hardware characterization demonstrate that, for latency-critical traffic, the proposed solution closely approximates the ideal interconnect even under heavy load while preserving throughput for both latency-critical and noncritical traffic.

This paper presents a novel simultaneous multithreading (SMT) VLIW DSP architecture with dynamic dispatch mechanism to address the challenge of the underutilization of computing resources in the non-unit assumed latency (NUAL) VLIW DSPs. The SMT technology exploits the unused instruction slots by converting the thread-level parallelism to the instruction-level parallelism, improving the efficiency. With the specifically designed registers for eliminating the horizontal dependencies among the execution-packet, the NUAL VLIW DSP architecture supports issuing any subset of instructions of the execution-packet based on the availability of the corresponding functional units. With the dynamic dispatch mechanism, the DSP issues instructions to functional unit at run-time rather than at compile-time, such that the issue conflicts among multiple threads are reduced significantly. The new VLIW DSP architecture is implemented and evaluated, and the results show that the architecture can effectively increase the processor throughput, hide the cache miss latencies, and improve the performance on digital signal processing.

On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article presents Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network. Iris' linear-waveguide-based throughput-optimized circuit-switched subnetwork supports throughput-sensitive data transfer. Iris' planar-waveguide-based WDM broadcast-multicast subnetwork optimizes latency-critical traffic and supports the circuit setup of circuit-switched communication. Overall, the proposed design delivers an on-chip communication backplane with high power efficiency, low latency, and excellent throughput.

Very long instruction word (VLIW) processors are generally implemented as clustered architectures in order to reduce delay, area and power when function units increase. However, a side effect of clustered architectures is processor performance degradation, due to additional latency and copy operations from data transfers between these clusters. Therefore, appropriate scheduling algorithms must be applied to overcome this. This paper presents a new register-file-connectivity clustered VLIW (RFCC-VLIW) architecture, in which a global register file is used to transfer data between clusters. Using the global register file, latency and copy operations can be eliminated. Additionally, the paper presents a scheduling algorithm for the RFCC-VLIW architecture. The two-dimension force-directed algorithm can assign instructions evenly to all clusters and reduce usage of ports and global registers. Experimental results show our algorithm outperforms other scheduling algorithms for clustered VLIW when targeted toward RFCC-VLIW architectures.

This paper presents a novel architecture of register files that combines the local register files and the global register file for clustered VLIW (Very Long Instruction Word) processors. The communication between function units through global register file will be more efficient. The concept of associate register is introduced for this architecture. This makes it possible to write a result to two destination registers in one operation, which can efficiently speed up the software pipelining.

A test point selection algorithm TEPSAUS (TEst-Point Selection Algorithm Using Small signal model) for scan based build-in self-test (BIST) is proposed in this paper, In order to reduce the computational complexity, the algorithm uses Small Signal Model (SSM) to build recursion formulas for cost reduction functions. With the recursion functions, the cost reduction functions can be calculated efficiently.

Details a novel power estimation algorithm based on rate of bit propagation (RBP). Considering the reduction of RBP an advanced scan array architecture is proposed in which a wrapper and two dimensional scan chain is adopted. Estimated results based on RBP and experimental results of industrial circuits both show that testing power was reduced to the level of the functional power. Furthermore pseudo-BIST is integrated with the wrapper to reduce the test time.