In today's data centers, precisely controlling server power consumption is an essential way to avoid system failures caused by power capacity overload or overheating due to increasingly high server density. While various power control strategies have been recently proposed, existing solutions are not scalable to control the power consumption of an entire large-scale data center, because these solutions are designed only for a single server or a rack enclosure. In a modern data center, however, power control needs to be enforced at three levels: rack enclosure, power distribution unit, and the entire data center, due to the physical and contractual power limits at each level. This paper presents SHIP, a highly scalable hierarchical power control architecture for large-scale data centers. SHIP is designed based on well-established control theory for analytical assurance of control accuracy and system stability. Empirical results on a physical testbed show that our control solution can provide precise power control, as well as power differentiations for optimized system performance and desired server priorities. In addition, our extensive simulation results based on a real trace file demonstrate the efficacy of our control solution in large-scale data centers composed of 5,415 servers.

This demonstration presents a power panel level power monitoring and management (PMM) system developed at IBM Research. The ultimate goal of this project is to develop a low-cost, high accuracy, non-intrusive and retrofittable data center power management system.

In today's data centers, precisely controlling server power consumption is an essential way to avoid system failures caused by power capacity overload or overheating due to increasingly high server density. While various power control strategies have been recently proposed, existing solutions are not scalable to control the power consumption of an entire large-scale data center, because these solutions are designed only for a single server or a rack enclosure. In a modern data center, however, power control needs to be enforced at three levels: rack enclosure, power distribution unit, and the entire data center, due to the physical and contractual power limits at each level. This paper presents SHIP, a highly scalable hierarchical power control architecture for large-scale data centers. SHIP is designed based on well-established control theory for analytical assurance of control accuracy and system stability. Empirical results on a physical testbed show that our control solution can provide precise power control, as well as power differentiations for optimized system performance. In addition, our extensive simulation results based on a real trace file demonstrate the efficacy of our control solution in large-scale data centers composed of thousands of servers.

Today's computing environment is changing, with growing emphasis on reducing both operational energy costs and the high capital costs to reliably deliver power and cooling to systems in factory-sized data centers. The greening of data centers is challenging microprocessor and system designs, including server, storage, and network designs, to deliver ever higher performance within strict power and cooling constraints. This paper outlines some of the challenges, research approaches and holistic solutions to more energy efficient data centers, starting with microprocessor and system design and extending to the broader environment.

The growing power and cooling requirements of high-density computing systems pose significant challenges for the design and operation of computers and their facilities. The rising operating expenses for datacenters demand the implementation of energy-efficient technologies and the best power management solutions. This tutorial addresses power management and cooling solutions from the individual computer system level to the datacenter. The audience will learn about the fundamental nature of the problems, approaches to developing solutions, available commercial solutions, and current research directions.

Summary form only given. Power-related research activities at IBM's Austin Research Lab (ARL) include low power circuitry, power-efficient microprocessor designs, and server systems power measurement and management at many different levels. Researchers are given the opportunity to see their contributions at all levels of product design, since IBM produces its own microprocessors for its System p, i, and z platforms as well as producing System x platforms with other vendors' microprocessors, as well as marketing Tivoli systems management middleware.

The combination of increasing component power consumption, a desire for denser systems, and the required performance growth in the face of technology-scaling issues are posing enormous challenges for powering and cooling of server systems. The challenges are directly linked to the peak power consumption of servers.Our solution, Power Shifting, reduces the peak power consumption of servers minimizing the impact on performance. We reduce peak power consumption by using workload-guided dynamic allocation of power among components incorporating real-time performance feedback, activity-related power estimation techniques, and performance-sensitive activity-regulation mechanisms to enforce power budgets.We apply our techniques to a computer system with a single processor and memory. Power shifting adds a system power manager with a dynamic, global view of the system's power consumption to continuously re-budget the available power amongst the two components. Our contributions include:• Demonstration of the greater effectiveness of dynamic power allocation over static budgeting,• Evaluation of different power shifting policies,• Analysis of system and workload factors critical to successful power shifting, and• Proposal of performance-sensitive power budget enforcement mechanisms that ensure system reliability.

Existing techniques manage power for the main memory by passively monitoring the memory traffic, and based on which, predict when to power down and into which low-power state to transition. However, passively monitoring the memory traffic can be far from being effective as idle periods between consecutive memory accesses are often too short for existing power-management techniques to take full advantage of the deeper power-saving state implemented in modern DRAM architectures. In this paper, we propose a new technique that will actively reshape the memory traffic to coalesce short idle periods --- which were previously unusable for power management --- into longer ones, thus enabling existing techniques to effectively exploit idleness in the memory

A quantitative performance study of two-phase locking in a parallel database machine using a simulation-based methodology is presented. The DBSIM simulation methodology uses a Petri-net model at the higher level and a queuing network model at the lower level. The Petri net model captures the characteristics of parallelism and synchronization at the workload level, while the queuing network model captures queuing aspects of the system at the physical resource level. Transactions in a workload are specified using a performance-oriented specification language based on the transaction component graph: a data-flow graph with database operators. The transaction specifications are translated into Petri-net representations to drive the simulation experiments. Results of an analysis of a two-phase locking strategy with machine sizes ranging from 4 to 256 processors are presented.>

We compare two high-availability techniques for recovery from media failures in database systems. Both techniques achieve high availability by having two copies of all data and indexes, so that recovery is immediate. “Mirrored declustering” spreads two copies of each relation across two identical sets of disks. “Interleaved declustering” spreads two copies of each relation across one set of disks while keeping both copies of each tuple on separate disks. Both techniques pay the same costs of doubling storage requirements and requiring updates to be applied to both copies.

A quantitative performance study of two-phase locking in a parallel database machine using a simulation-based methodology is described. The DBSIM simulation methodology uses models at two levels: a Petri net model at the higher level and a queuing network model at the lower level. The Petri net model captures the characteristics of parallelism and synchronization at the workload level, while the queuing network model captures queuing aspects of the system at the physical resource level. Transactions in a workload are specified using a performance-oriented specification language based on the transaction component graph, a data flow graph with database operators. The transaction specifications are translated into Petri net representations to derive the simulation experiments. The workload is a transaction taken from an order-entry application. A shared-nothing parallel machine architecture is assumed. Results of analysis of a two-phase locking strategy with machine sizes ranging from 4 to 256 processors are presented.>

This paper examines the problem of data placement in Bubba, a highly-parallel system for data-intensive applications being developed at MCC. “Highly-parallel” implies that load balancing is a critical performance issue. “Data-intensive” means data is so large that operations should be executed where the data resides. As a result, data placement becomes a critical performance issue.

The same application implemented on different systems will necessarily present different workloads to the systems. Characterizations of workloads intended to represent the same application, but input to models of different systems, must also differ in analogous ways. We present a hierarchical method for characterizing a workload at increasing levels of detail such that every characterization at a lower level still accurately represents the workload at higher levels.