With the continued scaling of VLSI technology beyond 3 nm, a consistent demand for layout reduction in standard cells has been made. CFET (Complementary-FET) has been accepted as a promising device technology, stacking N-FET on P-FET (or vice versa) to achieve this goal while providing metal interconnects on both the front and backside of the wafer through BEOL (back-end-of-line) processing. However, the layout synthesis of CFET based standard cells and its use in physical design implementation are not fully compatible with the effective exploitation of backside interconnects. This is because of a considerable overhead on the allocation of special vias in FEOL (front-end-of-line) referred to as tap-cells, which are essential for the net routes using backside wire. To overcome this drawback of using CFET cells, a new technology called FFET (Flip-FET) has been proposed, which flips the lower FET in CFET to enable direct pin accessibility on both sides of BEOL with no tap cells. In this context, we propose an FFET cell based DTCO methodology to fully utilize backside wires with minimal tap-cells. Precisely, we propose a three-step approach: (1) synthesizing multiple FFET standard cells with diverse styles of pin distribution for each of primitive logic gates, (2) performing a tap-cell avoiding cell replacement during placement optimization by using the cells obtained from Step 1 to prevent tap-cell allocation for net routing, and (3) rebalancing the wire usage between the frontside and backside to mitigate net congestion. Experiments with benchmark circuits show that our FFET cell based DTCO methodology scales up chip size beyond CFET designs with much fewer routing failures.

In deep-submicron technology nodes, I/O pin accessibility on the cells is crucial for successful net routing in physical design. For this reason, the conventional design flows have paid a considerable attention to acquiring the cell library with high pin accessibility to facilitate the net routing task. Nevertheless, the increase in routing failures is inherently unavoidable as the cell size shrinks with the progress of the technology node. In this context, this work proposes a new technique called adaptive pin-pattern modification (APM) to tackle this fundamental problem. Precisely, our proposed ECO-routing method based on adaptive pin-pattern modification makes use of three novel pin-pattern modifications on standard cells, which are referred to as pin-shift-trim (PST), pin-free (PF) and pin-bridge (PB). By applying these pin-pattern modifications adaptively and systematically to suit the circumstances to the individual cell instances with pin access failure, our ECO-router is able to explore the routable paths more extensively and effectively over the sequential, maze-routing based, ECO-routers but spend a much shorter time over the concurrent ECO-routers. Experimental results show that our proposed APM-enabled ECO-router resolves 17.7% of pin inaccessibility cases that a commercial tool has failed to find legal routes, with no penalty of chip PPA, and achieves over 116x speedup compared to the concurrent MCF (multi-commodity flow) based ECO-router.

Deep learning (DL) models have recently paid considerable attention to timing prediction in the place-and-route (P&R) flow. As yet, the DL-based prior works are confined to timing prediction at the time-consuming routing stage, and very few have addressed the timing prediction problem at the placement, i.e., at the pre-route stage. Moreover, no work has addressed a seamless link of timing prediction at the pre-route stage to the final timing optimization through commercial P&R tools. In this work, we introduce a novel framework called DTOC-P that seamlessly integrates deep-learning-driven timing optimization into cutting-edge commercial P&R tools. Our framework is composed of two phases: (1) the pre-route timing prediction phase that performs DL-driven arc delay and arc output slew prediction with an elaborated hierarchical model; (2) the timing optimization phase which incorporates commercial P&R tools with DL-driven prediction outcomes to perform timing optimization. In addition, DTOC-P framework achieves enhanced practicality with the application of continual learning in the timing prediction phase, and the concept of anomaly detection in the timing optimization phase. Experimental results show that our DTOC-P framework improves pre-route prediction accuracy by up to 55% and 47% on arc delay and arc output, which are further enhanced to encompass a broader range of designs by continual learning supported in DTOC-P, practically using a tenfold reduced training time compared to re-training all datasets from scratch. In terms of timing optimization, our experiments reveal that DTOC-P framework improves WNS, TNS, and the number of timing violation paths by up to 12%, 41%, and 34%, respectively, which is a remarkable progress compared to its predecessor through the integration of anomaly detection that excludes potential outliers to effectively protects against erroneous timing updates during the timing optimization phase.

Recently, deep-learning (DL) models have paid a considerable attention to timing prediction in the placement and routing (P&R) flow. As yet, the DL-based prior works are confined to timing prediction at the time-consuming global routing stage, and very few have addressed the timing prediction problem at the placement, i.e., at the pre-route stage. This is because it is not easy to “accurately” predict various timing parameters at the pre-route stage. Moreover, no work has addressed a seamless link of timing prediction at the pre-route stage to the final timing optimization through making use of commercial P&R tools. In this work, we propose a framework called DTOC, to be used at the pre-route stage for this end. Precisely, the framework is composed of two models: (1) a DL-driven arc delay and arc output slew prediction model, performing in two levels: (level-1) predicting net resistance (R), net capacitance (C), and arc length (Len), followed by (level-2) predicting arc delay and arc output slew from the R/C/Len prediction obtained in (level-1); (2) a timing optimization model, which uses the inference outcomes in our DL-driven prediction model to enable the commercial P&R tools to calculate the full path delays, setting update timing margins on paths, so that the P&R tools should use more accurate margins on timing optimization. Experimental results show that, by using our DTOC framework during timing optimization in P&R, we improve the pre-route prediction accuracy on arc delay and arc output slew by 20~26% on average, and improve the WNS, TNS, and the number of timing violation paths by 50~63 % on average.