Asynchronous circuits become an attractive alternative to synchronous circuits owing to their potential benefits such as low power consumption, and no clock distribution problems. However, handshake control and relative timing analysis make designing asynchronous circuits a complex and error-prone task. Moreover, traditional electronic design automation (EDA) tools are tailored specifically for synchronous circuits, resulting in significant manual effort when designing asynchronous circuits. To address these issues, this paper proposes a desynchronization method based on Chisel, which converts synchronous circuits into bundled-data asynchronous ones automatically. For demonstration, an open-source synchronous RISC-V processor is desynchronized to an asynchronous one, and both are implemented on Zynq7020 FPGA. The experimental results illustrate that the power consumption of Clicks for handshaking in the desynchronized processor is only 33.3% of that of the global clocks in the synchronous one. Besides, with Clicks the power consumption of memory access is reduced by 80%. Compared with previous synchronous and asynchronous RISC-V processors, the asynchronous RISC-V processor achieves up to 8.4x and 1.5x dynamic power reductions respectively.

This paper describes a bias-current-free hybrid phase-locked loop (PLL) architecture that employs a multi-phase time-interleaved phase detector (TI-PD) in a proportional-gain path. To achieve a low reference spur, the reduction of a common-mode (CM) ripple is done through phasor addition by distributing clock edges to multiple paths with a fixed delay. In addition to the spur suppression, the multi-phase TI-PD mitigates the mismatch problem of the multiple paths with an averaging effect. Compared with the single TI-PD-based PLL, the proposed PLL with the multi-phase TI-PD improves the spur performance by 30dB, achieving a reference spur of -81dBc in the simulation. With the fully voltage-domain operation, the proposed PLL is highly promising for low-voltage clock generation systems.

This paper describes a balanced frequency shift keying (FSK) modulation, namely quasi-balanced FSK (QB-FSK), for energy-efficient high-data-rate communication. Not suffering from data-pattern dependency, the proposed modulation method enables frequency modulation (FM) over 100 Mb/s by utilizing a wideband phase-locked loop (PLL). The QB-FSK signal is generated with the same baseband clock frequency as the non-return zero (NRZ)-coded binary FSK (BFSK) signal, resulting in improved bandwidth efficiency compared to other balanced FSK signals. For demodulation, the receiver employs a sideband energy detection (SB-ED) method. A FM discriminator converts the QB-FSK signal to an on-off keying (OOK) signal. After that, a band-pass filter (BPF) is used to filter out 1/f noise and dc offset. Based on the proposed QB-FSK modulation and the SB-ED method, a prototype FSK transceiver is implemented in 65-nm CMOS for high-data-rate sub-6-GHz proprietary wireless connectivity. The receiver successfully demodulates data at a rate of 200 Mb/s with a sensitivity of –67 dBm, while the transmitter can achieve a maximum data rate of 400 Mb/s. The 200-Mb/s transceiver achieves an energy efficiency of 0.14 nJ/b.

This paper describes a crystal-less heterodyne phase-tracking receiver (PTRX) architecture that offers a wide tracking range, flexible yet robust loop dynamics, and a 1-bit demodulation output. Unlike the sliding-IF PTRX, a nested integer-N bang-bang phase-locked loop (BBPLL) is implemented within the PTRX to enhance the tracking range by taking the output of an intermediate-frequency (IF) voltage-controlled oscillator (VCO) as an input. The BBPLL also performs phase-to-digital conversion with an oversampled 1-bit digital output. To further improve the demodulation performance, a dual-path injection method with extra control inversion is employed. In the proposed heterodyne PTRX, a phase offset over frequency variation is minimized in the IF mixer. As a result, the mixer-based phase detector in the proposed PTRX has lower gain variation over frequency changes even with a type-I loop, resulting in stable loop dynamics. In this paper, the frequency-tracking and phase-tracking properties of the PTRX are analyzed in view of the jitter transfer and jitter tolerance characteristics of a clock-and-data recovery (CDR) circuit for the first time. The proposed 2.4-GHz PTRX is implemented in 65-nm CMOS, consuming 3.0 mW from a 0.9-V supply. The receiver achieves a sensitivity of –83 dBm at 1 Mb/s.

This paper describes an IR-UWB transmitter with an asymmetric pulse which is featured with a steep rising edge and a slow falling edge. The proposed asymmetric pulse not only achieves a better ranging resolution but also reduces the intersymbol interference (ISI) for high data rate communication. For low data rate communication, a frequency hopping (FH) method is applied to the transmitter to enhance the link margin. The proposed UWB transmitter is designed in 65nm CMOS. Compared to the conventional triangle pulse, the ranging variation of the proposed asymmetric pulse is reduced from 120ps to 10ps over process, voltage and temperature (PVT) variations, the transmitter achieves the maximum data rate of 500Mb/s with a pulse energy of 11.5pJ/bit while meeting the UWB spectral mask.

This paper presents an improved correlation-based timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step.

This paper discusses different design aspects of the ΔΣ fractional-N bang-bang PLL (BBPLL) compared with conventional analog or digital fractional-N PLLs performing linear phase detection. Several in-band noise reduction methods without relying on a high-performance digital-to-time converter (DTC) are considered at the architecture-level. It is shown that two-stage topology, single-bit ΔΣ modulation, and phase-domain filtering methods can improve the in-band phase noise, which is different from the conventional PLLs. It is also shown that two-point modulation is superior to one-point modulation regardless of data rate when an overdamped BBPLL is employed for frequency modulation. By integrating those in-band noise reduction methods, we propose a DTC-free, calibration-free ΔΣ BBPLL architecture that achieves the inband noise of about -100dBc/Hz. Behavioral simulation results show that the in-band noise performance can be improved by nearly 40dB without having the DTC.

This paper describes a bias-current-free fractional-N hybrid phase-locked loop (HPLL) architecture that does not use a charge pump (CP) or a linear time-to-digital converter (TDC). A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection under a low supply voltage. The CP-less analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. Unlike the TDC, the flip-flop PD has negligible contribution to the in-band phase noise over different supply voltages. To mitigate ΔΣ quatization noise and PD nonlinearity effects, an FIR-filtered ΔΣ modulation is employed for fractional division. The proposed fractional-N HPLL implemented in 65-nm CMOS operates with a 0.65-V supply except a 0.9-V digital/voltage-controlled oscillator (D/VCO), consuming 1.85 mW at 1.2 GHz. The phase noise of-97 dBc/Hz at 1-MHz offset frequency and the reference spur of-76 dBc with the programmable notch filter are achieved. The measured in-band fractional spur levels vary from-37 dBc to-58 dBc. The experimental results show that the proposed architecture is promising for low-voltage clock generation and modulation systems.

This paper describes a low-voltage fractional-N hybrid phase-locked loop (HPLL) architecture that does not require current biasing. A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection. The analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. To mitigate ΔΣ quantization noise and PD nonlinearity effects, an FIR-filtered ΔΣ modulation is employed for fractional division. The proposed bias-free fractional-N HPLL is implemented in 65nm CMOS. At 1.2GHz output, the phase noise of -97dBc/Hz at 1MHz offset frequency and the reference spur of -76dBc with the programmable notch filter are measured. When 14nm FinFET technology is used, simulation results show that a 1.2GHz bias-free PLL can be designed with a 0.4V supply.

This paper presents an energy-efficient high data rate constant-envelope modulator based on a frequency-domain on-off keying (FOOK) modulation method. The fully-balanced frequency-shift keying (FSK) feature makes it possible for an integer-N PLL to perform modulation with a VCO only (1+-point modulation). By having Gaussian filtering and carrier spreading (CS) techniques, the proposed Gaussian FOOK (G-FOOK) modulation offers a fully-balanced FSK with good bandwidth efficiency and spectrum compliance. A prototype 5GHz G-FOOK modulator is designed with 65nm CMOS process to verify the proposed modulation. The modulator achieves a data rate of 50Mb/s, consuming 6.8mW from a 1V supply. Simulation results show that the proposed modulator can also achieve a data rate as high as 1Gb/s modulation.

This paper presents an effective way of noise and spur reduction in the design of ΔΣ fractional-N bang-bang phase-locked loops (BBPLLs). An integer-N BBPLL based phase domain low pass filter (PDLPF) significantly suppresses the high frequency quantization noise of the ΔΣ modulator in the feedback path, which mitigates phase folding effects of the bang-bang phase detector (BBPD). A ΔΣ fractional-N BBPLL, combined with the PDLPF for deterministic jitter (DJ) reduction, is implemented in 65nm CMOS. Simulation results show that the proposed architecture achieves an in-band noise reduction of 27dB and a spur reduction of 23dB at 5GHz output with the PDLPF enabled.

This paper presents an ultra-low voltage and ultra-low power PVT tolerant digital PLL with a semi-digital low dropout regulator (LDO). A low cost integrated temperature compensation circuit (TCC) is proposed and implemented by combining with a proposed ΔΣ LDO to reduce temperature variation of the digitally-controlled relaxation oscillator (DCRXO). A 50-to-145MHz PLL implemented in 65nm CMOS consumes a 77.3μW from a 0.6V supply at 100MHz output and achieves the phase noise of -94.3dBc/Hz at 1MHz offset frequency and the reference spur below -70dBc at 6.25MHz offset frequency. The output frequency variation of open-loop oscillator with the TCC is less than 5% across temperature variation from -20°C to 90°C.

This paper proposes a frequency-domain OOK (F-OOK) modulation transmitter with a phase rotator and a 4-stage ring digital/voltage-controlled oscillator (D/VCO) to achieve high energy, bandwidth and area efficiencies. Both frequency deviation and frequency modulation are realized in the phase domain by utilizing the phase rotator. A 9-bit phase rotator covering a phase shifting range of 180° is designed with a phase resolution of 5.625° and phase steps of 32. A hybrid 2.4GHz PLL with a 4-stage ring D/VCO generates orthogonal signals as inputs of the phase rotator. The proposed F-OOK transmitter designed in 65nm CMOS consumes 5.4mW from a 1V supply at the maximum data rate of 10Mb/s, achieving an energy efficiency of 0.54nJ/bit.

This paper describes an effective way of relaxing the nonlinearity problem of the digitally-controlled oscillator (DCO) in the two-point modulator design. A separate coarse varactor array dedicated for the high-pass modulation significantly simplifies the nonlinearity calibration of the DCO with a few-bit control. In addition, a finite-impulse response (FIR) filter is designed for the multi-bit high-pass modulation path to reduce the quantization noise, while offering a time-interleaving operation to minimize the DCO sensitivity to the coupling during switching time. A two-point modulator based on a semidigital fractional-N phase-locked loop (PLL) is implemented in 0.18μm CMOS. Simulation results show that the proposed modulator can achieve 10Mb/s GFSK/GMSK modulations with the EVM of -37dB.

This paper presents a ΔΣ modulated digital power amplifier (DPA) with a finite-impulse response (FIR) filter for wireless body area network (WBAN) applications. The proposed DPA utilizes a 1-bit second-order ΔΣ modulator to avoid nonlinearity problem of the multi-level quantization and achieve better quantization noise performance than the first-order modulator. The time-interleaving operation inherently provided by the embedded FIR filter mitigates the mismatching effect of PA cells. The proposed architecture not only improves the out-of-band noise performance but also reduces AM-AM and AM-PM distortions. The proposed ΔΣ DPA is implemented in 65nm CMOS. Simulation results show that it can achieve good out-of-band noise performance with the maximum output power of 6dBm and maximum power-added efficiency of 45%.

A ΔΣ́ all-digital delay-locked loop (ADDLL) is proposed to realize a PVT-insensitive time-to-digital converter (TDC) with enhanced linearity in an all-digital phase-locked loop (ADPLL). With the proposed TDC, poor timing resolution and nonlinearity problems are mitigated, enabling a low cost, low comparison frequency TDC design without using the advanced CMOS technology. A novel digitally-controlled delay line (DCDL) is proposed to ensure monotonous and linear mapping between a digital control word and a total time delay. A phase error compensator (PEC) is employed to calibrate periodic phase error of the proposed TDC. A 2.5GHz ADPLL is designed in 0.18μm CMOS. Simulation results show that the proposed method effectively reduces fractional spurs caused by the TDC.

This paper describes circuit techniques for robust IR-UWB receiver design for high data rate centimeter range communications. For high data rate transmission, multiple frequency bands are utilized to increase transmission power for improved link margin, in the receiver design, a multiband LNA, a fully differential squarer, and a high speed parallel interlacing integrator are developed for high speed data recovery without requiring a high performance analog-to-digital converter. In this work, a 500Mb/s 12.5mW UWB receiver is designed in 65nm CMOS, achieving energy efficiency of 25pJ/b. Simulation results show that narrowband interference from the frequency band of 802.11a wireless standard whose power spectral density is 70dB higher than target sensitivity of -65dBm can be tolerated.

A delay- and phase-locked loop (D/PLL) based clock and data recovery (CDR) system enables an independent bandwidth control for jitter transfer and jitter tolerance but requires careful loop design with PVT-sensitive analog building blocks. In this work, an all-digital DLL and a digitally-controlled type-I boosted-gain fractional-N PLL followed by an injection-locked oscillator (ILO) are designed to realize a semidigital CDR system with enhanced frequency tracking capability and low algorithm jitter generation. The proposed CDR designed in 90nm CMOS consumes 26.4mW from a 1.2V supply and occupies the active area of 1.17mm2.

This paper presents a pulse-shaped power amplifier (PSPA) design for delay line based IR-UWB transmitters. By utilizing an array of CMOS transmission gates as a dynamic bias scheme, the switched PA generates desired output pulse with negligible static current. The PSPA designed in 65nm CMOS generates UWB pulses with a -10dB bandwidth of 2.7GHz and a center frequency of 5GHz and achieves reconfigurable pulse shaping with high power efficiency. Simulation results show that the energy consumption of the PA is 3pJ/pulse with a typical current efficiency of 90% at a data rate of 200Mbps.

This paper describes the design of a low-jitter source-synchronous link transmitter macro for data rates of 9.6 Gb/s. The transmitter macro consists of 5 data channels plus 1 forwarded-clock channel. A low jitter PLL with bandwidth linearization is employed to achieve 0.66ps rms jitter. The power supply induced jitter is minimized by employing a hybrid clock distribution network which is proposed for both jitter and power consideration. To minimize the influence of PVT variation, Successive Approximation Register (SAR) sub block is implemented to accurately set the on chip impedance and the signal amplitude. A CML driver with 4 tap feed forward equalizer is implemented to compensate the channel loss. The transmitter is implemented in 65nm CMOS technology, the active chip area is 3.12 mm2.

This paper describes a ΔΣ modulation based ranging method for the IR-UWB radar system. To relax the phase resolution requirement of the delay line in the receiver, two coarse timing boundaries of the delay line are used to form a bilevel quantizer which can be the part of a 1-bit ΔΣ oversampling TDC. Also, a digital phase rotator circuit is designed to provide an unlimited phase capture range. Simulation results show that the proposed ΔΣ IR-UWB radar can achieve sub-mm ranging resolution with good matching assumed.

This paper firstly presents a CMOS voltage-controlled oscillator (VCO) which enables octa-phase triangular waveform generation. By utilizing a cascaded relaxation oscillator core followed by a pseudo injection-locked oscillator circuit, an octa-phase differential VCO with triangular waveform outputs is realized. Simulation results show that the proposed fully differential multi-phase VCO can achieve broad tuning range with programmable timing capacitors, offering <;1% phase mismatch.

A wide-tuning low-cost PLL architecture with negligible loop filter area is presented. To overcome the static phase error or reference spur problem of the conventional type-I PLL over broad frequency tuning range, a Δ-Σ DAC based real- time frequency acquisition aid method is employed in the PLL voltage domain. Different from other Δ-Σ based frequency acquisition methods mainly used for the type-II all-digital PLL (ADPLL), the proposed method provides inherent quantization noise reduction by the PLL loop filter. Simulation results verify that significant reference spur reduction as well as Δ-Σ noise reduction can be achieved with the proposed architecture.

This paper describes a practical settling time analysis of the charge-pump phase-locked loop (PLL) by considering nonlinear circuit effects on transient settling behavior; a PLL slew rate, a PFD reset delay, and a loop filter charge sharing. A transient analysis including those parameters with a refined lock-in range is given, showing that the overall settling time can be significantly affected by the nonlinear factors even with the same PLL bandwidth. Behavioral simulation results verify that the proposed analysis predicts the transient settling time more accurately than existing methods.

This paper describes a method to control the zeroes in the frequency response of hybrid finite impulse response (FIR) filter in ΣΔ fractional-N PLL for quantization noise reduction. By adjusting the current allocation in different branches of the charge pump, transfer function of the FIR filter can be customized to meet various system requirements. Simulation results shows that the proposed method effectively adds flexibility to the hybrid FIR noise filtering technique while it also helps to reduce the hardware complexity.

In this paper, a novel architecture of a fractional-Nphase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequential outputs of a ΔΣ modulator, finite impulse response (FIR) filtering with respect to modulator noise is realized in the PLL, resulting in quantization noise reduction in high frequencies. Hence, a low oversampling ratio (OSR) ΔΣ fractional-NPLL can be achieved without increasing quantization noise. Architecture comparison and simulation results are also presented.