Joey Y. Lin

dblp:04/309 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 93% Reconfigurable computing and FPGAs · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
circuit clustering
0.112006
Optimal simultaneous mapping and clustering for FPGA delay optimization · DAC 2006
Electronic design automation › physical design › timing optimization
delay optimization
0.112006
Optimal simultaneous mapping and clustering for FPGA delay optimization · DAC 2006
Electronic design automation
logic synthesis
0.112006
Optimal simultaneous mapping and clustering for FPGA delay optimization · DAC 2006
Electronic design automation › logic synthesis
technology mapping
0.112006
Optimal simultaneous mapping and clustering for FPGA delay optimization · DAC 2006
Reconfigurable computing and FPGAs
FPGA design flow
0.012006
Optimal simultaneous mapping and clustering for FPGA delay optimization · DAC 2006

Methods — techniques the papers use, named apart from their topics

technology mapping · 0.1circuit clustering · 0.1
YearPublicationVenuePosition
2006 Optimal simultaneous mapping and clustering for FPGA delay optimization
abstract
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry out these two synthesis steps sequentially. Such a two-step approach cannot guarantee that the final delay of the circuit is optimal, because the quality of clustering depends significantly on the initial mapping result. To address this problem, we develop an algorithm that performs mapping and clustering simultaneously and optimally under a widely used clustering delay model. To our knowledge, our algorithm, named SMAC (simultaneous mapping and clustering) is the first delay-optimal algorithm to generate a synthesis solution that considers a combination of both steps. Compared to a synthesis flow using state-of-the-art mapping and clustering algorithms DAOmap [7] + T-VPACK [17] ? SMAC achieves a 25% performance gain with a 22% area overhead under the clustering delay model. After placement and routing, SMAC is 12% better in performance.
Joey Y. Lin, Deming Chen, Jason Cong
DAC1
2002 A new enhanced SPFD rewiring algorithm
abstract
This paper presents an in-depth study of the theory and algorithms for the SPFD-based (Set of Pairs of Functions to be Distinguished) rewiring, and explores the flexibility in the SPFD computation. Our contributions are in the following two areas: (1) We present a theorem and a related algorithm for more precise characterization of feasible SPFD-based rewiring. Extensive experimental results show that for LUT-based FPGAs, the rewiring ability of our new algorithm is 70% higher than SPFD-based local rewiring algorithms (SPFD-LR) [19][21] and 18% higher than the recently developed SPFD-based global rewiring algorithm (SPFD-GR)[20]. (2) In order to achieve more rewiring ability on certain selected wires used in various optimizations, we study the impact of using different atomic SPFD pair assignment methods during the SPFD-based rewiring. We develop several heuristic atomic SPFD pair assignment methods for area or delay minimization and show that they lead to 10% more selected rewiring ability than the random (or arbitrary) assignment methods. When combining (1) and (2) together, we can achieve 38.1% higher general rewiring ability.
Jason Cong, Joey Y. Lin, Wangning Long
ICCAD2