As a scalable, cost-effective, and flexible solution for data-intensive systems, we are exploring active-network-storage (ANS), which is an array of ANS disk drives. The ANS drive improves flexibility by using a modular software design; that is, users can specify functions of the ANS drive by loading/unloading the corresponding modules on it. To keep the ANS drive cost-effective, users are allowed to choose whether native code modules or platform-independent Java-bytecode modules are executed on the drive. We forecast that a current high-performance embedded-processor is powerful enough to enable this modular design to be implemented and to provide a scalable, cost-effective, and flexible ANS system. We have confirmed our forecast by conducting an experiment with an ANS drive prototype with a 200 MHz embedded-processor running database sequential scanning and NFS, which are typical off-loaded functions with different characteristics. To evaluate scalability and cost-effectiveness of the ANS system, we estimated the throughput from measurements on our ANS prototype, and we compared it with the throughput that was measured on a 450 MHz Pentium II Xeon server. Our estimation indicates that the scan throughput of the ANS system increases up to 71 MB/s while that of the server saturates at 25 MB/s because of its CPU bottleneck. The NFS read/write throughputs of two ANS drives surpassed the server maximum throughputs.

The characteristics of a cluster-structure parallel computer are analyzed and evaluated on the PIM/c parallel inference machine, which consists of eight-processor shared-memory clusters communicating through a processor connected to a network. To avoid communication bottlenecks, the maximum number of processors in a cluster is limited by the ratio of communication operations to program-execution operations. Since this ratio can be as high as 30% on the PIM/c, the network receiving operations should be distributed to processors in the same cluster.

Presents new principles for online monitoring in the context of multiprocessors (especially massively parallel processors) and then focuses on the effect of the aliasing probability on the error detection process. In the proposed test architecture, concurrent testing (or online monitoring) at the system level is accomplished by enforcing the run-time testing of the data and control dependences of the algorithm currently being executed on the parallel computer. In order to help in this process, each message contains both source and destination addresses. At each message source, the sequence of destination addresses of the outgoing messages is compressed on a block basis. At the same time, at each destination, the sequence of source addresses of all incoming messages is compressed, also on a block basis. Concurrent compression of the instructions executed by the PEs is also possible. As a result of this procedure, an image of the data dependences and of the control flow of the currently running algorithm is created. This image is compared, at the end of each computational block, with a reference image created at compilation time. The main results of this work are in proposing new principles for the online system-level testing of multiprocessor systems, based on signaturing and monitoring the data dependences together with the control dependences, and in providing an analytical model and analysis for the address compression process used for monitoring the data routing process.>

This paper discusses the design concepts of a lock mechanism for a Parallel Inference Machine (the PIM/c prototype) and investigates the performance of the mechanism in detail.

Presents new principles for online monitoring in the context of multiprocessors (especially massively parallel processors) and then focuses on the effect of the aliasing probability on the error detection process. In the proposed test architecture, concurrent testing (or online monitoring) at the system level is accomplished by enforcing the run-time testing of the data and control dependences of the algorithm currently being executed on the parallel computer. In order to help in this process, each message contains both source and destination addresses. At each message source, the sequence of destination addresses of the outgoing messages is compressed on a block basis. At the same time, at each destination, the sequence of source addresses of all incoming messages is compressed, also on a block basis. Concurrent compression of the instructions executed by the PEs is also possible. As a result of this procedure, an image of the data dependences and of the control flow of the currently running algorithm is created. This image is compared, at the end of each computational block, with a reference image created at compilation time. The main results of this work are in proposing new principles for the online system-level testing of multiprocessor systems, based on signaturing and monitoring the data dependences together with the control dependences, and in providing an analytical model and analysis for the address compression process used for monitoring the data routing process. >

The bubble memory has several features such as low-cost low-power consumption, small physical size, high reliability, and non- volatility, which make it suitable for low-cost microcomputer files.