In recent years, domino logic has received much attention. But in the case of standard domino logic, only non-inverting gates are allowed. Then, clock-delayed (CD) domino logic, that realizes any logic gate, has been proposed. Moreover, the domino logic has another drawback in that it is very sensitive to noise induced by crosstalk. Therefore, we focus our attention on crosstalk faults in CD domino circuits. In order to realize an efficient fault simulation, in this paper we propose a new method of target fault reduction, considering conflicts of signal values in the circuit and dominance of faults. In addition, we introduce a faster fault simulation method, which uses only logic values without handling details of the timing events of circuits.

With the movement into deep submicron (DSM) technology and GHz clock frequencies, signal integrity problems have become important. Signal integrity problems are induced by circuit noise such as crosstalk, power supply noise. substrate noise. In this paper, we consider crosstalk in such noise and propose a new built-in self-test method for faults induced by crosstalk, called crosstalk faults.

A new Built-in Self Test (BIST) method for multiple configurable logic block (CLB) faults of SRAM-Look-Up-Table (LUT) type FPGA is reported. In this method, self test is performed concurrently for every test block containing eight CLBs. Faulty FPGA which includes up to five faulty CLBs in one test block can be detected completely even if each faulted CLB includes unlimited number of faults.

As VLSI circuits become high-speed and high-density, a crosstalk fault becomes an important problem. In a synchronous sequential circuit, since the crosstalk fault between a data line and a clock line is important, we described an algorithmic test generation technique for the fault. Some simulation results of our method for the ISCAS bench mark circuits are reported.

The continuous reduction of the device size in integrated circuits and the increase in the switching rate cause parasitic capacitances between conducting layers to become dominant and cause logic errors in the circuits. Therefore, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this class of faults. This paper presents a logic level characterization and fault model for crosstalk faults. The authors also show how a fault list of such faults can be generated from the layout data, and give an automatic test pattern generation procedure for them.>

An algorithmic test pattern generation method named ZALG* for circuits including tri-state modules that have been extensively used in recent MOS VLSI is presented. For the circuits, special attention must be paid to bus clash and memory retention in order to avoid device destruction in testing. Since ZALG* takes complete measures against bus clash and memory retention and uses a multiple-path sensitization method, like PODEM, it is a complete algorithm in the sense that all possible combinations of input values will be tried in the worst case. ZALG* is implemented by FORTRAN, and some experimental results for circuits with two to three thousand gates are reported.>