The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical design flow. In this paper we discuss two different approaches to model generation, the design flows they lend themselves to and results from the application of these model generation solutions to large customer designs.

System design, i.e. the design of board-level circuits andsystems-on-a-chip, focuses on the integration of off-the-shelf andapplication-specific VLSI components. A key aspect of systemdesign is to ensure the satisfaction of component interface timingrequirements. This is necessary for the correct exchange ofinformation among components on a system. We present amethodology for the interface timing verification and subsequenttiming-driven floorplanning of systems. We present results on theapplication of this methodology to real-world circuits.

There is a well-recognized need for accurate timing verification tools that account for the functional behavior of component interfaces, and thereby do not traverse false combinational and sequential paths. Such tools, however, are susceptible to an exponential increase in task complexity as the circuit size and functional complexity of components increase. The viability of accurate timing verifiers hinges on their ability to efficiently analyze the smallest subset of circuit behaviors, while verifying the timing characteristics of the overall space of behaviors. This paper presents theoretical results that address this issue for the timing verification of interacting FSMs.

A timing verifier that scales to verify complex sequential circuits, modeled in terms of interacting FSMs, while rejecting false sequential and combinational paths has, so far, not been developed. We present an algorithm for this purpose. The inherently modular nature of interactions among FSMs, allow a highly efficient symbolic simulation verification methodology. Experimental results illustrate this methodology's ability to scale, while providing accurate timing verification results.

Article The minimization and decomposition of interface state machines Share on Authors: Ajay J. Daga ECES Department, The University of Michigan, Ann Arbor, MI ECES Department, The University of Michigan, Ann Arbor, MIView Profile , William P. Birmingham ECES Department, The University of Michigan, Ann Arbor, MI ECES Department, The University of Michigan, Ann Arbor, MIView Profile Authors Info & Claims DAC '94: Proceedings of the 31st annual Design Automation ConferenceJune 1994 Pages 120–125https://doi.org/10.1145/196244.196301Online:06 June 1994Publication History 3citation116DownloadsMetricsTotal Citations3Total Downloads116Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

MICON is a knowledge-based system that designs small computer systems. The synthesis of a digital system may be viewed as successive design and redesign of individual subsystems. Redesign is necessary when the design of one subsystem imposes conflicting requirements on the design of another, and when a design cannot meet specifications. This paper discusses the technique used to make MICON capable of redesign. The paper discusses a dependency network used to facilitate failure correction and highlights the novel features of this scheme. An example is given.