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Dundar Dumlugol

dblp:04/4645 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 92% Parallel and multicore computing · 8%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.021987
Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › circuit simulation › relaxation-based simulation
waveform relaxation
0.011987
Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Electronic design automation › circuit simulation
switch-level simulation
0.011983
Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › circuit simulation
parallel circuit simulation
0.011987
Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Parallel and multicore computing
parallel computing
0.011987
Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Electronic design automation › timing analysis
delay modeling
0.011983
Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983

Methods — techniques the papers use, named apart from their topics

mixed-mode simulation · 0.0event-driven scheduling · 0.0dynamic feedback loop cutting · 0.0time wheel · 0.0local relaxation · 0.0event-driven simulation · 0.0
YearPublicationVenuePosition
1987 Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers
abstract
The Segmented Waveform Relaxation Method (SWRM) is a new and efficient waveform relaxation method for circuit-level simulation of large-scale digital MOS networks. SWRM is original in two aspects. 1) Dynamic feedback loop cutting and waveform event driven scheduling result in a varying simulation order of the subcircuits and, for digital synchronous circuits, lead to logically correct and accurate ground waveforms in one waveform iteration where the only approximation is due to Miller feedback over MOS capacitances (timing error being usually <5 percent). 2) Dynamic decomposition of large subcircuits at MOS transistors which are temporarily in a nonconducting state. SWRM has been implemented in the program SWAN and tested on large industrial circuits (up to 4000 transistors) with speed gains of 10 /spl gt/ 100 over SPICE2G6. A mixed-mode switch electrical implementation of SWRM together with novel acceleration methods on parallel computers will be described together with test results on real-life circuits.
Dundar Dumlugol, Patrick Odent, Johan Cockx, Hugo De Man
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1983 Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling
abstract
In this paper a new algorithm for switch level simulation is presented. The algorithm is compatible with classical time wheel mechanisms for logic simulation and therefore allows for assignable delay modeling also at the switch level. The key to this algorithm is a local relaxation method which takes care of localized bilateral effects. The algorithm is shown to be 0(n) and proven to converge to a unique solution.
Dundar Dumlugol, Hugo De Man, Piet Stevens, Guido G. Schrooten
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1