The paper presents a fast and accurate motion estimation algorithm. To obtain accurate motion vectors while minimizing computational complexity, we adjust the search range for each frame and each block to suit the motion level of the video. An appropriate search range for each frame is determined on the basis of motion vectors and prediction errors obtained for the previous frame. At each block, the search range is determined on the basis of the search range of its frame and of the motion vector values of all adjacent blocks for which those values have already been obtained. With our algorithm, since narrow search ranges are chosen for areas in which little motion occurs, computational complexity can be reduced without degrading estimation accuracy. Since wide search ranges are chosen for areas of significant motion, good video-quality encoding can be maintained. In the encoding of an SDTV size video, the addition of range adjustment results in a reduction in the computational complexity of motion estimation of roughly 65%, while maintaining the same video quality.

This paper describes a new hardware/software co-verification method for System-On-a-Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, and high verification speed, at a low cost. We describe the application of this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development. In these projects, our verification methodology was used to perform complete system verification at 0.2-1.1 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump" viewers, and debugging functions such as "step" or "break".

The paper describes an analysis-based method for optimizing the timing of decisions regarding early termination of block matching (BM) in the application of a successive similarity detection algorithm (SSDA). Although the SSDA reduces BM computational costs, making decisions to terminate BM or not consumes additional processor cycles. Here, total costs, including cycles for decisions, are formulated through use of a decision interval, processor-dependent cost factors, and a function which gives probabilities of BM termination. The optimal decision interval is derived by minimizing the cost function. Experiments on MPEG-4 video coding show the proposed method facilitates comparative evaluation of the computational costs of SSDA-based BM for various processors.

This paper describes an analysis-based method for optimizing the timing of decisions regarding early termination of block matching (BM) in the application of a successive similarity detection algorithm (SSDA). Although the SSDA reduces BM computational costs, making decisions to terminate BM or not consumes additional processor cycles. Here, total costs, including cycles for decisions, are formulated through use of a decision interval, processor-dependent cost factors, and a function which gives probabilities of BM termination. The optimal decision interval is derived by minimizing the cost function. Experiments on MPEG-4 video coding show the proposed method facilitates comparative evaluation of the computational costs of SSDA-based BM for various processors.

We have developed a new-generation, general-purpose digital signal processor (DSP) core with low power dissipation for use in third-generation (3G) mobile terminals. The DSP core employs a 4-way VLIW (very long instruction word) approach, as well as a dual-multiply-accumulate (dual-MAC) architecture with good orthogonality. It is able to perform both video and speech codec for 3G wireless communications at 384 k bit/sec with a power consumption of approximately 50 mW. This paper presents an overview of both the DSP core architecture and a DSP instruction set, and it also gives some application benchmarks.

This paper describes an efficient architecture enhancement for video codec on a new-generation, general-purpose digital signal processor (DSP) core called SPXK5 developed for handheld devices. With high performance features of SPXK5's base architecture, an MPEG-4 video codec can be implemented efficiently. In addition, only a few SIMD type instructions effectively accelerate MPEG-4 video codec implementation by 20% with only 2.5% hardware increase. By reducing cycle count, the DSP's power consumption can be reduced. Both video and speech codec for 3G mobile service at 384kbps can be realized with a power consumption of less than 50mW.

Reed-Solomon (RS) coders are used for error-control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. Traditionally, RS coders have been implemented using dedicated hardware. This paper considers software-based implementation of RS codecs. A hardware-software codesign approach is used to design the finite field datapath in a domain-specific digital signal processor (DSP) with low-energy RS codecs application in mind. These datapaths are designed to accommodate programmability with respect to the primitive polynomial as well as the field degree m. A novel heterogeneous digit-serial approach is proposed, where the heterogeneity corresponds to the use of different digit sizes in the multiply-accumulate (MAC) and degree reduction (DEGRED) subarrays. The salient feature of this digit-serial approach is that only the digit cells are implemented in hardware and the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations. Efficient scheduling strategies for digit-serial finite field multiplications are presented and applied to the design of low-energy high-performance RS codecs in software. Significant energy and energy-latency reductions can be achieved using the digit-serial datapaths, as compared with the traditional approach where a combined MAC-DEGRED (parallel multiplier) unit is used. It is concluded that for two-error-correcting RS(n, k) codes over finite field GF(2/sup 8/), datapath containing a parallel MAC unit (of digit size eight) and a DEGRED unit with digit size two (or four) leads to RS codecs with the least energy consumption and energy-latency products; with these datapath architectures and appropriate digit-serial scheduling strategies, more than 60% energy reduction and more than one-third energy-latency reduction can be achieved compared with the parallel multiplication datapath-based approach.

A fast radix-4 complex FFT implementation using 4-parallel SIMD instructions is presented. Four radix-4 butterflies are calculated in parallel at all stages by loading consecutive 4 elements into a register. At the last stage, every 4 elements is packed into a register and calculated in parallel. This regular data flow enables higher parallelism and an overhead reduction in data format conversion. The implementation result on the V830R processor, which has a 4-parallel SIMD-type multimedia instruction set, achieves practical performance quite competitive with high-end parallel DSPs. Multiply-accumulate instructions with symmetrical rounding introduced to the V830R processor are effective to maintain FFT accuracy.

This paper presents an implementation of a fast two-dimensional inverse discrete cosine transform (IDCT) with multimedia instructions for a software MPEG-2 decoder. IDCT algorithms for sparse blocks which eliminate the calculation for zero coefficients are realized by using multimedia instructions. To reduce the cycle count for IDCT, an adaptive control method for these IDCT algorithms, based on the bit rate and picture type, is proposed and its performance is described. In the implementation of a software MPEG-2 decoder, the execution time for IDCT is reduced to 10% by using MMX instructions from the original C program. Moreover, using the proposed adaptive control, it can further be reduced to 76%.

This paper presents a low-power, 32-bit RISC microprocessor with a 64-bit "single-instruction multiple-data" multimedia coprocessor, V830R/AV, and its MPEG-2 video decoding performance. This coprocessor basically performs multimedia-oriented four 16-bit operations every clock, such as multiply-accumulate with symmetric rounding and saturation, and accelerates computationally intensive procedures of the video decoding; an 8/spl times/8 IDCT is performed in 201 clocks. The processor employs the Concurrent Rambus DRAM interface, and facilities for controlling cache behavior explicitly by software to speed up enormous memory accesses necessary for motion compensation. The 200-MHz V830R/AV processor with the 600-Mbyte/s Concurrent Rambus DRAMs decodes MPEG-2 MP@ML video in real-time (30 frames/s).

This paper describes an H.263 video codec implementation based on a low power consumption general purpose DSP. Fast algorithms, such as a fast motion estimation algorithm and a low complexity noise reduction filter, are proposed to implement the video codec on a single DSP chip maintaining sufficient picture quality. By using a 50 MIPS, 100 mW DSP, the developed codec encodes and decodes 7.5 QCIF frames per second, which is sufficient performance for low bit-rate video compression, typically below 64 kbps.

Reed-Solomon (RS) codecs are used for error control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. This paper considers software-based implementation of RS codecs where special instructions are assumed to be used to program finite field multiplication datapaths inside a domain-specific programmable digital-signal processor (DS-PDSP). A heterogeneous digit-serial approach is presented, where the heterogeneity corresponds to the use of different digit-sizes in the multiply-accumulate (MAC for polynomial multiplication) and degree reduction (DEGRED for polynomial module operation) subarrays. The salient feature of this digit-serial approach is that only the digit-cells are implemented in hardware, the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations in RS encoders and decoders. It is concluded that, for 2-error-correcting RS(n,k) codec implementations over finite field GF(2/sup 8/), a parallel MAC unit (of digit-size 8) and a DEGRED unit with digit-size 2 is the best datapath, with respect to least energy consumption and energy-delay products. With this datapath architecture and appropriate digit-serial scheduling strategies, more than 60% energy reduction and more than 1/3 energy delay reduction can be achieved compared with the parallel multiplication datapath based approach.

This paper describes large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. General-purpose microprocessors for workstations and personal computers (PCs) use special built-in hardware for multimedia processing, so the multimedia processors described include these modified general-purpose microprocessors. After reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PCs, embedded RISCs, low-power digital signal processors (DSPs), which are mainly used for mobile communications devices, and media processors that support PCs for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSPs. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including "system on a chip," and their applications are also discussed.

Real-time operation of signal processing applications on multimedia RISC processors is often limited by high instruction cache miss rates of direct-mapped caches. In this paper, a heuristic approach is presented which reduces high instruction cache miss rates in direct-mapped caches by code positioning. The proposed algorithm rearranges functions in memory based on trace data so as to minimize cache line conflicts. Moreover, a new method to extract potential cache misses from trace data is introduced which enables accurate cache behavior analysis and greatly enhances code positioning efficiency. Application of code positioning to an MPEG-1 video decoder implementation on the V830 multimedia RISC processor reduced instruction cache refill cycles by 66-98%. The proposed code positioning algorithm does not require hardware modifications; it can easily be integrated in an object linker to automate the optimization process.

Motion estimation (ME) has widely been used in video codecs, such as MPEG and ITU-T H.261, to remove interframe redundancy. This paper describes a fast full-search ME method for programmable processors with a multiply-accumulator. It is based on the block matching method that evaluates block mismatch by the mean square error. In order to reduce the computational load of the ME, a fast two-dimensional FIR filtering algorithm is applied, and the redundancy of the overlapped area computation among the reference blocks is eliminated. When the block size is 16/spl times/16 and the number of reference blocks in the search window is 32/spl times/32, this method reduces the computational load to 22.6% without degrading the motion tracking capability.

A building block for a scalable signal processor array is developed with a general-purpose DSP and a message routing LSI. Each DSP can be connected by multiple routing LSIs forming a point-to-point message-passing network with data packet communication. Low network latency is obtained by cut-through routing technique with sufficient communication bandwidth. The employment of an on-chip routing table allows regular as well as irregular topologies with complex routing techniques such as broad/multi-casting and dynamic routing. The combination of DSPs ( mu PD77240), a flexible message-passing network and an optional application-specific I/O interface makes the processor array suitable for a wide range of high speed signal processing applications such as adaptive array processing and 3-D vision processing.>

A software design system for asynchronous multirate/multitask processing is developed for a programmable digital signal processor, the NEC77240. A new scheduling method which combines static and dynamic scheduling is proposed. This avoids runtime overheads due to interrupts in asynchronous multirate system design for digital signal processors (DSPs). The processing delay is avoided by introducing deadline scheduling in the static scheduling. In this system, a block diagram description language is extended to describe a asynchronous multitask processing. By using this scheduling method, asynchronous multirate processing such as arbitrary sampling ratio rate conversion, asynchronous interface and multimedia applications can be efficiently realized by programmable DSPs.>

A simple programming system has been developed for a 32 bit floating point signal processor µPD77230 [1]. The system is based on the blockdiagram language concept [2][3], in which many signal processing systems can be realized by combinations of primitive functional blocks. A wide dynamic range and high precision processing obtained from a 32 bit floating point arithmetic make this approach possible, without complex scaling or limit cycle oscillation problems encountered in a fixed point processing. About 100 primitive programs are implemented on a mask ROM sample chip. They can be used as library programs accessed by a main program stored in an external instruction memory. In addition, library programs can also be carried out by a command sequence stored in an internal memory under a special control program in the chip. This approach enables using µPD77230 processing capability without knowledge concerning its architecture or a set of microinstructions. In this paper, a DTMF receiver and an ADPCM coder, realized by this system, are shown as examples.

A CMOS single chip signal processor, which has 32-bit floating point arithmetic units and large capacity on-chip memories, has been developed. The processor, having a floating point parallel multiplier, a floating point accumulator, two 512- word data RAMs, a 1024-word data ROM and a 2048- word program ROM, is implemented within a 15.4 × 8.4 mm chip area, containing 370,000 elements. As the processor is designed to perform highly accurate multiply-accumulate operations for digital filtering and to attain complex addressing capability for FFT computation, this processor can execute FIR computation at the 150 nsec per tap rate, as well as achieve 1024 point complex FFT computation in 12.3 msec.

An LSI ADPCM codec, which is based on the CCITT standard 32 kbps algorithm, has been developed. The LSI chip has been designed as a software controllable signal processor whose architecture is optimized for the CCITT algorithm. A reconfigurable pipeline multiplier-normalizer-accumulator circuit is effectively utilized for realizing complex ADPCM specifications. The LSI chip, implemented by 2.5 µ CMOS technology, dissipates only 90 milliwatts of power.