Forward estimates of area and delay facilitate effective decision-making when searching the solution space of digital designs. Current estimation techniques focus on modeling the layout result and fail to deliver timely or accurate estimates. This paper presents a novel approach to deriving these area and delay estimates at the RTL level by modeling the layout tool, rather than the layout result. This approach uses machine learning techniques to capture the relationships between general design features (i.e., topology, connectivity, common input, and common output) and layout concepts (i.e., relative placement). Experiments illustrate the formulation of the training set for machine learning in this domain, and also show how we can derive different tool models. Finally, they show how we can use the resultant model to derive forward estimates of area and delay in real-world designs.

This paper presents an overview of a distributed embedded system design assistant called Systems Engineers Workbench (SEW 2.0). SEW 2.0 uses a suite of design frameworks, with supporting representations, to structure the inherent complexity. A set of design assist operatives further improves the ability of the designer to explore the domain space while evaluating performance/resource tradeoffs.

Abstract| This paper presents a novel approach to deriving area and delay estimates for high level synthesis using machine learning techniques to model layout tools.This approach captures the relationships between general design features (e.g., topology, connectivity, common input, and common output) and layout concepts (e.g., relative placement).Experimentation illustrates the eectiveness of this approach for a variety of real-world designs.

The knowledge representation and reasoning strategies in an automatic program synthesis architecture called ELF are described. ELF synthesizes computer-aided design (CAD) tools that automatically route wires in VLSI circuits. The design space ELF confronts, requires it to understand various physical technologies, to select an appropriate procedure-level decomposition, to choose algorithms and data structures, to manage any interdependencies, and to generate efficient code. ELF manages the design space using a variety of knowledge sources, including domain-specific knowledge. The manner in which knowledge is used determines the representation method of choice. The effectiveness of these ideas is illustrated via a tour through the synthesis steps for a specific routing tool, and a brief discussion of the performance of the resulting synthetic router as measured against an industrial tool.>

An automatic synthesis system for real-time software is described. It is argued that the presence of strict operation requirements, such as task-level timing constraints and compiler and target platform constraints, guides synthesis. An automatic software synthesis system, RT-SYN, integrates platform characteristics to synthesize real-time software which meets hard deadline design requirements. The RT-SYN system has four key features. First, a visual graphical user interface captures application algorithms without implementation specifications. Second, RT-SYN analyzes the task-level data and control flows to produce worst-case timing and space predictions. Third, RT-SYN uses these predictions to choose abstract representations of data structure and algorithm implementations to meet required timing and space constraints. Fourth, RT-SYN synthesizes C code from the selected implementations. Experimental results are given to illustrate these four features.>

The application of program synthesis techniques to the generation of technology-sensitive VLSI physical design tools is described. The architecture and implementation of a particular software generator (called ELF) targeted at the generation of maze routing software is described. ELF strives to meet the demands of the target technology by automatically generating maze router implementations to match the application requirements. ELF has three key features. First, a very high level language, lacking data structure implementation specifications, is used to describe algorithm design styles. Second, application-specific expertise about routing and application independent code synthesis techniques are used to guide search among alternative design styles for algorithms and data structures. Third, code generation is used to transform the resulting abstract descriptions of selected algorithms and data structures into final, executable code. Code generation is an incremental, stepwise refinement process. Experimental results are presented covering several correct. fully functional routers synthesized by ELF from varying high-level specifications. Results from synthetic and industrial benchmarks are examined to illustrate ELF's capabilities.>

This paper describes how program synthesis techniques can be applied to the generation of technology-sensitive VLSI design tools. We present results from ELF, a synthesis tool for wire-routing software. The ELF synthesis architecture has three key features. First, a very high level language, lacking data structure implementation specifications is used to describe algorithm design styles. Second, routing domain knowledge and generic program synthesis knowledge are used to guide search among candidate design styles for all necessary component algorithms, and to deduce compatible data structure implementations for these components. Third, code generation is used to transform the resulting abstract descriptions of selected algorithms and data structures into final, executable code. Code generation is an incremental, stepwise refinement process. We present experimental results from several correct, fully-functional routers synthesized by ELF from varying high-level specifications.