In this work, a rapid method is developed for predicting device-level temperature shifts in electronic and photonic integrated circuits. The method models the most dominant thermal interactions through resistive star networks. The resistance values are obtained through interpolation of data acquired by a finite element method solver or experimental characterizations and can be used to predict all device temperatures. Simulations using COMSOL and measurements of a silicon IC have verified the key assumptions of the method. After calibrating the method with experimentally obtained thermal reference data, thermal estimations have been shown to be as close as 8.1% to measurements. Compared to a finite element based approach, the method can allow for a 1 to 2 orders of magnitude speed-up, which the user may choose to trade off for a higher estimation accuracy.

An ultra-low power, energy efficient, and versatile resistive sensor interface for energy constrained internet-of-things applications is presented. The sensor interface includes an efficiently duty-cycled current digital-to-analog converter (I-DAC) and an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), which enables a fully-dynamic operation. A fast start-up circuit is used in the duty-cycled I-DAC to speed up the start-up procedure and to minimize the energy consumption. A system-level correlated double sampling (CDS) technique is employed to suppress ADC offset and 1/$f$noise. To tackle the limited robustness against supply and temperature variations observed in a previous implementation of the sensor interface, a system-level ratiometric measurement (SRM) approach is employed in an updated design, which is described here in detail. The chip is fabricated in 65nm CMOS technology. Thanks to the all-dynamic nature, measurement rates from 0.1S/s to 12.5kS/s can be supported with an inherent scaling of power over 3 orders of magnitude. A reported lowest power consumption of 0.32nW is achieved at 0.1S/s. Adaptable resolution with efficient scaling of power can also be achieved by adjusting sensor interface settings and/or using oversampling and averaging. The achieved figure-of-merit (FoM), which ranges from 98 to 552fJ/conv-step is also the lowest among prior designs. Thanks to the SRM approach, only 3.6%/V and 21ppm/$^\circ \text{C}$supply and temperature sensitivity are obtained, respectively.

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates 0.43 μJ and 0.82 μJ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and 0.56 μW, respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates 1.25 μJ per measurement, achieving a resolution of 18.7 mm at 0.55 m.

High Performance Wireless Sensor Networks (HP-WSN) for critical, low latency applications such as traffic control, industrial process control, smart structures and smart vehicles has been a fast-growing field. Nevertheless, efforts towards new systems and circuit architectures to enable real-time, predictable and reliable HP-WSN have been limited, specially for reliable, low latency wireless links. This paper presents for the first time, to authors' knowledge, a low power, wideband, large delay, tunable, compact, CMOS-scalable and frequency-independent true time delay cell that enables wideband beamforming on HP-WSN. This new architecture, inspired on bucket brigade devices and N-path structure, is especially well suitable for sub-3 GHz ISM bands, where most of WSN transceivers work. Post-layout simulations of a circuit demonstrator has shown a continuous time delay between 100 - 1000 ps with 0.5% delay variation over 0 - 3 GHz band. The layout area is only 0.025 mm2and it consumes 10 - 19 mW, including buffers. It has also established a record of delay-per-area density of 40000 ps/mm2.

The sampling nature of the phase-frequency detector (PFD) degrades the stability of the charge-pump phase-locked loop (CPPLL). This paper analyzes the effect of the PFD sampling on the CPPLL stability by using z-transform. The PFD is modeled as a zero-order hold to perform the z-domain analysis. The stability boundary predicted by the analysis is accurate and verified by simulations using Cadence Spectre. In addition, a physical interpretation of how sampling destabilizes an otherwise stable continuous feedback system is provided in time domain, which brings valuable insight into the operation of sampled feedback systems like CPPLL.

This paper presents a quadrature voltage controlled oscillator (QVCO) with the delay-locked loop (DLL) for ultra wideband (UWB) application. A new architecture of delay-locked loop is presented to achieve low power consumption and low-noise operation. A system analysis of delay locked loop based QVCO is discussed including the transfer function and the stability. Also, this DLL architecture is implemented in a 40-nm CMOS technology. From the simulated result, this design achieves 40% delay range from 6-9 GHz, with -149.1 dBc/Hz phase noise at 100 MHz frequency offset. The power consumption is 11 mW, and the phase accuracy is less than 5°.

This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

In this paper, a new envelope detector design in a 40nm CMOS technology is presented. The design employs quadrature signal generation and 2ndharmonic cancellation to reduce output ripple while achieving high detection speed at the same time. The envelope detector operates from 500MHz to 6GHz with a detection speed of 250 MHz. It achieves less than 2% ripple, 0.64 ns delay and consumes 76.9 uW. With the achieved results, it is suitable for use in a nonlinear interference suppression receiver, enabling more than 25 dB of suppression.

This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

The Phoenix1project aims to develop a new approach to explore unknown environments, based on multiple measurement campaigns carried out by extremely tiny devices, called agents, that gather data through multiple sensors. These low power and low resource agents are configured specifically for each measurement campaign to achieve the exploration goal in the smallest number of iterations. Thus, the main design challenge is to build agents as much reconfigurable as possible. This paper introduces the Phoenix project in more details, and presents first developments in the agent design.

A new wideband beam steering architecture for a receiver and transmitter is proposed. In this new interpolation based beam steering architecture (IBA), the number of true time delays can be dramatically reduced to 3 for a 2-dimensionaI array and 2 for a linear array independent of the number of array elements. While in conventional phased arrays, the number of phase shifters or time delays equals the number of antenna elements. This is achieved by representing individual antenna signals through a weighted sum of base vectors. In this paper, the system level implementation of the interpolation based beam steering architecture for the transmitter and receiver is presented. Also, trade-offs between number of time delays, array factor and the bandwidth of an N-element antenna array are discussed. The new architecture is expected to be relevant for the large beam steering arrays in 5G and beyond 5G wideband communication systems By using this method, the area, loss and complexity of a beam steering system can be reduced.

This paper presents a scalable baseband phase shifter implemented in a 40-nm CMOS technology for phased array applications. The baseband phase shifter makes use of the quadrature signals available from the I/Q mixers. By using a resistor chain at the load of the mixer, uniform levels of I and Q signals can be selected by means of gm-cells that can be enabled individually for realizing different phase and amplitude combinations. The proposed phase shifter architecture is scalable in resolution without increasing power consumption. The whole circuit provides 6.6 dB conversion gain, with a total power consumption of 14.7 mW. It achieves in total 225 constellation points for phase and amplitude tuning. It is suitable for accurate beamforming in phased arrays.

In this paper the architecture and performance of a co-integrated 60 GHz on-chip wireless energy harvester and ultra-low power (ULP) radio in 65-nm CMOS are discussed. Integration of an on-chip antenna with wireless power receiver and wireless data transfer module is the crucial next step to achieve compact and high efficiency fully-integrated monolithic wireless sensor nodes. A single-pole-single-throw 60 GHz RF switch is proposed and simulated to decouple the power harvesting and data transfer module. The designed on-chip RF switch has -2 dB insertion loss in EM simulations, and achieves -18 dB isolation between the energy harvesting module and the data transfer module. A single on-chip monopole antenna for power reception and data transfer is proposed with an adapted layout to reduce power coupling to undesired substrate modes. The simulated antenna shows a gain of -1.68 dBi. The power harvesting performance of the co-integrated antenna, switch and Dickson type multistage rectifier is simulated and leads to a DC output voltage of 1.2 V for -5 dBm input power at 60 GHz. With 15 dBm power transmitted to the tag at 30 GHz, the output voltage is 1.14V in the measurement. This paper is the first to demonstrate the 30 GHz mm-wave wireless energy harvesting with fully on-chip wireless energy receiver.

Monolithic wireless sensors with integrated antenna, on-chip transceiving, sensing and energy scavenging are low-cost and robust, thus very suitable for mass production and deployment. The design of such a sensor node requires a proper architecture with careful trade-offs and joint considerations over different building blocks. In this paper, we focus on the energy scavenging and receiver part of such a sensor node. A radio-triggered receiver architecture is proposed to achieve the extreme low energy budget. Energy/power models for different building blocks are developed that show the tradeoffs between available energy and sensor performance. A system-level analysis identifies the 60GHz mm-wave band is suitable for such applications. Moreover, a design example of receiver front-end in 65nm CMOS technology is presented to demonstrate the potential performance of the proposed architecture.

This paper presents the design of a 60-GHz rectenna with an on-chip antenna and rectifier in 65nm CMOS technology. The rectenna is often the bottleneck in realizing a fully-integrated monolithic wireless sensor tag. In this paper, problems of the mm-wave rectifier are discussed, and the self-threshold voltage modulation method is proposed for better sensitivity and efficiency. Based on this discussion, the design of a 60 GHz rectenna is provided. The designed on-chip antenna has 2 dBi gain at 60 GHz. The designed rectifier reaches 4.4% efficiency with 7 dBm input power with a 1.5 kΩ load in simulation.

RF energy scavenging enables batteryless operation of wireless sensors. In particular, a system with a central controller that transfers wireless energy to and exchanges information with RF energy scavenging sensors is very suitable for a wide range of applications. State-of-the-art analysis of RF energy scavenging is mostly based on RF-DC rectifier models operating with relatively high input power to achieve high rectification efficiency. However, to enable larger distance between the central controller and sensors and/or to increase the operating frequencies, which can lead to small and low-cost smart dust like sensors, a good model describing the RF-DC rectification with low input power is needed to aid system design and optimization. In this paper, we develop such a model. Using the model, we derive closed-form solutions for the equilibrium voltage and the input resistance of the rectifier. We further propose a quasi-static model to describe the dynamic charging of the capacitor in the rectifier. A comparison with circuit simulations using Cadence Virtuoso Spectre circuit simulator shows good match between our model and the circuit simulation.

In the future dense 60 GHz wireless environments, co-channel interference (CCI) is a potential problem that degrades the link quality. In this paper, a genetic algorithm (GA) assisted analog adaptive array is proposed for 60 GHz indoor applications to mitigate the CCI. The GA optimizes the weights on each receiver path to attenuate CCI from different directions and improve signal-to-interference-plus-noise ratio (SINR) with robustness. We make two further improvements for better spatial re-use. First, we take into account the trade-off between array gain at the desired direction and interference suppression by proposing adaptivity on the weights control in GA. By adaptively increasing phase perturbation, near-optimum SINR can be achieved for different interference situations. Secondly, in some cases, the link requires less receiver paths than available, e.g. for line-of-sight links. So instead of using fixed antennas, we further propose antenna selection in the GA. A further improvement on spatial re-use can be achieved compared to arrays with fixed uniform spacing.

A 2.4 GHz energy harvester for co-integration into a low-power transceiver (TRx) operating at the same frequency is presented. An RF switch decouples the harvester from the TRx and keeps the performance degradation of the TRx low, i.e. 0.2 dB reduced output power in Tx-mode and 0.4 dB reduced sensitivity in Rx-mode. In order to enable the harvester to operate without a DC power supply, an RF switch is used that is passively turned on. The circuit is implemented in a 130 nm CMOS process, and requires a minimum input RF power of -10 dBm. Based on post-layout simulation results the proposed energy harvester achieves a peak efficiency of 22.7% at an input power level of -3 dBm.

In multimode transceivers, the transmitter for one communication standard may induce a large interferer in the receiver for another standard. To linearly suppress this interferer, which can be several orders of magnitude larger than the desired received signal, the receiver should have a very large linear dynamic range, resulting in excessive power consumption. Many of potential interferers have a constant modulus modulation. Baier and Friederichs introduced a tuneable nonlinear circuit which can suppress a constant modulus interferer without excessive power consumption. Since an open- loop tuning method is used, the worst- case interference suppression was strongly limited by inaccuracy of circuit components. To alleviate this limitation, we propose a closed- loop tuning method that exploits the locally available interference as side information. Our analysis shows that the proposed method can strongly suppress the interferer while a symbol error rate performance close to that of an exactly linear receiver is achieved. Simulation results for a practical scenario confirm this analysis, and promise much smaller power consumption than for linear interference suppression approaches.

Reduction of the power consumption of analog circuits used in RF receivers, leads to decreased linearity. Digital algorithms can be used in the receiver to compensate for the distortion components that are created due to this. This leads to a trade-off between power consumption in the analog domain and digital domain. Most research concerning this topic concentrates on signal processing, and uses a polynomial to model the nonlinear effects observed in these circuits. Often memory effects are not taken into account, and the polynomials used are only able to model weakly nonlinear behavior. In this paper the behavior of RF circuits is analyzed leading to a look-up table model, which is able to compensate strongly nonlinear circuits including memory effects. To validate the discussed model, measurements are performed on a low noise amplifier.

Maximizing the battery life time of mobile devices and sensor nodes increasingly becomes a challenge, and receiver power consumption tends to become more problematic than delivering adequate transmit power. We address the challenge of achieving the highest possible throughput per Watt of receiver circuit power. Our results show that optimum and adaptive tuning of the front-end parameters of the receiver can result in substantial power savings, compared to the common practice of a design for worst case conditions. We obtain a closed form solution for maximum throughput and the corresponding optimal overall system specifications. We confirm that handling the interference from nearby channels has a large influence, and our analysis concludes that adaptive control of the IP3 performance has an overarching impact. We further describe how the adaptive overall system settings can be translated into optimum gain and IP3 specifications of each of the individual stages that form the receiver cascade, considering both the accumulation of circuit noise and distortion products. The example of a WLAN system is elaborated to illustrate our method.

This paper presents an Equivalent-Figure-of-Merit (EFOM) for designing and evaluating a wireless system towards low power and high performance. Relevant factors like delay, minimum latency, overhead length of a package, package length, data rate, bit-error-rate (BER), pre-receiving time of the receiver, average duty cycle and electronics performance factor are synthesized within a unique model. Comparing to other FOMs like energy per bit Ebit, this EFOM is able to rank the overall performance of a wireless network concerning the information not only power efficiency but also about communication quality (speed, BER, wake-up time, etc.), communication effectiveness and user's satisfaction. Applying this model to the system design, a 60 GHz self-demodulating receiver is designed and optimized, which obtains high-speed versatile performance in a low-traffic wireless network with better power efficiency comparing to other low-power wireless interface, e.g. Bluetooth and so on.

According to the well-known Friis equation the available power gain should be maximized to reduce the overall noise figure. Therefore, in receivers where an LNA is not present or its gain is low, the available power gain of the passive mixer is of interest. However, only the voltage gain is presented in many papers. In this paper an analytical model is presented for the power gain, voltage gain and input and output impedance of a passive mixer. The model is obtained using time-domain analysis since the mixer is periodically time variant. The validity of the models is checked using CMOS 90 nm transistor simulations.

In many wireless systems, the energy consumed by the receiver is significantly larger than the energy consumed by transmitter, possibly even by orders of magnitudes. This paper derives an analytical solution to maximize the throughput per unit of available receiver circuit power. Adaptive control of the IP3, to handle the time-varying adjacent channel interference level, can substantially improve the power efficiency, compared to the common practice of design for worst case. There appears to be an optimum throughput at a specific (non zero) power consumption level. For large SNR, the optimal throughput per Joule of receiver circuit power occurs for a modulation rate of 2.3 bits/s/Hz, irrespective of interference power level. If the receiver has less power available than the optimum setting requires, a duty cycling scheme can still achieve optimum operation.

In this paper analytical models of the energy consumption are presented which uses a real world radio model with two different low power modes. This model is used to compare energy consumption of different MAC protocols. The MAC protocols used for the comparison are chosen with sensor networks is mind. The energy consumption of the nodes in a sensor network needs to be minimized to maximize the lifetime of the network. Emphasis is placed on MAC protocols, since they have a big influence on the energy consumption. One of the MAC protocols uses a low power Wake Up Receiver (WURx) which is used to decrease the total energy dissipation. The WURx MAC protocol is compared with two other low power MAC protocols, namely the asynchronous X-MAC and synchronous TDMA protocol. The obtained model is used to derive the WURx power budget. The response time of the nodes is used as the main design requirement and the important application parameters are given that determine the WURx power budget.

We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RF. The measured data show good agreement with the simulation results.

This paper discusses optimizations for the power dissipation of RF front ends in portable wireless devices. A breakthrough in power dissipation can be achieved by simultaneously optimizing the antenna interface, circuits, and IC technology of such devices. A model that predicts the minimum power dissipation of a front end for both short-range and long-range connections will be introduced. Using these models, the impact of the antenna interface on the power dissipation will be assessed. Using two antennas with equal gain combining, a typical power dissipation reduction of 2.5 to 30 times can be achieved. Using high-impedance circuits for short-range systems in combination with silicon-on-anything technology, a further reduction of power dissipation by up to one order of magnitude can be realized.

EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOORIST) and a database (DATABIST). EXIST contains several unique features including: editing while in simulation, manual and automated hierarchical floorplan optimization, and user-friendly interface based on the model-view controller paradigm of Smalltalk. These features make EXIST a promising environment for exploration of alternative VLSI architectures, such as RISC (reduced instruction-set computer) controllers.>