The effect of three I/O controller architectures on schedulable utilization, which is the highest attainable resource utilization at or below which all deadlines can be guaranteed, is examined. FIFO (first-in-first-out) request queuing, priority queuing, and priority queuing with preemptable service are simulated for a range of CPU computation to I/O traffic ratios. The results show that, for I/O-bound task sets and zero preemption costs, priority queuing with preemptable service can provide a level of schedulable utilization 35% higher than that attainable with FIFO queuing, and 20% higher than priority queuing and nonpreemptable service. Although the potential gain for priority queuing with preemptable service is large, further simulations that incorporate a time penalty for each preemption show that the gain is very sensitive to preemption cost. With preemption cost represented as a ratio of preemption time to the minimum-task period, the level of schedulable utilization for priority queuing with preemptable service degrades to that of priority queuing with nonpreemptible service, for a preemption cost ratio of 0.04. A high-level design of a preemptable I/O controller is described and the issues determining preemption cost are detailed, along with techniques for its minimization.>

Real-time scheduling algorithms that provide responsive aperiodic service in the presence of hard real-time periodic tasks require the creation of a high-priority periodic server task for servicing aperiodic requests. The authors describe the extended priority exchange algorithm, which can provide better aperiodic response than previous aperiodic service algorithms, particularly for cases where the worst-case periodic load is high and little or no utilization is left for a server task. The extended-priority-exchange (EPE) algorithm attains better aperiodic responsiveness by exploiting unused time allocated to periodic tasks for aperiodic service. The average aperiodic response times for the EPE algorithm and four other aperiodic service algorithms (background, polling, deferrable server, and priority exchange) are compared for a range of periodic and aperiodic loads. Simulation results show that for a difference between the average and worst-case periodic load of only 12.5%, the EPE algorithm provides significantly better response times for aperiodic tasks.>

This paper summarizes results from recent experiments which quantify the performance effects of multiple register sets on computer architectures 1.These experiments started with the simulation of procedure-intensive benchmarks on three different computer architectures which had various register set schemes added to them.The results from these simulations were dramatic, yet they were difficult to interpret since many interacting factors were involved.This led to a more focussed study to characterize the parameter passing and procedure context switching costs of various register set schemes.The basic hypothesis behind this work, that the performance gains from multiple register sets are independent of instruction set complexity, is supported by the results.Also of interest is the perspective this study gives on the interactions between parameter passing, procedure state saving, and machine architecture.