Technology scaling and supply voltage reduction make sequential circuits around clock edges increasingly vulnerable to single-event transients (SETs). This work analyzes the sensitive regions of a dual interlocked storage cell (DICE)-based flip-flop (DICEFF) in a 15 nm FinFET process and reveals the correlation between critical charge distribution and SET pulse characteristics. A lightweight fault-tolerant scheme is proposed that integrates delay elements (DEs) with the self-recovery capability of DICE to temporally desynchronize SET pulse arrivals and facilitate self-correction through temporal misalignment. Furthermore, a visualization method based on critical charge distribution is presented to delineate SET tolerance boundaries. HSPICE simulations demonstrate that the proposed method is robust against PVT variations, improving the average critical charge by up to$1.7\times $over the baseline and reducing the risk window by 47%, while maintaining comparable delay and power efficiency.

In recent years, the probability of soft error occurrence has increased due to the miniaturization of semiconductor devices and reduced operating voltages. FPGAs (Field Programmable Gate Arrays) enable designers to program circuit configurations after manufacturing and have flexibility and high power consumption performance. Thus, FPGAs are used for various purposes. This study has presented a redundant FPGA cluster system with error correction capability and archives more efficient use of devices by switching between TMR and DMR according to the situation. The probability of not correctable errors increases by 1.67, but parallel computation allows for twice as fast computation. We implemented a high-level synthesized circuit and applied the proposed method to an FPGA cluster. This experimentation with the implemented system verified that the proposed system’s reconfiguration from DMR to TMR worked correctly.

This paper has presented an error-tolerant approach to deep neural network (DNN) inference accelerated with field-programmable gate arrays (FPGAs) against Stuck-at Faults. We achieved a recognition rate of 99.7% for the error-free case by eliminating outliers using a threshold calculated from the median and deviation for the parameters and computing them as 0.

This paper presents a new write latency reduction scheme for a Phase Change Memory (PCM) made of Multi-Level Cells (MLCs). This scheme improves over an existing scheme found in the technical literature and known as CABS. The proposed scheme is based on the utilization of a new coding arrangement for the selection of candidate codewords. The code relies on the two-step feature found in the write operation of a MLC PCM and avoids the symbol that incurs in the largest latency at a higher rate than CABS. A detailed simulation based evaluation and comparison are also pursued; the proposed scheme accomplishes improvements in write latency (for parallel writing) as well as coding rate (16/17 for the proposed scheme versus 16/18 for CABS for 16 symbols or 32-bit word). As the proposed scheme utilizes novel selection criteria for the candidates, the design of the required circuitry (encoder and decoder) has also been changed with respect to CABS; in terms of hardware, the areas of the encoder and decoder for the proposed scheme are reduced by 73 and 56 percent respectively compared with CABS.

Many systems have critical bits which must be decoded at high speeds; for example, flags to mark the start and end of a packet (SOP and EOP) determine subsequent actions, thus they must be decoded first and fast. This paper presents a new single and adjacent error correction (SAEC) code; as the codewords have critical bits, the proposed code accomplishes a fast decoding for them. The proposed code is a systematic code and permits shortening. This is accomplished by reducing the information bits, so that columns in the H matrix can be eliminated, while still keeping both the SAEC capability and the systematic feature, but for an odd number of information bits, an adjustment step in critical bits is required. It is shown that the check bit length of the proposed code is nearly the same as that of the traditional (optimal) Hamming SAEC code. The decoder of the proposed SAEC code is compared with the traditional Hamming SAEC code; this comparison shows that on average, the delay time for the critical bits is reduced by 6 percent compared with the traditional Hamming SAEC code (so at the same reduction level as a previous SEC scheme for fast decoding of critical bits over a traditional SEC code). Also, the area and power consumption of the proposed decoder show average reductions of 12 percent and 10 percent compared with the decoder of a traditional SAEC code.

This paper addresses at coding-level the challenge of providing a write latency reduction with either endurance enhancement and/or error control for a phase change memory (PCM) system. Endurance enhancement is assessed by considering the skewed write operations among the cells of a PCM system, i.e., when the maximal number of cell write operations is smaller, then the coding scheme achieves a better endurance, because the access of the memory cells in the system is more uniform (less skewed). As a first contribution, simulation of different industrial benchmarks shows that for realistic code rates (such as at k/n = 4/5), the write time speed-up (WTS) code not only reduces the write latency as previously reported, but it also reduces the skewed (nonuniform) use of PCM cells. This occurs because the WTS code uses as many cells as possible to reduce the number of SET operations in a PCM cell. Then, error control is considered. An encoding/decoding scheme that is compatible with a write latency reduction code, such as WTS, is proposed. For compatibility with the write latency reduction, a partition-based error control code (ECC) must be used. Also, the ECCs employed in these cases are systematic. The original information always appears in the codeword without modification. Evaluation by simulation shows that also in this case, the maximal number of write operations of the WTS code is smaller.

Center for Environmental Remote Sensing, Chiba University develops L Band circularly polarized synthetic aperture radar (SAR) sensor for microsatellite (150 kg class). This paper explains the project, specification, antenna deployment, RF system, and experiment of circularly polarized SAR in anechoic chamber. In the future, this sensor will be employed to monitor global land deformation.

A hybrid memory cell usually consists of a Static Random Access Memory (SRAM) and an embedded Dynamic Random Access Memory (eDRAM) cell; hybrid cells are particularly suitable for cache design. A novel hybrid cache memory scheme (that has also non-volatile elements) is initially proposed; this scheme is assessed through extensive simulation to show significant improvements in performance. Different design implementations of the hybrid cache are then proposed at architectural level and different features (such as the memory hit rate, the Instruction Per Cycle (IPC) access pattern and the memory cell access time) are also simulated at this level using benchmarks to show the advantages of the proposed scheme for use as an hybrid cache.

This manuscript proposes three classes of codes for error correction in a storage system in which the memory cells do not have the same number of levels, i.e., a multiscale storage. The proposed codes are single multiscale-symbol error correction (SMSEC) codes and are capable of correcting any errors occurring on a single memory cell, namely a column-deleted SMSEC code, an element-compacted SMSEC code and a product SMSEC code. In the proposed codes, the codewords are divided into two partitions, the elements on the first partition are over GF(2b1), while those on the remaining partition are over GF(2b2). This paper also gives guidelines for selection among the three SMSEC codes to meet the desired hardware overhead in the parallel decoder for realistic parameters of the partition pair, such as (b1, b2) 1/4 (4,3), (4,2) and (3,2). Moreover it is shown that the best choice for a MSS system is the SMSEC code with the shortest check bit length; if the check bit lengths of at least two codes are equal, then the use of the element-compacted SMSEC code incurs in the smallest hardware overhead.

Processing at the nanometric scales presents unique challenges that may require new computational paradigms such as approximate computing. In this paper a novel approach to memory protection using an unequal protection code (UEP) is proposed; this approach is in synergy with approximate (or inexact) computing. Multi-level burst error correcting UEP codes are analyzed. These codes improve over previously presented two-level burst error correcting UEP codes, because they utilize different conditions and criteria in the code partitions and decoder construction. An analysis by which multiple partitions can be selected to reduce the expected error magnitude, is provided. The area and power consumption of the parallel decoders closely depend on the desired code function. Simulation shows that the area and power consumption of the parallel error pattern generator are proportional to the partition length; the gate depth however is not strongly related to the partition length. The results of this manuscript confirm that the proposed multi-level burst error correcting UEP codes reduce the hardware overhead with no significant degradation in storage protection as potential storage application for approximate computing systems.

This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. A soft error rate (SER) analysis is also pursued to confirm the findings of the critical charge-based analysis. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A novel memory scheme with the proposed NVSRAM cells is proposed for tolerating MBU; in this scheme, only the error detection circuitry is required, because error correction is provided by the non-volatile elements of the NVSRAM cells. Simulation results show that the proposed scheme is very efficient in terms of delay and number of transistors (as measure of complexity). Moreover, the very high critical charge of some of the proposed cell designs reduces the number of MBU appearing as errors at the outputs of the memory, thus further reducing the error detection hardware required by the proposed scheme. An extensive evaluation and comparison of different schemes are presented.

Memory design has radically changed in the last few years; the emergence of new technologies has further improved performance and the traditional separation of storage levels between Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is not viable as in the past. Recently, the embedded DRAM (eDRAM) has been proposed for cache utilization to improve density while attempting to retain high performance operations; this scheme is often referred as hybrid due to the utilization of different technologies in a memory. In this paper, a hybrid scheme is proposed by adding non-volatile features and related circuits to the SRAM/eDRAM; an Oxide Resistive Random Access Memory (RRAM) is utilized as non-volatile storage in the embedded memory circuit. Different memory cells are proposed in this manuscript; they are evaluated with respect to circuit-level figures of merit as related to operational features (read, write, static noise margin, power delay product) as well as tolerance to event upsets (critical charge) and variations. Extensive simulation results using nanometric PTMs are provided. It is shown that the proposed designs offer substantial improvements over previous hybrid cells as well as a conventional NAND Flash memory cell.

This manuscript proposes non-binary orthogonal Latin square (OLS) codes that are amenable to a multilevel phase change memory (PCM). This is based on the property that the proposed (n symbols, ksymbols) t-symbol error correcting code uses the same H matrix as an (n bits, kbits) binary t-bit error correcting OLS code. The new codes are shown to have a shorter check bit length and better probability in encoding/decoding than conventional binary OLS codes. Extensive results are provided for assessment and comparison. The proposed codes are also shown to be always better than the matrix codes, i.e. independently of the metric and the parameters employed in the comparison.

Approximate (or inexact) computing is an attractive paradigm for digital processing at nanometric scales for applications in which imprecision in computation can be tolerated for improvements in other computational figures of merit, such as power consumption, circuit complexity and delay. The same principles of approximate computing are investigated in this manuscript for storage protection using an unequal protection code (UEP). In the proposed UEP code, the codeword is divided into two partitions; these partitions have different error protection functions. This paper presents a new class of two-level burst error correcting UEP codes and its parallel decoder. The proposed code is more efficient than an existing code in term of code rate, area and power consumption for the parallel decoder.

Dynamic Random Access Memories (DRAM) are widely used in processor design. Different cells have been proposed in the past to overcome concerns associated with low retention time, degradation in performance due to process variations and susceptibility to soft errors. This paper proposes two novel DRAM cells (referred to as 4TI and 4T1D) that utilize the techniques of gated diode and forward body-biasing to overcome the above issues. The designs of these cells are evaluated by HSPICE simulation; different figures of merits (such as Read delay, Write delay, retention time, power dissipation, critical charge and layout area) are assessed and a comparative analysis of the proposed cells with existing cells is pursued. The 4TI cell achieves the best power dissipation, while the 4T1D achieves the best retention time, the highest critical charge and the least average Read delay. An extensive simulation based evaluation of process variations is also presented to confirm that using static and Monte Carlo based analysis, the proposed cells are likely to be less affected by process variations (in threshold voltage and effective channel length) than the other cells found in the technical literature.

When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUTs). To facilitate the network on chip (NoC) testing, test engineers frequently focus on reusing the NoC as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocolsc) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM method and a TAM architecture named T2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 6% and 55% while imposing less than 9.6% area overhead.

This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The pro- posed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-μm process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.

The significance of redundant technologies for improving dependability and delay fault testability are growing. So, delay fault testing on two-rail logic circuits well known as a class of redundant technologies will become important. Two-rail logic circuits can be efficiently tested by noncodeword vector pairs. However, noncodeword vector pairs may sensitize some faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with noncodeword vector pairs may be overtesting. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the overtesting. The amounts of test data for the proposed test sets are, on average, 28.2 percent less than those for the test sets, which are obtained by the existing construction for unate circuits and lead to the overtesting.

This paper presents a low area on-chip delay measurement system using an embedded delay measurement circuit. To reduce the area, the proposed method does not demand the measurement of the exact path under measurement, but the measurement of a path including the path under measurement and wires of clock tree unlike the conventional methods. The proposed Stop Signal Generator (SSG) consists of OR gate trees and a selector circuit. In addition, the area of SSG is lower than the conventional one. SSG is additional circuit which sends the transition from the output of the path under measurement to the embedded delay measurement circuit. Therefore, the area of the proposed system is lower. Because the area is low, the proposed method can be used for small-delay defect detection in manufacturing testing and failure prediction due to aging after shipment. We can apply the proposed delay measurement system to any embedded delay measurement circuit that measures the time difference between the two input signal transitions sent to the circuit. The evaluation shows that the area overhead is 16.54%. It is 6.62% smaller than the conventional method, and 8.41% larger than standard scan design.

Recently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems. For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. Especially, quantitative metric of integrity has not been proposed yet. This paper proposes quantitative metric for integrity for remote systems based on the Internet. It is also useful for evaluation of the effect of the measure against data destruction elements. This paper applies it to example systems in order to confirm its effectiveness.

In recent high-density VLSIs, soft errors, particularly single event upsets (SEUs), frequently occur during system operation. In addition, the occurrence of delay faults caused by manufacturing defects is a significant problem. Thus, SEU tolerant design and delay fault testing are of increasing significance. This paper presents two types of SEU tolerant flip-flops (FFs). The proposed FFs tolerate SEUs caused by particles striking feedback loops in the FFs. Moreover, the proposed FFs allow enhanced scan delay fault testing. The proposed FFs are master-slave FFs, and the slave latches are constructed by modifying existing SEU tolerant latches, namely, SEH latches. The two proposed FFs tolerate particles with charges of 370 fC and of 369 fC or lower, whereas an existing SEU tolerant enhanced scan FF, called an ESFF-SEC, tolerates those of 431 fC or lower. Furthermore, the areas of the proposed FFs are 23.1% and 20.5% smaller than that of the ESFF-SEC. The CK-Q delay times are 44.4% and 41.1% shorter than that of the ESFF-SEC. Moreover, the average power consumptions of the proposed FFs during system operations are 55.6% and 53.3% lower than that of the ESFF-SEC.

This paper proposes a delay measurement technique using signature registers, and a scan design for delay measurement utilizing the proposed delay measurement technique to detect small-delay defects. The delay of circuits can be measured with the scan design with lower area, smaller data volume, and shorter measurement time than with the conventional scan design for delay measurement. Accordingly, the small-delay defects outside the range of the normal-distributed delay are detected with lower cost. Evaluation with 0.18 ¿m process shows that the area overhead of the proposed scan design is 32.2% smaller than that of the conventional method. The measurement time and the data volume for the measurement are reduced 66.7% and 66.0% compared with the conventional method, respectively.

Recently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems.For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. This paper proposes security evaluation metric which is a part of RASIS for remote systems using the Internet.The proposed metric gives quantitative evaluation in the similar manner of availability evaluation.It is based on the time that the system can tolerate take-over attack, which is one of the biggest threats among the attacks through the Internet.It can give appropriate system parameters to achieve the desired security.This paper applies it to example systems in order to confirm its effectiveness.

Two-rail logic circuits can be efficiently tested by non-codeword vector pairs. However, non-codeword vector pairs may sensitize some path delay faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with non-codeword vector pairs may be over-testing. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the over-testing.

This paper proposes a method providing efficient test compression for delay fault testing using enhanced scan design. In the proposed method, the initial and transition vectors of test data are interleaved before test compression using statistical coding. This paper also shows test architecture for delay fault testing using the proposed method. The proposed method is experimentally evaluated from the viewpoint of compression rates. For robust testable path delay fault testing on 11 out of 23 ISCA589 benchmark circuits, the combination of Huffman coding and the proposed method provides higher compression rates than Huffman coding without the proposed method, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC)

This paper proposes a design of a defect tolerant Wallace multipliers. A repair procedure for the proposed design is also shown. This paper evaluates the proposed design from the view point of the yield, area and delay time. For example, the yield of a 32 /spl times/ 32 Wallace multiplier increases from 0.90 to 0.99 by applying the proposed design while the area increases by a factor of 1.89.