Tetsuya Higuchi

dblp:04/830 · DBLP profile ↗
← Back
37ranked-venue papers
6as first author
0since 2021 · last 2015
0000-0003-1317-3560ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 26 · 3 first-authorGraphics, computer vision, multimedia, augmented reality and games · 15 · 1 first-authorSystems, architecture and hardware · 5 · 3 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1Human-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
1 paper
Audio and music processing · 100%
Computer architecture, parallel and distributed computing, and storage systems
8 papers
Hardware accelerators and domain-specific architectures · 34% Reconfigurable computing and FPGAs · 30% Parallel and multicore computing · 18%
Artificial intelligence
6 papers
Efficient and distributed learning · 37% Optimization for machine learning · 21% Machine translation · 21%

Topics — the 16 heaviest of 18, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Audio and music processing › audio classification
acoustic scene classification
0.212015
Acoustic Scene Classification based on Sound Textures and Events · ACM Multimedia 2015
Audio and music processing
sound event detection
0.212015
Acoustic Scene Classification based on Sound Textures and Events · ACM Multimedia 2015
Reconfigurable computing and FPGAs › reconfigurable computing
evolvable hardware
0.021999
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing · IEEE Trans. Computers 1999
Evolvable Hardware for Generalized Neural Networks · IJCAI 1997
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.011999
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing · IEEE Trans. Computers 1999
Hardware accelerators and domain-specific architectures
neural network hardware
0.011999
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing · IEEE Trans. Computers 1999
Machine learning › Efficient and distributed learning › automated machine learning › neural architecture search
evolutionary neural architecture search
0.011997
Evolvable Hardware for Generalized Neural Networks · IJCAI 1997
Processor architecture and microarchitecture › SIMD
parallel associative processor
0.021991
IXM2: A Parallel Associative Processor · ISCA 1991
IXM2: A Parallel Associative Processor for Knowledge Processing · AAAI 1991
Parallel and multicore computing › parallel architecture
massively parallel processing
0.031991
High Performance Memory-Based Translation on IXM2 Massively Parallel Associative Memory Processor · AAAI 1991
Massively Parallel Artificial Intelligence · IJCAI 1991
Massively Parallel Memory-Based Parsing · IJCAI 1991
Natural language and speech › Machine translation
example-based machine translation
0.011993
Example-Based Machine Translation on Massively Parallel Processors · IJCAI 1993
Machine learning › Optimization for machine learning › evolutionary computation
genetic algorithms
0.011993
Evolutionary Learning Strategy using Bug-Based Search · IJCAI 1993
Natural language and speech › Information extraction and text analysis
syntactic parsing
0.011991
Massively Parallel Memory-Based Parsing · IJCAI 1991
Emerging computing paradigms › neuromorphic computing
associative memory
0.011991
High Performance Memory-Based Translation on IXM2 Massively Parallel Associative Memory Processor · AAAI 1991
Parallel and multicore computing › parallel architecture
associative processor
0.011991
IXM2: A Parallel Associative Processor · ISCA 1991
Parallel and multicore computing › parallel architecture
massively parallel processor
0.011993
Example-Based Machine Translation on Massively Parallel Processors · IJCAI 1993
Parallel and multicore computing › parallel architecture
parallel processor
0.011991
IXM2: A Parallel Associative Processor · ISCA 1991
Processor architecture and microarchitecture › SIMD
SIMD processor
0.011991
IXM2: A Parallel Associative Processor · ISCA 1991

Methods — techniques the papers use, named apart from their topics

class-conditional fusion · 0.2evolvable hardware · 0.0evolutionary algorithm · 0.0genetic algorithm · 0.0DSP · 0.0parallel processing · 0.0example-based machine translation · 0.0memory-based reasoning · 0.0massively parallel parsing · 0.0evolutionary learning · 0.0bug-based search · 0.0associative processing · 0.0
YearPublicationVenuePosition
2015 Acoustic Scene Classification based on Sound Textures and Events
abstract
Semantic labelling of acoustic scenes has recently emerged as active topic covering a wide range of applications, e.g. surveillance and audio-based information retrieval. In this paper, we present an effective approach for acoustic scene classification through characterizing both background sound textures and acoustic events. The work takes inspiration from the psychoacoustic definition of acoustic scenes, that is, "skeleton of (acoustic) events on a bed of (sound) texture". In detail, we firstly employ distinct models to exploit sound textures and events in acoustic scenes, individually. Subsequently, based on fact that the perceptual importance of two parts will vary with respect to different scene categories, we develop favourable class-conditional fusion scheme to aggregate two-channel information. To validate proposed approach, we conduct extensive experiments on Rouen dataset which includes 19 categories of daily acoustic scenes with 3026 real-world recordings, and the proposed approach outperforms state-of-the-art methods by a large margin.
Jiaxing Ye, Takumi Kobayashi 0001, Masahiro Murakawa, Tetsuya Higuchi
ACM Multimedia4
2014 Robust acoustic feature extraction for sound classification based on noise reduction
abstract
In this paper, we present a novel method for environmental sound classification in non-stationary noise environment. The proposed method mainly consists of three stages: noise source separation and acoustic feature extraction and multi-class classification. At first stage, we employ probabilistic latent component analysis (PLCA) to perform time-varying noise separation. To alleviate the artifacts introduced by source separation, a series of spectral weightings is applied to enhance reliability of audio spectra. At feature extraction stage, we extract acoustic subspace to effectively characterize temporal-spectral patterns of denoised sound spectrogram. Subsequently, regularized kernel Fisher discriminant analysis (KFDA) is adopted to conduct multi-class sound classification through exploiting class conditional distributions based on extracted acoustic subspaces (features). The proposed method is evaluated with Real World Computing Partnership (RWCP) sound scene database and experimental results demonstrate its superior performance compared to other methods.
Jiaxing Ye, Takumi Kobayashi 0001, Masahiro Murakawa, Tetsuya Higuchi
ICASSP4
2013 Kernel discriminant analysis for environmental sound recognition based on acoustic subspace
abstract
In this paper, we propose an effective discriminant subspace learning framework to recognize the environmental sounds. Firstly, Gabor transform is adopted to characterize the time-frequency distributions of environmental sounds. We further encode the prominent time-frequency patterns with low rank representation by extracting the subspace from Gabor spectrogram. Unlike conventional sound recognition schemes that are mostly based on acoustic feature vectors, we treat the acoustic subspaces (matrixes) as basic elements for recognition, retaining rich temporal-spectral contextual information. At recognition stage, we employ kernel Fisher discriminant analysis to effectively exploit the class conditional distributions of environmental sounds which are favorable for performing multi-class classification. With a well developed kernel function, the proposed approach achieved superior recognition performance on RWCP sound scene database, compared with the existing methods.
Jiaxing Ye, Takumi Kobayashi 0001, Masahiro Murakawa, Tetsuya Higuchi
ICASSP4
2013 Incremental acoustic subspace learning for voice activity detection using harmonicity-based features
Jiaxing Ye, Takumi Kobayashi 0001, Masahiro Murakawa, Tetsuya Higuchi
INTERSPEECH4
2011 Detection of peptide ion peaks in mass spectra by using weighted auto-correlation
abstract
In biology, peptide ion detection from mass spectra is important for identifying proteins. Many methods have been proposed for detecting peptide ion peaks, some of which use wavelet transform. In these methods, however, the co-occurrence pattern of peptide ions and those isotopes is not directly considered. In this paper, we propose a novel method for detecting peptide ion peaks from a mass spectrum by using a weighted auto-correlation. The weight functions derived from Maxwell-Boltzmann distribution and the sine function are introduced to the proposed auto correlations to effectively represent the peptide ion co-occurrence patterns. The multi-scaled auto-correlation features extracted with those weight functions are compressed by using principal component analysis. Experiments on raw mass spectra show that the proposed method achieves the favorable performances and is capable of automatically detecting peptide ion peaks.
Kenji Watanabe, Takumi Kobayashi 0001, Katsuyuki Koike, Tetsuya Higuchi, Tohru Natsume, Nobuyuki Otsu
ICASSP4
2010 Audio-based sports highlight detection by fourier local auto-correlations
Jiaxing Ye, Takumi Kobayashi 0001, Tetsuya Higuchi
INTERSPEECH3
2008 Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins
abstract
To solve the problem of fluctuations in clock timing with digital LSIs (also known as the "clock skew" problem), we propose a genetic algorithm (GA) based clock adjustment method that ensures robust clock-timing to cope with fluctuations in the LSI environment such as temperature or power supply voltage. This method is realized by the combination of dedicated adjustable circuitry and adjustment GA software, with the values for multiple adjustable delay circuits inserted into the clock lines being determined by the GA software after fabrication. Experimental results demonstrate that the proposed method can enhance the operational yields of developed test chips while ensuring sufficient timing margins.
Tatsuya Susa, Masahiro Murakawa, Eiichi Takahashi, Tatsumi Furuya, Tetsuya Higuchi
HIS5
2007 Proposal of transmission line modeling using multi-objective optimization techniques
abstract
This paper presents the first successful application of multi-objective genetic algorithms (MOGA) to transmission line modeling. Conventionally, it is difficult to simultaneously realize high-accuracy transmission line simulations for both the frequency and time-domains. In order to overcome the problem, this paper proposes the application of MOGA to transmission line modeling. The proposed modeling method has two distinctive features: (1) Simultaneous modeling of both frequency and time-domain characteristics. (2) Selection of conventionalmodel from among set of Pareto optimization solutions based on simulation objectives. The results of an experiment with a micro-strip line demonstrate that the proposed method accomplished a transmission line simulation up to 2.54 times more accurate than conventional methods.
Yosuke Iijima, Masahiro Murakawa, Yuji Kasai, Eiichi Takahashi, Tetsuya Higuchi
IEEE Congress on Evolutionary Computation5
2005 Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm
abstract
In this paper, we present an automatic parameter extraction method with the GA (Genetic Algorithm) for surface-potential-based MOSFET models such as HiSIM (Hiroshima-university STARC IGFET Model). The method employs a two-stage extraction procedure operating on different sets of model parameters. Experimental results demonstrate that extraction of 34 parameters can be completed within 23 hours with PC (AthlonXP 2500), although this would typically take a human expert several days.
Masahiro Murakawa, Mitiko Miura-Mattausch, Tetsuya Higuchi
ASP-DAC3
2003 Automatic adjustments of a femtosecond-pulses laser using genetic algorithms
abstract
This paper describes the automatic adjustment of a femtosecond-pulse laser using genetic algorithms (GA). Laser systems must be precisely adjusted, because the light beam has to travel many times within a laser cavity before returning to the focus point with submicron resolution. Therefore, it typically takes three days or more to adjust a femtosecond laser manually, requiring much trial and error to determine the optimal settings. In order to overcome this problem, we propose an automatic adjustment method using genetic algorithms to quickly achieve the optimal settings for a femtosecond-pulse laser. We have also developed new mirror holders allowing for both high-precision and high-speed adjustment. With this laser system, the optical components can be automatically adjusted within 15 minutes.
Hirokazu Nosato, Yuji Kasai, Masahiro Murakawa, Taro Itatani, Tetsuya Higuchi
IEEE Congress on Evolutionary Computation5
2001 Evolving a cooperative population of neural networks by minimizing mutual information
abstract
Evolutionary ensembles with negative correlation learning (EENCL) is an evolutionary learning system for learning and designing neural network ensembles (Liu et al., 2000). The fitness sharing used in EENCL was based on the idea of "covering" the same training patterns by shared individuals. This paper explores connection between fitness sharing and information concept, and introduces mutual information into EENCL. Through minimization of mutual information, a diverse and cooperative population of neural networks can be evolved by EENCL. The effectiveness of such evolutionary learning approach was tested on two real-world problems.
Yong Liu 0012, Xin Yao 0001, Qiangfu Zhao, Tetsuya Higuchi
CEC4
2001 Scaling up fast evolutionary programming with cooperative coevolution
abstract
Evolutionary programming (EP) has been applied with success to many numerical and combinatorial optimization problems in recent years. However, most analytical and experimental results on EP have been obtained using low-dimensional problems. It is interesting to know whether the empirical results obtained from the low-dimensional problems still hold for high-dimensional cases. It was discovered that neither classical EP (CEP) nor fast EP (FEP) performed satisfactorily for some large-scale problems. The paper shows empirically that FEP with cooperative coevolution (FEPCC) can speed up convergence rates on the large-scale problems whose dimension ranges from 100 to 1000. Cooperative coevolution adopts the divide-and-conquer strategy. It divides the system into many modules, and evolves each module separately and cooperatively. The results of FEPCC on the problems investigated here are something of a surprise. The time used by FEPCC to find a near optimal solution appears to scale linearly; that is, the time used seems to go up linearly as the dimensionality of the problems studied increases.
Yong Liu 0012, Xin Yao 0001, Qiangfu Zhao, Tetsuya Higuchi
CEC4
2000 Adaptive Wavelet Transform for Lossless Compression using Genetic Algorithm
Yasuo Takehisa, Hidenori Sakanashi, Tetsuya Higuchi
GECCO3
2000 An Integrated On-Line Learning System for Evolving Programmable Logic Array Controllers
Yong Liu 0012, Masaya Iwata, Tetsuya Higuchi, Didier Keymeulen
PPSN3
2000 Evolutionary ensembles with negative correlation learning
abstract
Based on negative correlation learning and evolutionary learning, this paper presents evolutionary ensembles with negative correlation learning (EENCL) to address the issues of automatic determination of the number of individual neural networks (NNs) in an ensemble and the exploitation of the interaction between individual NN design and combination. The idea of EENCL is to encourage different individual NNs in the ensemble to learn different parts or aspects of the training data so that the ensemble can learn better the entire training data. The cooperation and specialization among different individual NNs are considered during the individual NN design. This provides an opportunity for different NNs to interact with each other and to specialize. Experiments on two real-world problems demonstrate that EENCL can produce NN ensembles with good generalization ability.
Yong Liu 0012, Xin Yao 0001, Tetsuya Higuchi
IEEE Trans. Evol. Comput.3
1999 The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing
abstract
This paper describes the GRD (Genetic Reconfiguration of DSPs) chip, which is evolvable hardware designed for neural network applications. The GRD chip is a building block for the configuration of a scalable neural network hardware system. Both the topology and the hidden layer node functions of a neural network mapped on the GRD chips are dynamically reconfigured using a genetic algorithm (GA). Thus, the most desirable network topology and choice of node functions (e.g., Gaussian or sigmoid function) for a given application can be determined adaptively. This approach is particularly suited to applications requiring the ability to cope with time-varying problems and real-time constraints. The GRD chip consists of a 100 MHz 32-bit RISC processor and 15 33 MHz 16-bit DSPs connected in a binary-tree network. The RISC processor is the NEC V830 which executes mainly the GA. According to chromosomes obtained by the GA, DSP functions and the interconnection among them are dynamically reconfigured. The GRD chip does not need a host machine for this reconfiguration. This is desirable for embedded systems in practical industrial applications. Simulation results on chaotic time series prediction are two orders of magnitude faster than on a Sun Ultra 2.
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao 0001, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi
IEEE Trans. Computers7
1999 Real-world applications of analog and digital evolvable hardware
abstract
In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITI's Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation.
Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu
IEEE Trans. Evol. Comput.1
1999 Promises and challenges of evolvable hardware
abstract
Evolvable hardware (EHW) has attracted increasing attention since the early 1990s with the advent of easily reconfigurable hardware, such as field programmable gate arrays (FPGAs). It promises to provide an entirely new approach to complex electronic circuit design and new adaptive hardware. EHW has been demonstrated to be able to perform a wide range of tasks, from pattern recognition to adaptive control. However, there are still many fundamental issues in EHW that remain open. This paper reviews the current status of EHW, discusses the promises and possible advantages of EHW, and indicates the challenges we must meet in order to develop practical and large-scale EHW.
Xin Yao 0001, Tetsuya Higuchi
IEEE Trans. Syst. Man Cybern. Part C2
1998 On-Line Compression of High Precision Printer Images by Evolvable Hardware
abstract
This paper describes an image compression system based on evolvable hardware (EHW) for high precision printers (HPP). These printers are especially flexible for book publishing, but require large disk space for images, in particular those of higher resolution. To increase the printing speed and reduce the disk space, the images should be compressed. The system for this compression must be (1) adaptive, so that it changes depending on image characteristics and (2) on-line, which means implemented in hardware. The standard compression methods have a simple template change strategy which is not efficient for the images of HPP. We used an EHW system for compressing HPP images in real time. The EHW is a type of adaptive hardware which allows evolutionary algorithms to change the hardware configuration in real time. It works as fast as other compression systems (like the JBIG standard), but changes the image modeling to reflect the changes in the image characteristics. Simulation results show more than a 50% increase in compression ratio compared to JBIG for the printer system.
Mehrdad Salami, Hidenori Sakanashi, Masaharu Tanaka, Masaya Iwata, Takio Kurita 0001, Tetsuya Higuchi
Data Compression Conference6
1998 Adaptive Blind Equalization Using Bottleneck Networks Implemented by Evolvable Hardware
Masahiro Murakawa, Kazuyuki Hiraoka, Tetsuya Higuchi, Tatsumi Furuya, Shuji Yoshizawa
ICONIP3
1998 Online Evolution for a Self-Adapting Robotic Navigation System Using Evolvable Hardware
abstract
Great interest has been shown in the application of the principles of artificial life to physically embedded systems such as mobile robots, computer networks, home devices able continuously and autonomously to adapt their behavior to changes of the environments. At the same time researchers have been working on the development of evolvable hardware, and new integrated circuits that are able to adapt their hardware autonomously and in real time in a changing environment. This article describes the navigation task for a real mobile robot and its implementation on evolvable hardware. The robot must track a colored ball, while avoiding obstacles in an environment that is unknown and dynamic. Although a model-free evolution method is not feasible for real-world applications due to the sheer number of possible interactions with the environment, we show that a model-based evolution can reduce these interactions by two orders of magnitude, even when some of the robot's sensors are blinded, thus allowing us to apply evolutionary processes online to obtain a self-adaptive tracking system in the real world, when the implementation is accelerated by the utilization of evolvable hardware.
Didier Keymeulen, Masaya Iwata, Yasuo Kuniyoshi, Tetsuya Higuchi
Artif. Life4
1997 Evolvable Hardware for Generalized Neural Networks
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Tetsuya Higuchi
IJCAI4
1997 Recent Advances in Evolvable Systems - ICES 96 (International Conference on Evolvable Systems)
abstract
This paper reviews the developments in evolvable hardware systems presented at the First International Conference on Evolvable Systems (ICES 96). The main body of the review gives an overview of the 34 papers presented orally, splitting them into three broad groups according to whether they involve (1) evolving a fit solution to a problem as a member of a population of competing candidates, (2) evolving solutions that can individually learn from and adapt to their environments, or (3) the embryonic growth of solutions. We also review the discussion sessions of the conference and give pointers to related upcoming events.
Ian Frank, Bernard Manderick, Tetsuya Higuchi
Evol. Comput.3
1996 A Pattern Recognition System Using Evolvable Hardware
Masaya Iwata, Isamu Kajitani, Hitoshi Yamada, Hitoshi Iba, Tetsuya Higuchi
PPSN5
1996 Hardware Evolution at Function Level
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Tatsumi Furuya, Masaya Iwata, Tetsuya Higuchi
PPSN6
1994 Applying Evolvable Hardware to Autonomous Agents
Tetsuya Higuchi, Hitoshi Iba, Bernard Manderick
PPSN1
1993 Evolutionary Learning Strategy using Bug-Based Search
Hitoshi Iba, Tetsuya Higuchi, Hugo de Garis, Taisuke Sato
IJCAI2
1993 Example-Based Machine Translation on Massively Parallel Processors
Eiichiro Sumita, Kozo Oi, Osamu Furuse, Hitoshi Iida, Tetsuya Higuchi, Naoto Takahashi, Hiroaki Kitano
IJCAI5
1992 BUGS: A Bug-Based Search Strategy using Genetic Algorithms
Hitoshi Iba, Sumitaka Akiba, Tetsuya Higuchi, Taisuke Sato
PPSN3
1991 IXM2: A Parallel Associative Processor for Knowledge Processing
Tetsuya Higuchi, Hiroaki Kitano, Tatsumi Furuya, Ken'ichi Handa, Akio Kokubu, Naoto Takahashi
AAAI1
1991 High Performance Memory-Based Translation on IXM2 Massively Parallel Associative Memory Processor
Hiroaki Kitano, Tetsuya Higuchi
AAAI2
1991 Massively Parallel Memory-Based Parsing
Hiroaki Kitano, Tetsuya Higuchi
IJCAI2
1991 Massively Parallel Artificial Intelligence
Hiroaki Kitano, James A. Hendler, Tetsuya Higuchi, Dan I. Moldovan, David L. Waltz
IJCAI3
1991 IXM2: A Parallel Associative Processor
abstract
Article IXM2: a parallel associative processor Share on Authors: Tetsuya Higuchi Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305 Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305View Profile , Tatsumi Furuya Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305 Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305View Profile , Kenichi Handa Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305 Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305View Profile , Naoto Takahashi University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, Japan 305 University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, Japan 305View Profile , Hiroyasu Nishiyama University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, Japan 305 University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, Japan 305View Profile , Akio Kokubu New Media Development Associate, 1-4-28 Mita, Minato-ku, Tokyo, Japan 108 New Media Development Associate, 1-4-28 Mita, Minato-ku, Tokyo, Japan 108View Profile Authors Info & Claims ISCA '91: Proceedings of the 18th annual international symposium on Computer architectureApril 1991 Pages 22–31https://doi.org/10.1145/115952.115956Online:01 April 1991Publication History 5citation307DownloadsMetricsTotal Citations5Total Downloads307Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, Naoto Takahashi, Hiroyasu Nishiyama, Akio Kokubu
ISCA1
1991 Initial evaluation of a parallel associative processor IXM2
Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, Akio Kokubu
Microprocessing and Microprogramming1
1990 Massively parallel spoken language processing using a parallel associative processor IXM2
Hiroaki Kitano, Tetsuya Higuchi, Masaru Tomita
ICSLP2
1989 The Prototype of a Semantic Network Machine IXM
Tetsuya Higuchi, Tatsumi Furuya, Hiroyuki Kusumoto, Ken'ichi Handa, Akio Kokubu
ICPP (1)1