Clock skew minimization that is an important issue in very large scale integration design has become difficult due to the presence of process, voltage, and temperature (PVT) variations. The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even after a chip is manufactured has generated considerable discussion. The basic idea of the PST architecture is to minimize the clock skew dynamically. Unlike most previous works that have focused on the implementation and the performance issues of a PST architecture, this paper focuses on the testing issues of a PST architecture. However, testing the variation tolerance ability of the PST architecture is difficult because the clock skew does not directly affect the functionality of a design. In this paper, we propose an efficient fault model considering the physical limitation of the devices for the PST architecture. In addition, we propose some novel structures to detect the manufacturing faults and increase the robustness of a PST architecture. Our experiment shows that with a little increase in overhead, we can achieve robustness.

Clock skew minimization is an important design consideration. However, with the advance of the technology and the smaller device scaling, Process, Voltage, and Temperature (PVT) variations make the clock skew minimization face great challenges. To mitigate the impact of PVT variations, many previous works proposed the Post Silicon Tuning (PST) architecture to dynamically balance the skew of a clock tree. In the PST architecture, there are two main components: Adjustable Delay Buffer (ADB) and Phase Detector (PD). In this paper, we make a survey about existing techniques to the PST architecture and introduce several important design concerns such as the ADB selection, system controlling, and design testing to the PST architecture.

Clock skew minimization is important in VLSI design field. Due to the presence of Process, Voltage, and Temperature (PVT) variations, the Post-Silicon Skew Tuning (PST) technique with the ability of tolerating PVT variations has brought a broad discussion. A PST architecture can dynamically minimize the clock skew even after a chip is manufactured. However, testing the variation tolerance ability of a PST architecture is very difficult because the clock skew does not directly affect the functionality of a design. In addition, creating PVT variation in the traditional testing environment is not easy. Unlike most previous works which focus on the implementation and the performance issues of a PST architecture, the objective of this paper is to propose efficient test mechanisms and verify the variation tolerance ability. In addition, we also propose a novel structure to increase the robustness of a PST architecture in case of a manufacturing fault. Our experiment shows that with little overhead, we can achieve robustness.

Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured. There are two key components in the skew synchronization scheme: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous researchers have emphasized on ADB placement issues. In this paper, we show that the connection between FFs and PDs can also greatly influence the final clock skew due to the insertion of the PDs. We first analyze the influence of PD connection structures. Then we propose an algorithm to generate a PD connection structure which achieves the minimum influence to the clock skew. Our experimental results are very encouraging.

Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock skew has faced a great challenge. To overcome the influence of PVT variations, several previous works proposed Post Silicon Tuning (PST) architecture to dynamically balance the skew of a clock tree. In the PST architecture, there are two main components: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous works focus on determining good positions of ADBs in a PST design. In this paper, we first show that which pairs of FFs are connected to PDs, called PD structure, also greatly influence the complexity of hardware control for a PST design. Without careful planning of a PD structure, we need large number of control signals to adjust the delays of ADBs. In addition, we also show that a PD structure may influence the accuracy of the clock skew. Among possible connection structures, this paper proposes an efficient PD structure which not only simplifies the hardware control but also minimizes the clock skew of a PST design.