Wafer packing is a process of combining multiple chip designs on the same wafer such that the fabrication cost can be shared by several designs and hence reduced. This technique is widely used for designs that require a small number of dies or chips. It is essential to have computer algorithms to decide how to allocate designs to wafers in order to reduce the total fabrication cost. Based on different wafer fabrication techniques, two versions of the wafer packing problem are formulated. The authors study different variations for each version. They present algorithms to find optimal solutions for these variations which are polynomial-time solvable. They also present heuristic algorithms for those proven to be NP-hard. The effectiveness of the proposed algorithms is demonstrated by experimental results.>

A new approach to the performance-driven placement based on a window concept is presented. We first convert timing constraints to geometric shapes using the defined windows. A window represents a region in which all the modules along a given path can be placed without degrading the circuit performance. Then a constructive placement process uses the window information to select an unplaced module, and to find an appropriate position for the module. This approach represents a unified way to consider both timing and geometric constraints during the placement process. The experimental results show that the improvement of circuit performance can be achieved by the sufficient use of the window information.

We have developed a gate matrix layout synthesis tool which utilizes folding technique on both rows and columns. The conventional interval graph model and the recently proposed dynamic net-list representation can not fully depict circuit schematics such as inter-net connections. The incomplete representations may mislead the search process for an optimal solution during the layout partitioning and the gate ordering phases. We propose a new graph-based model called hierarchical dynamic net-list to improve the schematic representation. Based on the new model, the folded layout area in the partitioning phase can be more accurately estimated. The new gate ordering algorithm proposed by us also takes the advantages of the hierarchical dynamic net-list model to handle the gate placement in the folded layouts. The experimental results show 12% to 15% improvement in layout area for small circuits and 30% improvement for a large circuit.