Complementary field-effect transistors (CFETs) have emerged as promising candidates for next-generation semiconductor devices. CFETs feature a structure with an nMOS (or pMOS) transistor at the bottom and a transistor of the opposite type at the top. CFETs can be classified into Fin-CFETs or GAA-CFETs based on their channel structure. In this study, we compare and analyze these two devices to determine which structure is more favorable for device scaling and which device exhibits better performance per unit area. For a reliable analysis, the threshold voltage was adjusted to be the same for all devices. Initially, to compare the DC performance, the on-state drive currents in both linear mode and saturation mode operations were extracted and compared from the$I_{\mathrm { DS}}$-versus-$V_{\mathrm { GS}}$input-transfer characteristics. Subsequently, complementary metal-oxide-semiconductor inverters were constructed to compare their AC performance. Six parameters were extracted and compared: high-to-low propagation delay ($t_{pLH}$), falling time ($t_{f}$), low-to-high propagation delay ($t_{pLH}$), rising time ($t_{r}$), overshoot voltage ($V_{ov}$), and undershoot voltage ($V_{und}$). Based on the results, we suggest which CFET structure is more suitable for device scaling.

Line edge roughness (LER) is an undesirable phenomenon that arises during semiconductor fabrication processes, causing fluctuations in the characteristics of semiconductor devices and potentially leading to significant yield degradation. Consequently, LER must be meticulously considered before fabricating integrated circuits. In this study, we present an approach for implementing and analyzing LER in vertical channel array transistors (VCATs) with a gate-all-around (GAA) structure for dynamic random access memory applications. Initially, we propose a method for reliably implementing LER in GAA semiconductor devices. Next, we extend the method to more complex structures beyond the basic cylindrical GAA structure. Utilizing the proposed method, we investigate the impact of LER on various VCAT device configurations by examining DC performance metrics such as IOFF, IDS,LIN, IDS,SAT, VT,LIN, VT,SAT, IOV,LIN, and IOV,SAT. Additionally, we explore AC performance metrics (THOLD, TREAD, and TWRITE) through mixed-mode simulations. The results show that the parameters influencing LER-induced fluctuations in VCATs vary depending on the transistor’s operating region (i.e., whether the transistor is turned on or not).

Recent advancements in deep learning have achieved significant progress by increasing the number of parameters in a given model. However, this comes at the cost of computing resources, prompting researchers to explore model compression techniques that reduce the number of parameters while maintaining or even improving performance. Convolutional neural networks (CNN) have been recognized as more efficient and effective than fully connected (FC) networks. We propose a column row convolutional neural network (CRCNN) in this letter that applies 1D convolution to image data, significantly reducing the number of learning parameters and operational steps. The CRCNN uses column and row local receptive fields to perform data abstraction, concatenating each direction's feature before connecting it to an FC layer. Experimental results demonstrate that the CRCNN maintains comparable accuracy while reducing the number of parameters and compared to prior work. Moreover, the CRCNN is employed for one-class anomaly detection, demonstrating its feasibility for various applications.

Continued increase in variability is a challenge for SRAM scaling into sub-22 nm nodes, and presents an opportunity for the introduction of alternate technologies. In this work, the performance and threshold-voltage variability of vertical SOI finFETs are compared against those of planar fully depleted (FD) SOI MOSFETs with thin buried oxide, and are presented as an alternative to planar bulk CMOS. Analytical modeling derived from 3D device simulations is used to estimate six-transistor SRAM cell performance and yield metrics.