This article presents a 24-MHz fast startup crystal oscillator (XO) with a phase-interpolator-assisted synchronized injection technique. The technique ensures phase consistency between the injection source and the crystal resonance, even with a 2% injection-$\Delta F$, enhancing the robustness of the startup under different PVT conditions. Additionally, we propose a differential peak detection technique to detect the phase error incurred by$\Delta F$. Such a peak detection technique shortens the auxiliary non-injection period during startup to merely four cycles, thereby maximizing the injection percentage to 97.4% and enhancing the startup’s efficacy. Fabricated in the 40-nm CMOS process, the XO achieves a 6.9-$\mu $s startup time (166 cycles) with a startup energy of 4.8 nJ under a 1-V$V_{\text {DD}}$. Furthermore, the startup time varies by ±4.4%, ±3.6%, and ±5.1% (worst case) over$\Delta F$(0.25% to 2%), temperature (−40 to$85~^{\circ }$C), and$V_{DD}$(0.95 to 1.05 V) variations, respectively. The XO’s phase noise in the steady-state is −137.8dBc/Hz at the 1-kHz offset, with a power consumption of$63~\mu $W.

This paper presents an analysis of differential-drive cross-coupled (DDCC) rectifier in high-sensitive RF energy harvesting system. The relationship between input RF voltage and output DC voltage with gate compensation voltage is built. Meanwhile, effects of mismatches on differential input branches are discussed. To verify the mismatch analysis, simulations on both the amplitude mismatch and the phase mismatch are conducted under standard CMOS 180nm process. Both theorical analysis and simulations indicate that the amplitude mismatch features little effect on the output DC voltage but the phase mismatch plays a much more important role to decrease the output voltage of DDCC rectifiers.

A novel Built-In Self-Test (BIST) algorithm is proposed in this paper, which is used for testing low-voltage SRAM. The algorithm is the improvement of March C+ algorithm, which integrates the continuous write 0 and write 1 operations to cover more fault models like Read Destructive Coupling Fault (CFrd), Write Destructive Coupling Fault (CFwd) and Write Disturb Fault. Consequently, higher fault coverage is achieved than traditional March algorithm. The proposed algorithm is implemented by user defined algorithm (UDA) of Mentor tools. In order to verify the effectiveness of the algorithm, a low-voltage 8T SRAM chip is designed and tested based on SMIC 40nm LL CMOS process. Simulation results show that the proposed BIST algorithm named March-LV for low-voltage SRAM arrays covers 100% target faults. The test results further verify the feasibility of the algorithm.