In this paper, a low-power and high-precision time-domain winner-take-all (WTA) circuit is proposed which is based on a novel group search algorithm. The proposed method, which determines the winner input within a single clock cycle, not only demands no multi-input positive-feedback latch, but also reduces the number of required latches. Therefore, the accuracy of the circuit is improved, and its power consumption is significantly reduced. In order to reduce the power consumption further, power gating and clock gating techniques are utilized for the employed delay lines. Post-layout simulation results for a 4-input WTA circuit in a 65-nm standard CMOS technology with a supply voltage of 0.5 V show that the total power consumption of the proposed structure at the operating frequency of 1 MHz is approximately 60 nW. Moreover, the precision of the circuit is 99.8%, and the silicon area occupied by the circuit is 16μm×34μm.

Unstructured neural network pruning algorithms have achieved impressive compression ratios. However, the resulting-typically irregular-sparse matrices hamper efficient hardware implementations, leading to additional memory usage and complex control logic that diminishes the benefits of unstructured pruning. This has spurred structured coarse-grained pruning solutions that prune entire feature maps or even layers, enabling efficient implementation at the expense of reduced flexibility. Here, we propose a flexible new pruning mechanism that facilitates pruning at different granularities (weights, kernels, and feature maps) while retaining efficient memory organization (e.g., pruning exactly k -out-of- n weights for every output neuron or pruning exactly k -out-of- n kernels for every feature map). We refer to this algorithm as dynamic probabilistic pruning (DPP). DPP leverages the Gumbel-softmax relaxation for differentiable k -out-of- n sampling, facilitating end-to-end optimization. We show that DPP achieves competitive compression ratios and classification accuracy when pruning common deep learning models trained on different benchmark datasets for image classification. Relevantly, the dynamic masking of DPP facilitates for joint optimization of pruning and weight quantization in order to even further compress the network, which we show as well. Finally, we propose novel information-theoretic metrics that show the confidence and pruning diversity of pruning masks within a layer.

This brief proposes a low-voltage, high-precision, and high-dynamic-range current-mode analog winner-take-all (WTA) circuit. The proposed structure employs a new high-gain stage as a feedback network between the input node of each cell and the common node of the circuit to reduce the sensitivity of the output current to the loser signals, especially when they are close to the winner. In addition, another network is employed that senses the amount of the output/winner current and adjusts the bias current of the gain stages. This ensures that the drain-source voltage of the input transistor in the winner cell matches the behavior of the output transistor’s drain-source voltage, enhancing the accuracy as well as the input dynamic range (DR) of the structure. Moreover, since the circuit works properly with a minimum supply voltage of only$V_{\text {GS}} + V_{\text {eff}}$, it is a promising candidate for applications in emerging technologies with low supply voltage requirements. Based on the proposed structure, a three-input WTA circuit is designed and fabricated in a 0.18-$\mu $m CMOS technology. According to the measurement results, the proposed circuit exhibits a maximum error of 1.5% for the input signal range of$60~\mu $A when the input frequency is 100 kHz. The silicon area occupied by the circuit is$33~\mu $m$\times 65~\mu $m.

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pruning in dedicated hardware is not a straightforward task, which increases memory and reduces the effective bandwidth usage. Moreover, such pruning algorithms should be adapted to certain hardware requirements, such as the use of tiling. Therefore, in this work, we leverage the use of the Gumbel-Softmax relaxation sampling to structurally prune tiles, which benefits further hardware implementations, and additionally allows to jointly optimize with quantization. Additionally, we show that the combination of different pruning scenarios leads to a larger sparsity. Finally, we demonstrate the benefit of using structured pruning on fine-grained elements (weights) in an FPGA design.

Walsh-Hadamard based orthogonal sampling of signals is studied in this paper, and an application of this technique is presented. Using orthogonal sampling, a single analog-to-digital converter (ADC) only is sufficient to perform parallel (simultaneous) recording from the sensors. Furthermore, employing Walsh functions as modulation signals, the required bandwidth of the ADC in the proposed system is equal to the bandwidth of a time-multiplexed ADC in a system with identical number of recording channels. Therefore, the bandwidth of the ADC in the proposed system is effectively employed and shared among all the channels. The efficient usage of the ADC bandwidth leads to saving power at the ADC stage and reducing the datarate of the output signal compared to state-of-the-art recording systems based on frequency-division multiplexing. This paper presents the orthogonal sampling technique for neural recording in multi-channel recording systems which is implemented with four recording channels using a 0.18 μm technology which results in a power consumption of 1.26 μW/channel at a 0.8 V supply.

This paper investigates a common phenomenon in current mode stimulation which is known as current overshoots and undershoots. The origin of these abnormalities in the current pulses has remained an open issue and these overshoots and undershoots have been considered as unwanted phenomena during the stimulation. A circuit-level perspective of the origin of the current overshoots (and possible undershoots) is studied in this paper. Possible solutions to overcome these issues are also presented which are validated using a 0.18 μm high-voltage CMOS technology.

A closed-loop system aiming at epilepsy control is proposed in this paper, in which electrical stimulation is triggered upon a decision aggragating different biological signatures of the seizure such as changes in the heart rate, blood flow in the brain, along side the changes in the iEEG signals. iEEG signals are recorded and processed in the implantable part of the system. Electrical stimulation of deep-brain or vagus nerve targets which are known to be effective in seizure abortion is started upon detection of a seizre onset. This paper focuses on the implantable part of the system including a high dynamic-range amplifier, a sub-ranging/amplification stage, a line-length feature extractor and a stimulator. The implantable part is integrated using a 0.18 μm technology.

The widely accepted block-matching technique, which is required to identify motion vectors, fails in cases in which texture is not existent. In [1], we proposed a hardware-oriented cellular-automaton algorithm that generates spatial patterns on textureless objects and backgrounds, aiming at motion-vector estimation of textureless moving objects. This demonstration presents a field-programmable gate array (FPGA) system that supports real-time processing. This system provides motion-vectors in moving textureless objects and enables enhanced processing of motion vector classification.

Real-time results obtained from an unsupervised feature extraction system using Restricted Boltzmann Machines (RBMs) implemented on FPGA are presented. The feature extraction application is demonstrated using the MNIST dataset, and the weights storing features are visualized in real-time. A digit classification is also performed based on the learning results. Our demonstration system performs 134 times faster than the compared conventional CPU.

A low-density parity check (LDPC) circuit and its properties as a post-processor is proposed for physically unclonable functions (PUFs) applications. PUFs can be realized using process variations or signal noises in SRAM or other PUF circuits, whereas the generated data needs to be processed by error check and correction (ECC) because of their inherent intra-PUF variabilities. The bit-flip LDPC circuits that have been developed in this study reveal compact constructions as well as notable noise tolerances during the ECC calculations. Unlike conventional deterministic post-processing, the LDPC circuits made even under unreliable fabrication conditions keep capable of guaranteeing robustness against noises.

A key aspect of constructing highly scalable Deep-learning microelectronic systems is to implement fault tolerance in the learning sequence. Error-injection analyses for memory is performed using a custom hardware model implementing parallelized restricted Boltzmann machines (RBMs). It is confirmed that the RBMs in Deep Belief Networks (DBNs) provides remarkable robustness against memory errors. Fine-tuning has significant effects on recovery of accuracy for static errors injected to the structural data of RBMs during and after learning, which are either at cell-level or block level. The memory-error tolerance is observable using our hardware networks with fine-graded memory distribution.

Live results obtained from the first real-time high-resolution free viewpoint synthesis hardware that utilizes three-camera disparity estimation are presented. The proposed hardware generates high-quality free viewpoint video at 55 frames per second on a Virtex-7 FPGA at a 1024×768 XGA video resolution for any horizontally-aligned arbitrary camera positioned between the leftmost and rightmost physical cameras.

The recent development of high-quality free viewpoint synthesis algorithms and their implementations allows to realize glasses-free 3D perception. Although many algorithms have been developed in this domain, the real-time hardware realization of a free viewpoint synthesis for real-world images is challenging due to its high computational load and memory bandwidth requirements. In this paper, the first real-time high-resolution free viewpoint synthesis hardware utilizing three-camera disparity estimation is presented. The proposed hardware generates high-quality free viewpoint video at 55 frames per second using a Virtex-7 FPGA at a 1024×768 XGA video resolution for any horizontally-aligned arbitrary camera positioned between the leftmost and rightmost physical cameras.

This paper presents a high-voltage, high-current implantable cortical stimulation integrated circuit aiming at supporting the rehabilitation of patients suffering from stroke. In this context, a large area of the motor cortex needs to be stimulated, requiring high current densities at the electrode-electrolyte interface. The designed integrated circuit contains eight fully programmable stimulation channels generating biphasic constant current pulses up to 8mA from a 20V supply. The current mismatch between positive and negative pulses has been evaluated at 0.03%. The chip has been fabricated in an AMS 0.18μm high-voltage CMOS process, and has a die area of 5mm2.

Centralized and multilevel implementations of the Panoptic omnidirectional multiaperture visual system were previously presented by us, relying on the transmission of all camera outputs to a single central processing node for omnidirectional image and video reconstruction. In this paper, a novel distributed and parallel implementation of the omnidirectional vision reconstruction algorithm of the Panoptic system is presented. The parallel approach aims to overcome the scalability problems and memory bandwidth limitations of the centralized approach. The real-time hardware implementation is presented for camera modules with image processing, memory, and interconnectivity features. A methodology is introduced for the arrangement of camera modules with interconnectivity feature into a target interconnection network topology. A unique custom-made multiple-field-programmable gate array hardware platform is introduced for the implementation of an interconnected network of 49 camera prototype Panoptic system. A hardware architecture based on presented hardware platform enabling the real-time implementation of the blending algorithms is presented, along with the imaging results and resource utilization. The real-time implementation results of the implemented omnivision application on the mentioned prototype are demonstrated.

Ultra-low power circuit design techniques have enabled rapid progress in biosignal acquisition. The design of a multi-channel biosignal recording system is a challenging task, considering the low amplitude of neural signals and limited power budget for an implantable system. The front-end low-noise amplifier is a critical component with respect to overall power consumption and noise of such system. In this paper, we present a new design of III-V Heterojunction TFET (HTFET)-based neural amplifier employing a telescopic operational transconductance amplifier (OTA) for multi-channel neural spike recording. Exploiting the unique device characteristics of HTFETs, our simulation shows that the proposed amplifier exhibits a midband gain of 39 dB, a gain bandwidth of 12 Hz-2.1 kHz, and an input-referred noise of 6.27 μVrms, consuming 5 nW of power at a 0.5 V supply voltage. Using the proposed HTFET amplifier, a noise efficiency factor (NEF) of 0.64 is achieved, which is significantly lower than the CMOS-based theoretical limit. Design tradeoffs related to gain, power and noise requirements are investigated, based on a comprehensive electrical noise model of HTFET and compared with the baseline Si FinFET design.

The computational complexity of disparity estimation algorithms and the need of large size and bandwidth for the external and internal memory make the real-time processing of disparity estimation challenging, especially for High Resolution (HR) images. This paper proposes a hardware-oriented adaptive window size disparity estimation (AWDE) algorithm and its real-time reconfigurable hardware implementation that targets HR video with high quality disparity results. The proposed algorithm is a hybrid solution involving the Sum of Absolute Differences and the Census cost computation methods to vote and select the best suitable disparity candidates. It utilizes a pixel intensity based refinement step to remove faulty disparity computations. The AWDE algorithm dynamically adapts the window size considering the local texture of the image to increase the disparity estimation quality. The proposed reconfigurable hardware of the AWDE algorithm enables handling 60 frames per second on Virtex-5 FPGA at a 1024×768 XGA video resolution for a 120 pixel disparity range.1

A novel compressive sampling scheme suitable for highly scalable hardware implementation is presented. The prototype design is implemented in a 0.18μm standard CMOS technology and utilizes compressed acquisition to achieve high frame rates and maintain low power consumption. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation algorithm is implemented which reduces in-pixel hardware complexity and performs measurement matrix generation in a single clock cycle. Per-column Differential Cyclic-ADCs based on the Zero-Crossing Detection (ZCD) technique are used to convert the analog image measurements. Physical IC design issues such as the required dynamic range, device noise, mismatch and non-linearity, are analyzed and their effects on compressed image acquisition are presented and discussed. The final simulation results show that the proposed 256x256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The proposed architecture can easily be scaled towards newer technology nodes and higher image resolutions.

This paper presents a novel approach to acquire multichannel wireless intracranial neural data based on a compressive sensing scheme. The designed circuits are extremely compact and low-power which confirms the relevance of the proposed approach for multichannel high-density neural interfaces. The proposed compression model enables the acquisition system to record from a large number of channels by reducing the transmission power per channel. Our main contributions are the twofold. First, a CMOS compressive sensing system to realize multichannel intracranial neural recording is described. Second, we explain a joint sparse decoding algorithm to recover the multichannel neural data. The idea has been implemented at system as well as circuit levels. The simulation results reveal that the multichannel intracranial neural data can be acquired by compression ratios as high as four.

A novel real-time implementation of a multi-resolution image blending algorithm is presented in this paper. A multi-resolution decomposition of the input is used to blend multiple images at different scales. Processing time is shortened by designing a pipeline system. The proposed solution requires less hardware multipliers and is able to achieve very high operating frequencies, compared to the current designs. The presented hardware architecture is optimized to support multiple simultaneous video streams, and high frame rates at High-Definition (HD) resolutions.

High-density wireless intracranial neural recording is a promising technology enabling the autonomous diagnosis and therapy of brain diseases. Increasing the number of recording channels is accompanied by the increased amount of data resulting in an unacceptable transmission power. A comprehensive study of possible compressed sensing methods in the context of neural signals has been done, and the compression of signals originating from different channels in the spatial domain has been implemented at the system and circuit levels. Results of the simulations in a UMC 0.18μm CMOS technology and subsequent reconstructions show the possibility of compressing with ratios as high as 2.6 with a recovery SNR of at least 10dB using extremely compact and low-power circuits. The power efficiency and limited area per channel confirm the relevance of the proposed approach for multi-channel high-density neural interfaces.

Stereo image rectification is a pre-processing step of disparity estimation intended to remove image distortions and to enable stereo matching along an epipolar line. A real-time disparity estimation system needs to perform real-time rectification which requires solving the models of lens distortions, image translations and rotations. Look-up-table based rectification algorithms allow image rectification without demanding high complexity operations. However, they require an external memory to store large size look-up-tables. In this work, we present an intermediate solution that compresses the rectification information to fit the look-up-table into the on-chip memory of a Virtex-5 FPGA. The low-complexity decompression process requires a negligible amount of hardware resources for its real-time implementation. The proposed image rectification hardware consumes 0.28% of the DFF and 0.32% of the LUT resources of the Virtex-5 XCUVP-110T FPGA, it can process 347 frames per second for a 1024×768 pixels image resolution, and it does not need the availability of an external memory.

Omnidirectional stereoscopy and depth estimation are complex problems of image processing to which the Panoptic camera offers a novel solution. The Panoptic camera is a biologically-inspired vision sensor made of multiple cameras. It is a polydioptric system mimicking the eyes of flying insects where multiple imagers, each with a distinct focal point, are distributed over a hemisphere. Recently, the omnidirectional image reconstruction algorithm (OIR) and its real-time hardware implementation have been proposed for the Panoptic camera. This paper presents an enhanced omnidirectional image reconstruction algorithm (EOIR) and its real-time implementation. The proposed EOIR algorithm provides improved realistic omnidirectional images and residuals compared to OIR. As a processing core of EOIR, 57% of the available slice resources in a Virtex 5 FPGA are consumed. The proposed platform provides the high bandwidth required to simultaneously process data originating from 40 cameras, and reconstruct omnidirectional images of 256x1024 pixels at 25 fps. This proposed hardware and algorithmic enhancements enable advanced real-time applications including omnidirectional image reconstruction, 3D model construction and depth estimation.

A CMOS imager is presented which has the ability to perform localized compressive sensing on-chip. In-pixel convolutions of the sensed image with measurement matrices are computed in real time, and a proposed programmable two-dimensional scrambling technique guarantees the randomness of the coefficients used in successive observation. A power and area-efficient implementation architecture is presented making use of a single ADC. A 256×256 imager has been developed as a test vehicle in a 0.18μm CIS technology. Using an 11-bit ADC, a SNR of 18.6dB with a compression factor of 3.3 is achieved after reconstruction. The total power consumption of the imager is simulated at 76.7mW from a 1.8V supply voltage.

In this paper a novel approach to optimize digital integrated circuits yield with regards to speed and area/power for aggressive scaling technologies is presented. The technique is intended to reduce the effects of intra-die variations using redundancy applied only on critical parts of the circuit. The inherent property of the technique is that the improvement in the maximum frequency the circuit can run is higher for the larger variations. The work shows that the technique can be already applied for 65nm CMOS technology process where a beneficial delay vs. area/power tradeoff can be made. However, a significant benefit is expected for future nanoscale CMOS technologies such as 45nm and 32nm nodes and in low-voltage applications.

The precise evaluation of the reliability of logic circuits has a significant importance in highly-defective and future nanotechnologies. It allows efficient comparison of fault-tolerance techniques, and enables designs improvement with respect to their reliability figure. This paper presents a novel, accurate and scalable method for modeling the output probability density functions (PDFs) of logic circuits. Our method combines probability theory with concepts from logic synthesis and testing. The PDFs are modeled using the acquired circuit output probability of failure and PDFs of gates in the last two layers of the output cone. Unlike the existing output PDF modeling techniques, the proposed method is directly applicable to standard CMOS design. Simulation results of benchmark circuits demonstrate the accuracy of the method. Several potential applications of the proposed technique include the analysis of averaging (analog) fault-tolerant techniques, fine-grained redundancy insertion, and reliability-driven design optimization.

We present a CMOS imager with built-in capability to perform Compressed Sensing coding by Random Convolution. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to complete the acquisition model. The feasibility of the imager and its robustness under noise and non-linearities have been confirmed by computer simulations, as well as the reconstruction tools supporting the Compressed Sensing theory.

We propose a bio-inspired circuit performing pulse-density modulation with single-electron devices. The proposed circuit consists of three single-electron neuronal units, receiving the same input and are connected to a common output. The output is inhibitorily fedback to the three neuronal circuits through a capacitive coupling, tuned to obtain a winners-share-all network operation. The circuit performance was evaluated through Monte-Carlo based computer simulations. We demonstrated that the proposed circuit possesses noise-shaping characteristics, where signal and noises are separated into low and high frequency bands respectively. This significantly improved the signal-to-noise ratio (SNR) by 4.34 dB in the coupled network, as compared to the uncoupled one. The noise-shaping properties are as a result of i) the inhibitory feedback between the output and the neuronal circuits, and ii) static noises (originating from device fabrication mismatches) and dynamic noises (as a result of thermally induced random tunneling events) introduced into the network.

The prospective use of upcoming nanometer CMOS technology nodes (65 nm, 45 nm, and beyond) in bio-electronic interfaces is raising a number of important issues concerning circuit architectures and design. In particular, the advantages of scaling and higher density integration must be balanced against the requirements of low noise design, uniform power density and surface temperature distribution, better component matching, and immunity to parameter variations. Dealing with these constraints also requires more innovative approaches towards hybrid integration technologies. In this paper, we discuss the key design issues with specific examples from DNA detection, protein detection, and neuro-electronic interfaces.

This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. Characteristics of the averaging/thresholding layer are emphasized. A complete tool based on Monte Carlo simulation for a-priori functional fault tolerance analysis was used for analysis of distinctive cases and topologies. A full chip CMOS integrated design of the 128-bit AES cryptography algorithm with multiple cores that incorporate reliability architectures is shown.

An assessment of the fault-tolerance properties of single-ended and differential signaling is shown in the context of a high defect density environment, using a robust error-absorbing circuit architecture. A software tool based on Monte-Carlo simulations is used for the reliability analysis of the examined logic families. A benefit of the differential circuit over standard single-ended is shown in case of complex systems. Moreover, analysis of reliability of different circuits and discussion on the optimal granularity of redundant blocks was made.

In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our approach is a generic (parametrical) architectural template. Configurable nanostructures for reliable nano electronics (CONAN), which embeds support for reliability at various levels of abstractions. Some of the main reliability sources are regular and decentralized structures based on simple basic computation cells designed to be robust against disturbances and noise, fault tolerance based on hardware, time and information redundancy applied at the basic cell level as well as at higher levels, self diagnosis assisted by the dynamic reconfiguration of basic computation cells and interconnect rerouting. Within the CONAN template, both technology dependent and independent models co-exists such that the more abstract layers are technology independent while the lower levels can be retargeted to various fabrication technologies. Our proposal is application-oriented and allows the designers to deal with unpredictability, and low reliability, which are unavoidable characteristics of future emerging nano-devices. When combined with the underlying software, the tools supporting the CONAN approach allow the designer to check whether the design constraints are fulfilled before performing a detailed implementation and provides means to trade area, delay, and power consumptions for reliability. As such, this proposal is a call-to-arms to mobilize the efforts of systems designers in order to achieve a systematic design methodology for reliable systems.

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In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The fundamental principles of a highly regular, redundant, and scalable design approach based on fixed-weight neural networks and multiple-valued logic are presented. It is demonstrated that the proposed design technique offers significantly improved immunity to permanent and transient faults occurring at the transistor level, and that it results in graceful degradation of circuit performance in response to device failures.

A novel circuit-level Hamming artificial neural network architecture based on the principle of analog charge-based computation of the neural function is proposed. k-winner-take-all and k-loser-take-all operations are performed in the time-domain, allowing for fast and compact realization of complex functions. The VLSI realization of a two-dimensional array arrangement of the Hamming network is presented, with the targeted processing applications.

A circuit-level neuron architecture based on the principle of analog charge-based computation of neural functions has been developed with the goals of high-speed processing, adjustable weights, and support of perturbation-based learning algorithms. The two-stage architecture which is composed of nonlinear synapses, driving a linear capacitive soma, has been implemented using a conventional double-polysilicon CMOS technology. The feedforward architecture of the proposed neuron model is shown to synthesize a large number of nonlinear mappings of the 2D-1D space.