In modern automobiles, a Controller Area Network (CAN) bus facilitates communication among all electronic control units for critical safety functions, including steering, braking, and fuel injection. However, due to the lack of security features, it may be vulnerable to malicious bus traffic-based attacks that cause the automobile to malfunction. Such malicious bus traffic can be the result of either external fabricated messages or direct injection through the on-board diagnostic port, highlighting the need for an effective intrusion detection system to efficiently identify suspicious network flows and potential intrusions. This work introduces Residually Interconnected and Superimposed Kolmogorov-Arnold Networks (RISK-4-Auto), a set of four deep neural network architectures for intrusion detection targeting in-vehicle network traffic classification. RISK-4-Auto models, when applied on three hexadecimally identifiable sequence-based open-source datasets (collected through direct injection in the on-board diagnostic port), outperform six state-of-the-art vehicular network intrusion detection systems (as per their accuracies) by ≈1.0163% for all-class classification and ≈2.5535% on focused (single-class) malicious flow detection. Additionally, RISK-4-Auto enjoys a significantly lower overhead than existing state-of-the-art models, and is suitable for real-time deployment in resource-constrained automotive environments.

Aluminum electrolytic capacitors play a critical role in power electronics, where degradation under storage conditions poses reliability challenges for long-lifecycle systems in defense, avionics, and industrial applications. This research introduces the physics-of-failure-informed neural network (PoFINN), which integrates electrolyte evaporation physics with neural architectures for accurate degradation forecasting. Existing approaches struggle with limited data, nonstationary patterns, and physically implausible predictions.PoFINNaddresses these limitations through two key innovations: an embedded first-principles evaporation model capturing capacitance loss through mass balance equations and a dual-phase training methodology. This approach initializes long short-term memory weights using simulated physical data, and then refines parameters with empirical measurements. A parametric hybrid loss function balances physical constraints with data errors, maintaining plausibility while optimizing accuracy. Experimental validation showsPoFINNoutperforms conventional forecasting approaches, achieving error reductions of 27%–81% across all time horizons compared to statistical, neural, and ensemble techniques. The most substantial improvements (70%–80%) are observed against recurrent architectures, with advantages more pronounced in long-term forecasting. Performance remains robust across different train–test splits (50–50, 60–40, and 70–30), highlightingPoFINN’s effectiveness with limited data—addressing a critical challenge in degradation prediction. The methodology shows immediate practical value for inventory management in reliability-critical sectors and potential applicability to other components, improving maintenance planning and replacement decisions.

An Arbiter PUF (APUF) is a useful hardware security primitive. However, FPGA-based design and implementation of APUF circuits with superior values of quality metrics have proven to be extremely challenging. In this work, we have designed a novel 64-bit APUF which is "robust-by-construction", i.e., it has close to ideal values of quality metrics when implemented. The circuit structure and methodical implementation on a Xilinx FPGA platform ensure that the response bit is unbiased, and is dependent on intrinsic process variation alone. The effect of placement and routing tools and the choice of last-stage arbiters have been investigated in detail. Our implemented APUF achieves average Uniformity, Uniqueness, Steadiness, Min-Entropy, and Reliability (evaluated at four operating temperatures) metric values of 51.22%, 50.81%, 1.82%, 88.38%, and 99.34%, respectively. A software-based fuzzy error correction scheme is used on the responses generated at different temperatures. The design is also found to be strongly resistant to machine learning based model-building attacks, with Logistic Regression (LR) and Support Vector Machine (SVM) prediction accuracies of 51.22% and 52.61% respectively, on a dataset of 2,097,152 CRPs using additive delay models and a security analysis is performed using MLP modelling-attacks of the pypuf framework.

The advancement of artificial intelligence (AI) has led to its application to a broad spectrum of complex problems associated with everyday life. AI is extensively deployed in many daily applications through dedicated hardware accelerators, in several safety-critical security-sensitive systems, e.g. self-driving cars, smart home devices, health monitoring apps, bio-metric access control, public surveillance systems, etc. However, several recent studies have demonstrated that these hardware-centric AI applications are susceptible to diverse attacks, with great potential to cause harm. To mitigate such threats, many works have focused on developing effective countermeasures for different attack scenarios, to design robust AI-based system. This paper surveys different potent and imaginative attacks on AI hardware, and countermeasures to mitigate them. We analyse various threat models, and provide a detailed discussion of the challenges of attacks and the efficacy of various countermeasures. We also point to future directions of research.

Cryptographic systems employing SRAM-based Physically Unclonable Functions (SRAM-PUFs) rely on the assumption that modelling the internal PUF state is practically infeasible. This work investigates the modelling prowess of an adversary with access to side-channel information collected from similar, albeit not identical, devices to develop templates for leakages. To the best of our knowledge, this is the first work to show the modelling vulnerability of SRAM-PUFs to side-channel leakages by utilizing the correlation between power, electromagnetic signatures obtained from similar devices with identical patterns in their PUF responses. To evaluate the effectiveness of our attack, we perform extensive experiments on ATmega328P and demonstrate a maximum accuracy of 98.45% in the Hamming Weight ( <?TeX $\mathsf {HW}$?> Math 2 ) prediction of the PUF responses and <?TeX $96.91\%$?> Math 3 for the exact PUF response over 50 target devices. Our attack’s feasibility also extends to newer technology nodes, as validated on the 32-bit ARM Cortex M0+. Additionally, we augment the well-known helper data induced min-entropy loss to factor in the effect of side-channels and show that the residual entropy per byte of SRAM-PUF reduces significantly due to <?TeX $\mathsf {HW}$?> Math 4 leakage. Lastly, we propose an in-situ masking countermeasure using SRAM metastable cells, that effectively randomizes the side-channel signatures and reduces the <?TeX $\mathsf {HW}$?> Math 5 prediction accuracy to <?TeX $< 30\%$?> Math 6 .

Static random access memory (SRAM)-based physically unclonable functions (PUFs) utilize unpredictable start-up values (SUVs) for key generation, making them widely adopted in cryptographic systems. This unpredictability in SUVs is accompanied by device noise that escalates with process-voltage–temperature (PVT) variations, resulting in significant deviations from the golden response collected at ambient conditions, thereby increasing the bit-error-rate (BER) of the PUF responses. To reduce this high-$(\geq 15\%)$BER, either an involved error correcting code (ECC) circuitry with significant overhead is required, or more helper information needs to be generated at varying operating conditions, resulting in increased information leakage. We address this issue by proposing the first reported application of machine learning to recalibrate the responses by predicting the golden responses of the SRAM-based PUF (SRAM-PUF) at different operating conditions with high accuracy. Our recalibration technique is based on a novel collective decision that involves observing the neighborhood cells of the SRAM-PUF, as opposed to the traditional single-cell approach. By leveraging a memory map exhibiting a high correlation in ambient reliability amongst neighboring cells, we indirectly use the physical co-location of SRAM cells to assist neighborhood error prediction. It leads to efficient post-processing for SRAM-PUFs by using helper data generated at ambient conditions only while employing a fixed ECC designed for the same. Subsequently, to justify our claims and validate the efficacy of our proposed methodology, we demonstrate extensive experimentation results over multiple SRAM-PUF instances implemented on the Arduino UNO (an 8-bit microcontroller unit) and its scaled-up version, the Arduino Zero (a 32-bit microcontroller unit) boards, by varying supply voltages from 3.8 to 6.2 V and 7 to 12 V, respectively, and temperature from −25° to 70° C in both cases. Our observations show a vast drop in BER from 17.02% to$\approx 1\%$. Although worst-case conditions with both voltage and temperature variations at play resulted in a BER of 20%, using our proposed approach reduces it to$\approx 1{\text {-}} 2\%$, in turn demonstrating the high efficacy of our scheme.

NIST’s recent review of the widely employed special publication (SP) 800–22 randomness testing suite has underscored several shortcomings, particularly the absence of entropy source modeling and the necessity for large sequence lengths. Motivated by this revelation, we explore low-dimensional modeling of the entropy source in random number generators (RNGs) using a variational autoencoder (VAE). This low-dimensional modeling enables the separation between strong and weak entropy sources by magnifying the deterministic effects in the latter, which are otherwise difficult to detect with conventional testing. Bits from weak-entropy RNGs with bias, correlation, or deterministic patterns are more likely to lie on a low-dimensional manifold within a high-dimensional space, in contrast to strong-entropy RNGs, such as true RNGs (TRNGs) and pseudo-RNGs (PRNGs) with uniformly distributed bits. We exploit this insight to employ a generative AI-based noninterference test (GeNI) for the first time, achieving implementation-agnostic low-dimensional modeling of all types of entropy sources. GeNI’s generative aspect uses VAEs to produce synthetic bitstreams from the latent representation of RNGs, which are subjected to a deep learning (DL)-based noninterference (NI) test evaluating the masking ability of the synthetic bitstreams. The core principle of the NI test is that if the bitstream exhibits high-quality randomness, the masked data from the two sources should be indistinguishable. GeNI facilitates a comparative analysis of low-dimensional entropy source representations across various RNGs, adeptly identifying the artificial randomness in specious RNGs with deterministic patterns that otherwise passes all NIST SP800-22 tests. Notably, GeNI achieves this with$10\times $lower-sequence lengths and$16.5\times $faster execution time compared to the NIST test suite.

Modern integrated circuit (IC) design incorporates the usage of proprietary computer-aided design (CAD) software and integration of third-party hardware intellectual property (IP) cores. Subsequently, the fabrication process for the design takes place in untrustworthy offshore foundries that raises concerns regarding security and reliability. Hardware Trojans (HTs) are difficult to detect malicious modifications to IC that constitute a major threat, which if undetected prior to deployment, can lead to catastrophic functional failures or the unauthorized leakage of confidential information. Apart from the risks posed by rogue human agents, recent studies have shown that high-level synthesis (HLS) CAD software can serve as a potent attack vector for inserting HTs. In this article, we introduce a novel automated attack vector, which we term “HLS-IRT”, by inserting HT in the register transfer logic (RTL) description of circuits generated during an HLS based IC design flow, by directly modifying the compiler-generated intermediate representation (IR) corresponding to the design. We demonstrate the attack using a design and implementation flow based on the open-source Bambu HLS software and Xilinx FPGA, on several hardware accelerators spanning different application domains. Our results show that the resulting HTs are surreptitious and effective, while incurring minimal design overhead. We also propose a novel detection scheme for HLS-IRT, since existing techniques are found to be inadequate to detect the proposed HTs.

Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are two highly useful hardware primitives to build up the root-of-trust for embedded devices in Internet-of-Things and Cyber-Physical System applications. These applications demand the primitives be lightweight, yet flexible. However, PUFs are designed to offerrepetitive and instance-specificrandomness, whereas TRNGs are expected to beinvariablyrandom. A challenging but thought-provoking problem from a hardware designer's perspective would be to design a circuit that serves the purpose of both PUF and TRNG depending on the exact requirement of the application. Here, we present a dual-mode PUF-TRNG design that utilises two different hardware-intrinsic properties, i.e., oscillatory metastability of Transition Effect Ring Oscillator (TERO) cell and propagation delay of a buffer within the cell to achieve this goal. A 48.62% reduction in area is accomplished due to the integration in comparison to separate instances of standalone PUFs/ TRNG designs, built from Programmable Delay Line (PDL) based Arbiter PUFs (APUFs) and TERO-TRNG. Our final design has a hardware footprint of 618 Look-Up Tables (LUTs) and 447 Flip-Flops (FFs). Furthermore, experimental analysis of the state-of-the-art modelling attacks, reliability attacks on the proposed PUF design shows a prediction accuracy of 55.37% and 50.14% respectively for 5.2M Challenge Response Pairs (CRPs). Additionally, the TRNG passes evaluation through National Institute of Standards and Technology (NIST) Special Publication (SP) 800-22 and German Federal Office for Information Security (BSI) Application Notes and Interpretation of the Scheme (AIS)-31 tests.

With the rapid increase in the development of deep learning methodologies, deep neural networks (DNNs) are now being commonly deployed in smart systems (e.g., autonomous vehicles) and high-end security applications (e.g., face recognition, biometric authentication, etc.). The training of such DNN models often requires exclusive valuable training datasets, enormous computational resources, and expert fine-tuning skills. Hence, a trained DNN model can be regarded as valuable proprietary intellectual property (IP). Piracy of such DNN IPs has emerged as a major concern, with increasing trends of illegal copying and redistribution. A number of mitigation approaches targeting DNN IP protection have been proposed in recent years. In this work, we target two recently proposed DNN IP protection schemes: 1) chaotic map theory-based encryption of the weight parameters and 2) traditional block cipher-based encryption of the weights. We demonstrate attacks on two recent DNN IP protection techniques, with one technique each belonging to the above-mentioned schemes, under a pragmatic attack model. We also propose a novel DNN IP protection technique based on selective encryption of the weight parameters, termed limited encryption of weights for IP protection (LEWIP) to mitigate the exposed weaknesses, while having low implementation and performance overheads. Finally, we demonstrate the effectiveness of the LEWIP technique against state-of-the-art DNN implementations.

The globalization of the integrated circuit (IC) manufacturing industry has lured the adversary to come up with numerous malicious activities in the IC supply chain. Logic locking has risen to prominence as a proactive defense strategy against such threats. CAS-Lock (proposed in CHES'20), is an advanced logic locking technique that harnesses the concept of single-point function in providing SAT-attack resiliency. It is claimed to be powerful and efficient enough in mitigating existing state-of-the-art attacks against logic locking techniques. Despite the security robustness of CAS-Lock as claimed by the authors, we expose a serious vulnerability and by exploiting the same we devise a novel attack algorithm against CAS-Lock. The proposed attack can not only reveal the correct key but also the exact AND/OR structure of the implemented CAS-Lock design along with all the key gates utilized in both the blocks of CAS-Lock. It simply relies on the externally observable Distinguishing Input Patterns (DIPs) pertaining to a carefully chosen key simulation of the locked design without the requirement of structural analysis of any kind of the locked netlist. Our attack is successful against various AND/OR cascaded-chain configurations of CAS-Lock and reports 100% success rate in recovering the correct key. It has an attack complexity of$\mathcal{O}(m)$, where$m$denotes the number of DIPs obtained for an incorrect key simulation.

Physically unclonable functions (PUFs) which are robust to modeling attacks, usually have a complex, high-dimensional, nonlinear relationship between challenges and responses. Often, it is difficult to derive closed-form analytical expressions for these relationships. Consequently, it becomes difficult to compare PUF variants with regard to their robustness to modeling attacks. In this article, we apply a data-driven empirical metric termed the intrinsic dimension (ID), to estimate theinherent complexityof the relationship between the challenges and responses of a given PUF variant. This metric is computed from the linear projection layer of a deep neural network (DNN) aimed at modeling the PUF and has a unique advantage that it is independent of the architectural details and chosen hyperparameters of the DNN. It also does not require the knowledge of the structural and functional details of the PUF. The proposed approach is evaluated using two well-known ID estimation methods based on thenearest neighbor methodand the full correlation integral (FCI). Through detailed experimental results, we demonstrate that the numerical values of the FCI-based ID metric for different types of PUFs have consistently high positive correlation with the perceived difficulty of modeling several common PUF variants. We also show that the ID metric provides deep insight about various subtleties that affect the robustness of PUFs to modeling attack and provides a convenient mechanism to perform a systematic comparison between different PUF compositions.

Secure authentication of any Internet-of-Things (IoT) device becomes the utmost necessity due to the lack of specifically designed IoT standards and intrinsic vulnerabilities with limited resources and heterogeneous technologies. Despite the suitability of arbiter physically unclonable function (APUF) among other PUF variants for the IoT applications, implementing it on field-programmable gate arrays (FPGAs) is challenging. This work presents the complete characterization of the path changing switch (PCS) 1 based APUF on two different families of FPGA, like Spartan-3E (90 nm CMOS) and Artix-7 (28 nm CMOS). A comprehensive study of the existing tuning concept for programmable delay logic (PDL) based APUF implemented on FPGA is presented, leading to establishment of its practical infeasibility. We investigate the entropy, randomness properties of the PCS based APUF suitable for practical applications, and the effect of temperature variation signifying the adequate tolerance against environmental variation. The XOR composition of PCS based APUF is introduced to boost performance and security. The robustness of the PCS based APUF against machine learning based modeling attack is evaluated, showing similar characteristics as the conventional APUF. Experimental results validate the efficacy of PCS based APUF with a little hardware footprint removing the paucity of lightweight security primitive for IoT.

Analysis of Physically Unclocnable Functions (PUFs) from a Boolean function perspective, and the efficient hardware implementation of such Boolean representations, can potentially lead to interesting insights about their behavior and robustness. Such a circuit implementation can also be a convenient substitute for the machine learning model of a PUF instance in PUF-based security protocols. In this paper, we present APUF-BN, a novel computer-aided design (CAD) framework to efficiently generate a combinational circuit representation of an Arbiter PUF (APUF) instance, which accurately mimics its input-output behavior. This representation is derived from an optimized fully-connected Binarized Neural Network (BNN) model of the APUF. Our fully-automated CAD framework takes challenge-response pairs (CRPs) of an APUF instance as input, and generates Verilog description corresponding to the optimized combinational circuit representation as output. The optimized Boolean logic representation achieves more than 24% reduction in area overhead compared to the unoptimized BNN representation, while achieving close to 98% modeling accuracy. We also validate the derived combinational circuit representation on Xilinx Artix-7 FPGA platform.

The skyrocketing cost of integrated circuit (IC) manufacturing has forced the majority of enterprises to shift to fabless operation. IC design is often outsourced to foreign fabrication laboratories to reduce time and cost However, as a flip-side, it has introduced various hardware security concerns at different stages in the supply chain, namely, IP piracy, illegal overproduction, design counterfeiting, etc. Logic locking has risen to prominence as a proactive defense strategy against such threats. The basic idea of logic locking is to obscure the actual design to an adversary by integrating additional key-based logic into the original design. The authors in [1] have proposed an obfuscation scheme using a class of non-group additive cellular automata (CA) called $D1 * CA$ and $D1 * CA_{dual}$ to obfuscate each state-transition of an FSM. We propose a novel attack (named ORACALL) to extract the secret key used to obfuscate each FSM state-transition. We further propose a novel logic locking technique [2] which harnesses the security of block ciphers. It is found to be secure against known existing attacks.

In logic locking, the finite-state machine (FSM) embedded in a sequential circuit is often chosen to be obfuscated. Such an obfuscation scheme using a class of nongroup additive cellular automata (CA) called$D1 * CA$and$D1 * CA_{\mathrm{ dual}}$to obfuscate each state transition of an FSM has been proposed previously. Since$D1 * CA$and$D1 * CA_{\mathrm{ dual}}$provide high testability even in the absence of scan-based design-for-testability techniques, they conceal the sequential elements, thus thwarting several existing scan-chain attacks. In this article, we introduce a novel attack to extract the secret key used to obfuscate each state transition of the FSM, by utilizing the information leaked by the leftmost CA cell, which is obtained via an oracle query to the obfuscated circuit. The proposed attack has two variants: 1) when the combinational circuit of theInterrupt Logicis not logic encrypted and 2) when theInterrupt Logicis logic encrypted with a$k$-bit key. The first attack variant has a complexity of$\mathcal {O}(n \cdot m)$, where$n$denotes the number of transitions in the FSM, and$m$denotes the maximum transition cycle length of the underlying$D1 * CA$. The second attack variant has a complexity of$\mathcal {O}(n\cdot q_{\mathrm{ max}})$, where$q_{\mathrm{ max}}$denotes the maximum number of oracle queries (equal to the number of primary inputs involved in that state transition), followed by a SAT-attack to extract the$k$-bit key of the correspondingInterrupt Logic. The experimental evaluation of the attack on CA-based obfuscated benchmark circuits establishes the effectiveness of our proposed attack.

XOR arbiter PUF (XOR APUF), where the outputs of multiple arbiter PUF (APUFs) are XOR-ed, has proven to be more robust to machine learning-based modeling attacks. The reported successful modeling attacks for XOR APUF either employ auxiliary side-channel or reliability information, or require enormous computational effort. This robustness is primarily due to the difficulty in learning the unknown internal delay parameter terms in the mathematical model of a XOR APUF, and the robustness increases as the number of APUFs being XOR-ed increases. In this article, we employ a novel machine learning-based modeling technique called efficient CANDECOMP/PARAFAC-tensor regression network (CP-TRN), a variant of CP-decomposition-based tensor regression network, to reduce the computational resource requirement of model building attacks on XOR APUF. We theoretically prove the reduction in computational complexity, as well as give supporting experimental results. In addition, our proposed technique does not require any auxiliary information, and is robust to noisy training data. The proposed technique allowed us to successfully model 64-bit 8-XOR APUF and 128-bit 7-XOR APUF on a single desktop workstation, with high prediction accuracy. Further, we extend the proposed modeling attack technique to XOR APUF variants, e.g., lightweight secure PUF (LSPUF), which rely on input challenge transformation. The modeling accuracy results obtained by us for the LSPUF are comparable with those obtained by applying other state-of-the-art techniques, while requiring less training data.

Anonymous authentication (AA) schemes are used by an application provider to grant services to its n users for pre-defined k times after they have authenticated themselves anonymously. These privacy-preserving cryptographic schemes are essentially based on the secret key that is embedded in a trusted platform module (TPM). In this work, we propose a private physically unclonable function (PUF) based scheme that overcomes the shortcomings of prior attempts to incorporate PUF for AA schemes. Traditional PUF based authentication protocols have their limitations as they only work based on challenge-response pairs (CRPs) exposed to the verifier, thus violating the principle of anonymity. Here, we ensure that even if the PUF instance is private to the user, it can be used for authentication to the application provider. Besides, no raw CRPs need to be stored in a secure database, thus making it more difficult for an adversary to launch model-building attacks on the deployed PUFs. We reduce the execution time from O(n) to O(1) and storage overhead from O(nk) to O(n) compared to state-of-the-art AA protocols and also dispense the necessity of maintaining a revocation list for the compromised keys. In addition, we provide security proofs of the protocol under Elliptic Curve Diffie-Hellman assumption and decisional uniqueness assumption of a PUF. A prototype of the protocol has been implemented on a Z-Turn board integrated with dual-core ARM CortexA9 processor and Artix-7 FPGA. The resource footprint and performance characterization results show that the proposed scheme is suitable for implementation on resource-constrained platforms.

Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning–based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic , and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants—the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.

Reversible image watermarking is a technique that allows the cover image to remain unmodified after watermark extraction. Prediction error expansion-based schemes are currently the most efficient and widely used class of reversible image watermarking techniques. In this paper, first, we prove that the bounded capacity distortion minimization problem for prediction error expansion-based reversible watermarking schemes is NP-hard, and the corresponding decision version of the problem is NP-complete. Then, we prove that the dual problem of bounded distortion capacity maximization problem for prediction error expansion-based reversible watermarking schemes is NP-hard, and the corresponding decision problem is NP-complete. Furthermore, taking advantage of the integer linear programming formulations of the optimization problems, we find the optimal performance metric values for a given image, using concepts from the optimal linear prediction theory. Our technique allows the calculation of these performance metric limit without assuming any particular prediction scheme. The experimental results for several common benchmark images are consistent with the calculated performance limits validate our approach.

Remote integrity verification plays a paramount role in resource-constraint devices owing to emerging applications such as Internet-of-Things (IoT), smart homes, e-health, and so on. The concept of Virtual Proof of Reality (VPoR) proposed by Rührmair et al. in 2015 has come up with a Sense-Prove-Validate framework for integrity checking of abundant data generated from billions of connected sensors. It leverages the unreliability factor of Physically Unclonable Functions (PUFs) with respect to ambient parameter variations such as temperature, supply voltages, and so on, and claims to prove the authenticity of the sensor data without using any explicit keys. The state-of-the-art authenticated sensing protocols majorly lack in limited authentications and huge storage overhead. These protocols also assume that the behaviour of the PUF instances varies unpredictably for different levels of ambient factors, which in turn makes them hard to go beyond the theoretical concept. We address these issues in this work 1 and propose a Machine Learning (ML) assisted PUF calibration scheme to predict the Challenge-Response Pair (CRP) behaviour of a PUF instance in a specific environment, given the CRP behaviour in a pivot environment. Here, we present a new class of authenticated sensing protocols where we leverage the beneficence of ML techniques to validate the authenticity and integrity of sensor data over ambient factor variations. The scheme also reduces the storage complexity of the verifier from O ( p * K * l * ( c + r )) to O ( p * l *( c + r )), where p is the number of PUF instances deployed in the framework, l is the number of challenge-response pairs used for authentication, c is the bit lengths of the challenge, r is the response bits of the PUF, and K is the number of levels of ambient factor variations. The scheme alleviates the issue of limited authentication as well, whereby every CRP is used only once for authentication and then deleted from the database. To validate the proposed protocol through actual experiments on FPGA, we propose 5-4 Double Arbiter PUF, which is an extension of Double Arbiter PUFs (DAPUFs) as this design is more suited for FPGA, and implement it on Xilinx Artix-7 FPGAs. We characterise the proposed PUF instance from −20° C to 80° C and use Random Forest --based ML technique to generate a soft model of the PUF instance. This model is further used by the verifier to authenticate the actual PUF circuit. According to the FPGA-based validation, the proposed protocol with DAPUF can be effectively used to authenticate sensor devices across wide variations of temperature values.

With the large-scale adaptation of a "horizontal" business model, modern semiconductor supply chain is plagued by recycled and counterfeit ICs, including flash memory chips. Since flash memory modules have an inherently finite lifespan, detection of recycled flash memory chips before their deployment in safety-critical systems is important to prevent disastrous consequences. The state-of-art detection methods can detect flash memory modules between 0.05% to 3.00% of their lifespan as minimum usage duration, depending on the details of the flash memory chip. In this paper, we propose a versatile machine learning assisted detection methodology to improve the minimum usage duration accuracy between 0.05% to 0.96% of their lifespan, and also to accurately associate a flash memory IC with its manufacturer. Through detailed experimentation and comparison of detection results obtained using three popular supervised machine learning techniques (Support Vector Machines, Logistic Regression and Artificial Neural Networks), we demonstrate that usage of features composed of multiple characteristics of a given chip, rather than just a single property of a chip (as used in previous works), improves detection accuracy.

This work proposes a scheme to detect, isolate and mitigate malicious disruption of electro-mechanical processes in legacy PLCs where each PLC works as a finite state machine (FSM) and goes through predefined states depending on the control flow of the programs and input-output mechanism. The scheme generates a group-signature for a particular state combining the signature shares from each of these PLCs using (k,l)-threshold signature scheme. If some of them are affected by the malicious code, signature can be verified by k out of l uncorrupted PLCs and can be used to detect the corrupted PLCs and the compromised state. We use OpenPLC software to simulate Legacy PLC system on Raspberry Pi and show I/O pin configuration attack on digital and pulse width modulation (PWM) pins. We describe the protocol using a small prototype of five instances of legacy PLCs simultaneously running on OpenPLC software. We show that when our proposed protocol is deployed, the aforementioned attacks get successfully detected and the controller takes corrective measures. This work has been developed as a part of the problem statement given in the Cyber Security Awareness Week-2017 competition.

Cyclic logic encryption currently constitutes the most robust technique against Boolean satisfiability (SAT) based attacks on logic encryption; however, recent "Cyclic SAT" (CycSAT) attacks have overcome this resistance to a large scale. In this paper we develop an improved version of cyclic logic encryption using a common permutation network (the "Beneš network"). The cyclic nature is implemented by channeling some of the keys of the permutation network through the permutation network itself, and feeding them back to the target nodes instead of direct connection. It is observed that although the standalone Beneš network is highly susceptible to SAT based attacks, the proposed architecture has the two properties required for it to be immune to SAT attack, namely oscillatory and stateful. We also show that the procedure of enumerating cycles without node duplicity ("simple cycles") during the preprocessing step of CycSAT attacks, as considered in some previous works, is not technically correct; instead, we should consider cycles without edge duplicity. We then prove that the number of cycles without edge duplicity in our proposed technique grows as Ω(n!(n – 1)!), where n is the number of feedback paths. The logic synthesis tool distributes the different stages of our proposed network across the obfuscated circuit, thereby making it immune to trivial netlist tracing based detection and removal attacks. The robustness of the technique to the CycSAT attack has been validated for ISCAS-85 benchmark circuits.

Recently, antiforensic methods have been proposed that invalidate most of the state-of-the-art median filter digital image forensic techniques. Also, the existing counter antiforensic methods decline noticeably when evaluated on small-sized patches in JPEG compressed images. In this letter, we have developed a robust residual dense (Neural) network-based counter antiforensic median filter detection technique that exploits local dense connection and residual learning of features for improved classification of images. Experimental results demonstrate that the proposed approach achieves superior performance to state-of-the-art techniques in detecting forgeries, even in small patches, in JPEG compressed images, for both median filtered and antiforensic median filtered images.

Physically Unclonable Functions (PUFs) promise to be a critical hardware primitive to provide unique identities to billions of connected devices in Internet of Things (IoTs). In traditional authentication protocols a user presents a set of credentials with an accompanying proof such as password or digital certificate. However, IoTs need more evolved methods as these classical techniques suffer from the pressing problems of password dependency and inability to bind access requests to the “things” from which they originate. Additionally, the protocols need to be lightweight and heterogeneous. Although PUFs seem promising to develop such mechanism, it puts forward an open problem of how to develop such mechanism without needing to store the secret challenge-response pair (CRP) explicitly at the verifier end. In this paper, we develop an authentication and key exchange protocol by combining the ideas of Identity based Encryption (IBE), PUFs and Key-ed Hash Function to show that this combination can help to do away with this requirement. The security of the protocol is proved formally under the Session Key Security and the Universal Composability Framework. A prototype of the protocol has been implemented to realize a secured video surveillance camera using a combination of an Intel Edison board, with a Digilent Nexys-4 FPGA board consisting of an Artix-7 FPGA, together serving as the IoT node. We show, though the stand-alone video camera can be subjected to man-in-the-middle attack via IP-spoofing using standard network penetration tools, the camera augmented with the proposed protocol resists such attacks and it suits aptly in an IoT infrastructure making the protocol deployable for the industry.

Wide proliferation of counterfeit integrated circuits (ICs) is a major global threat. Currently, the process of counterfeit IC detection is time-consuming and requires highly skilled subject matter experts. In this paper, we have developed an automated image-processing-based methodology for recycled and remarked counterfeit IC detection, using images acquired through an ordinary optical microscope or a digital camera. The methodology has two phases: first, identification of counterfeit IC is attempted by package texture comparison of a golden IC sample and the given sample. Then, for the ICs which have not been inferred to be counterfeit, an optional second phase where detection of position and size of indents (or cavities) on the IC package surface is performed. Compared to previously proposed techniques, the proposed technique is less computationally expensive and avoids expensive equipment such as a scanning electron microscope or X-ray tomograph. Experimental results demonstrate that the proposed methodology achieves high detection accuracy, and the results are supported by an unsupervised clustering approach.

The Internet of Things (IoT) is envisaged to consist of billions of connected devices coupled with sensors which generate huge volumes of data enabling control-and-command in this paradigm. However, integrity of this data is of utmost concern, and is promisingly addressed leveraging the inherent unreliability of Physically Unclonable Functions (PUFs) w.r.t. ambient parameter variations, using the concept of Virtual Proofs (VPs). Advantage of these protocols is that they do not use explicit keys and aim at proving the authenticity of the sensor. Since the existing PUF-based protocols do not use the sensor data as a part of challenge (i.e. input) to PUFs, there is no guarantee of uniqueness of PUF's challenge-response behavior over multiple levels of ambient parameters. Few of these protocols needs to sequential search in the challenge-response database. To alleviate these issues, we develop a new class of authenticated sensing protocols where the sensor data is combined with the external challenge by utilizing the Strict Avalanche Criterion of the PUF. We validate the proposed protocol through actual experiments on FPGA using Double Arbiter PUFs (DAPUFs), which are implemented with superior uniformity, uniqueness, and reliability on Xilinx Artix-7 FPGAs. According to the FPGA-based validation, the proposed protocol with DAPUF can be effectively used to authenticate wide variations of temperature from -20°C to 80°C.

Differential Fault Analysis (DFA), aided by sophisticated mathematical analysis techniques for ciphers and precise fault injection methodologies, has become a potent threat to cryptographic implementations. In this paper, we propose, to the best of the our knowledge, the first “DFA-aware” physical design automation methodology, that effectively mitigates the threat posed by DFA. We first develop a novel floorplan heuristic, which resists the simultaneous corruption of cipher states necessary for successful fault attack, by exploiting the fact that most fault injections are localized in practice. Our technique results in the computational complexity of the fault attack to shoot up to exhaustive search levels, making them practically infeasible. In the second part of the work, we develop a routing mechanism, which tackles more precise and costly fault injection techniques, like laser and electromagnetic guns. We propose a routing technique by integrating a specially designed ring oscillator based sensor circuit around the potential fault attack targets without incurring any performance overhead. We demonstrate the effectiveness of our technique by applying it on state of the art ciphers.

Arbiter Physically Unclonable Functions (APUFs), while being relatively lightweight, are extremely vulnerable to modeling attacks. Hence, various compositions of APUFs such as XOR APUF and Lightweight Secure PUF have been proposed to be secure alternatives. Previous research has demonstrated that PUF compositions have two major challenges to overcome: vulnerability against modeling and statistical attacks, and lack of reliability. In this paper, we introduce a multiplexer-based composition of APUFs, denoted as MPUF, to simultaneously overcome these challenges. In addition to the basic MPUF design, we propose two MPUF variants namely cMPUF and rMPUF to improve the robustness against cryptanalysis and reliability-based modeling attack, respectively. An rMPUF demonstrates enhanced robustness against the reliability-based modeling attack, while even the well-known XOR APUF, otherwise robust to machine learning based modeling attacks, has been modeled using the same technique with linear data and time complexities. The rMPUF can provide a good trade-off between security and hardware overhead while maintaining a significantly higher reliability level than any practical XOR APUF instance. Moreover, MPUF variants are the first APUF compositions, to the best of our knowledge, that can achieve Strict Avalanche Criterion without using any additional input network (or hardware) for challenge transformation. Finally, we validate our theoretical findings using Matlab-based simulations of MPUFs.

The widespread penetration of counterfeit integrated circuits (ICs) is not only a major threat to the electronic goods supply chain, but also constitute a great threat to national security. Image processing based counterfeit IC design techniques are promising, but currently often suffer from high computational complexity and requirement of expensive image acquisition infrastructure. We describe two techniques based on image texture analysis to automate the process of counterfeit IC detection. The first method employs local textural feature identification to detect counterfeit ICs. The second method includes identification of counterfeit ICs by segmenting the image into regions of different textural features using texture filters. The first method is of lower computational complexity compared to the segmentation method, but the second method is capable of blind identification in the sense that it does not require knowledge of the textural features of a golden IC sample. Our experimental results show that these methods have high detection accuracy, even for images acquired using ordinary digital cameras and low-end digital microscopes.

PUF-PRFs are Pseudorandom Functions (PRFs) constructed using Physically Unclonable Functions (PUFs) as a hardware building block to provide the random input-output mapping. Since PUF-PRFs inherit all the principal properties of PUFs such as memory-leakage resilience, unclonablity, tampering-resistance, pseudo-randomness, and provable security, PUF-PRFs hold great promise as an extremely useful cryptographic hardware primitive. In this paper, we evaluate the security of PUF-PRFs against Side Channel Attacks. Two different attacks based on analysis of power side channel are developed, and demonstrated through the experiments on Xilinx FPGAs. In addition, we reduce the complexity of Correlation Power Analysis (CPA) to recover n-bit secret, from O(2 2n) to O(3n 2n). Based on our experimental results, we conclude that the security of PUF-PRFs, when subjected to side channel attacks, depends on not only the security of the used PUFs, but also the PUF-PRF architecture.

Copy-Move Forgery Detection (CMFD) is a well-studied image forensics problem. However, CMFD with Similar but Genuine Objects (SGO) has received relatively less attention. Recently, it has been found that current state-of-the-art CFMD techniques are mostly inadequate in satisfactorily solving this important problem variant. In this paper, we have addressed this issue by using Rotated Local Binary Pattern (RLBP) based rotation-invariant texture features, followed by Generalized Two Nearest Neighbourhood (g2NN) based feature matching, hierarchical clustering and geometric transformation estimation. Experimental results show that our technique outperforms the state-of-the-art CFMD techniques for forged images having similar but genuine objects, and matches the accuracy of state-of-the-art techniques for other copy-move forgery types. Our method is also robust with respect to filtering and compression based post-processing.

We present a computationally efficient technique to build concise and accurate computational models for large (60 or more inputs, 1 output) Boolean functions, only a very small fraction of whose truth table is known during model building. We use Genetic Programming with Boolean logic operators, and enhance the accuracy of the technique using Reduced Ordered Binary Decision Diagram based representations of Boolean functions, whereby we exploit their canonical forms. We demonstrate the effectiveness of the proposed technique by successfully modeling several common Boolean functions, and ultimately by accurately modeling a 63-input Physically Unclonable Function circuit design on Xilinx Field Programmable Gate Array. We achieve better accuracy (at lesser computational overhead) in predicting truth table entries not seen during model building, than a previously proposed machine learning based modeling technique for similar Physically Unclonable Function circuits using Support Vector Machines. The success of this modeling technique has important implications in determining the acceptability of Physically Unclonable Functions as useful hardware security primitives, in applications such as anti-counterfeiting of integrated circuits.

Security features are of paramount importance for the Internet of Things (IoT), and implementations are challenging given the resource-constrained IoT setup. We have developed a lightweight identity-based cryptosystem suitable for IoT to enable secure authentication and message exchange among the devices. Our scheme employs a Physically Unclonable Function (PUF) to generate the public identity of each device, which is used as the public key for each device for message encryption. We have provided formal proofs of security in the Session Key Security and Universally Composable Framework of the proposed protocol, which demonstrates the resilience of the scheme against passive and active attacks. We have demonstrated the setup required for the protocol implementation and shown that the proposed protocol implementation incurs low hardware and software overhead.

No abstract available.

Unpredictability is an important security property of Physically Unclonable Function (PUF) in the context of statistical attacks, where the correlation between challenge-response pairs is explicitly exploited. In the existing literature on PUFs, the Hamming Distance Test, denoted by HDT( t ), was proposed to evaluate the unpredictability of PUFs, which is a simplified case of the Propagation Criterion test PC( t ). The objective of these test schemes is to estimate the output transition probability when there are t or fewer than t bits flips, and ideally this probability value should be 0.5. In this work, we show that aforementioned two test schemes are not enough to ensure the unpredictability of a PUF design. We propose a new test, which is denoted as HDT( e , t ). This test scheme is a fine-tuned version of the previous schemes, as it considers the flipping bit pattern vector e along with parameter t . As a contribution, we provide a comprehensive discussion and analytic interpretation of HDT( t ), PC( t ), and HDT( e , t ) test schemes for Arbiter PUF (APUF), Exclusive-OR (XOR) PUF, and Lightweight Secure PUF (LSPUF). Our analysis establishes that HDT( e , t ) test is more general in comparison with HDT( t ) and PC( t ) tests. In addition, we demonstrate a few scenarios where the adversary can exploit the information obtained from the analysis of HDT( e , t ) properties of APUF, XOR PUF, and LSPUF to develop statistical attacks on them, if the ideal value of HDT( e , t ) = 0.5 is not achieved for a given PUF. We validate our theoretical observations using the simulated and Field Programmable Gate Array (FPGA) implemented APUF, XOR PUF, and LSPUF designs.

Many Internet of Things (IoT) applications can potentially benefit from the remote Dynamic Partial Reconfiguration (DPR) capabilities of modern Field Programmable Gate Arrays (FPGAs). Such capabilities enable changes in the circuit mapped on the FPGA, for modification or enhancement of functionality offered by the FPGA without taking it offline, via remote communications over a network. However, the use of remote DPR can result in security threats with catastrophic consequences. In this paper, we design two Hardware Trojan Horse attacks that exploit the remote DPR capability of the FPGA, on an encryption circuit and a true random number generator circuit, respectively. In particular, these attacks target the clock signal management circuitry on the FPGA to disrupt functionality. We substantiate the threat by demonstrating successful remote attacks via transfer of malicious bitstreams to a Virtex-5 FPGA, thereby embedding the HTH. Finally, we propose plausible countermeasures to prevent such attacks.

Current approaches for Hardware Trojan detection have varying degrees of computational and/or design overheads. In this paper, we develop a CAD methodology for a-priori estimation of Trojan vulnerability of a given circuit at the early stages of the design flow. We develop a security metric to estimate the testability of a circuit for HTHs, thus assessing its relative vulnerability. Our methodology overcomes several shortcomings of previously proposed testability metrics in the context of their applicability to the HTH detection problem in particular. We utilize the proposed metric to estimate the Trojan vulnerability of gate-level ISCAS benchmark circuits. The metric values show excellent correlation with the testability results obtained from previously proposed Trojan targeted ATPG techniques.

Recent literature has demonstrated that the security of Physically Unclonable Function (PUF) circuits might be adversely affected by the introduction of faults. In this paper, we propose novel and efficient architectures for a variety of widely used delay-based PUFs which are robust against high precision laser fault attacks proposed by Tajik et al. in FDTC-2015. The proposed architectures can be used to detect run-time modifications in the PUF design due to fault injection. In addition, we propose fault recovery techniques based on either logical reconfiguration or dynamic partial reconfiguration of the PUF design. We validate the robustness of our proposed fault tolerant delay-based PUF designs on Xilinx Artix-7 FPGA platform.

Buffer overflow and stack smashing have been one of the most popular software based vulnerabilities in literature. There have been multiple works which have used these vulnerabilities to induce powerful attacks to trigger malicious code snippets or to achieve privilege escalation. In this work, we attempt to implement hardware level security enforcement to mitigate such attacks on OpenRISC architecture. We have analyzed the given exploits [5] in detail and have identified two major vulnerabilities in the exploit codes: memory corruption by non-secure memcpy() and return address modification by buffer overflow. We have individually addressed each of these exploits and have proposed a combination of compiler and hardware level modification to prevent them. The advantage of having hardware level protection against these attacks provides reliable security against the popular software level countermeasures.

Physically Unclonable Function (PUF) circuits are often vulnerable to mathematical model-building attacks . We theoretically quantify the advantage provided to an adversary by any training dataset expansion technique along the lines of security analysis of cryptographic hash functions. We present an algorithm to enumerate certain sets of delay constraints for the widely studied Arbiter PUF (APUF) circuit, then demonstrate how these delay constraints can be utilized to expand the set of known Challenge--Response Pairs (CRPs), thus facilitating model-building attacks. We provide experimental results for Field Programmable Gate Array (FPGA)--based APUF to establish the effectiveness of the proposed attack.

We present the principles of operation and functioning of a CAD software tool for the automated realization of high performance integer arithmetic circuits targeting Xilinx Field Programmable Gate Arrays (FPGAs). The key ideas behind the improvement of circuit performance are optimal usage of the hardware primitives available on the Xilinx FPGA platform, as well as regular, careful and constrained placement of the circuit building blocks on the FPGA fabric. The bit - sliced architectures of our proposed designs allow us to automatically generate synthesizable, platform - specific structural Hardware Description Language (HDL) code for the proposed circuits, as well as the placement constraint files needed to control the placement of the design on the given FPGA fabric. Compared against circuits implemented using existing approaches and those automatically generated using existing CAD tools, our automatically generated implementations demonstrate significant speed improvement.

Despite the perceived lightweight and structural regularity of Arbiter PUF (APUF), high quality (bias-free) large APUF implementation on FPGA has traditionally proved to be challenging. Currently, the most widely accepted design approach for FPGA-based APUF implementation is the Programmable Delay Line (PDL) based APUF. In this work, we describe a scalable design methodology to implement close-to-ideal APUF on Xilinx FPGA using the standard Xilinx CAD tool flow. The main insight is to exploit the Hard Macro feature of the Xilinx design flow to design bias-free symmetric delay paths. We have demonstrated the effectiveness and superiority of our design to previously proposed PDL-based PUFs through implementation and characterization results.

Due to their unique physical properties, physically unclonable functions (PUF) have been proposed widely as versatile cryptographic primitives. It is desirable that silicon PUF circuits should be lightweight, i.e., have low-hardware resource requirements. However, it is also of primary importance that such demands of low hardware overhead should not compromise the security aspects of PUF circuits. In this paper, we develop two different mathematical attacks on previously proposed lightweight PUF circuits, namely composite PUF and the multibit output lightweight secure PUF (LSPUF). We show that independence of various components of composite PUF can be used to develop divide and conquer attacks which can be used to determine the responses to unknown challenges. We reduce the complexity of the attack using a machine learning-based modeling analysis. In addition, we elucidate a special property of the output network of LSPUF to show how such feature can be leveraged by an adversary to perform an intelligent model building attack. The theoretical inferences are validated through experimental results. More specifically, proposed attacks on composite PUF are validated using the challenge-response pairs (CRPs) from its field programmable gate array (FPGA) implementation, and attack on LSPUF is validated using the CRPs of both simulated and FPGA implemented LSPUF.

Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as Physically Unclonable Functions (PUFs). In this article, we propose a novel hybrid memristor-CMOS PUF circuit and demonstrate its suitability through extensive simulations of environmental and process variation effects. The proposed PUF circuit has substantially less hardware overhead than previously proposed memristor-based PUF circuits while being inherently resistant to machine learning-based modeling attacks because of challenge-dependent delays of the memristor stages. The proposed PUF can be conveniently used in many security applications and protocols based on hardware-intrinsic security.

Histogram‐bin‐shifting has been previously shown to be an effective method of reversibly watermarking greyscale images. For colour image reversible watermarking, histogram‐bin‐shifting technique can be extended trivially to RGB colour space. However, direct application of histogram‐bin‐shifting to the RGB colour image components, results in relatively poor performance of the watermarking algorithm. In order to improve the performance of the algorithm in terms of embedding capacity and distortion whereas preserving the inherent computational simplicity of the histogram‐bin‐shifting technique, the authors propose a technique of shifting frequency histogram bins of transformed colour components. In this study, the authors consider the YCbCr colour‐space. Experimental results on standard test images, prove that the proposed technique achieves high embedding capacity with considerably low distortion.

Hardware Trojan attack in the form of malicious modification of a design has emerged as a major security threat. Sidechannel analysis has been investigated as an alternative to conventional logic testing to detect the presence of hardware Trojans. However, these techniques suffer from decreased sensitivity toward small Trojans, especially because of the large process variations present in modern nanometer technologies. In this paper, we propose a novel noninvasive, multiple-parameter side-channel analysisbased Trojan detection approach. We use the intrinsic relationship between dynamic current and maximum operating frequency of a circuit to isolate the effect of a Trojan circuit from process noise. We propose a vector generation approach and several design/test techniques to improve the detection sensitivity. Simulation results with two large circuits, a 32-bit integer execution unit (IEU) and a 128-bit advanced encryption standard (AES) cipher, show a detection resolution of 1.12 percent amidst ±20 percent parameter variations. The approach is also validated with experimental results. Finally, the use of a combined side-channel analysis and logic testing approach is shown to provide high overall detection coverage for hardware Trojan circuits of varying types and sizes.

In general reversible watermarking algorithms, the convention is to reject the entire cover image at the receiver end if it fails authentication, since there is no way to detect the exact locations of tampering. This feature may be exploited by an adversary to bring about a form of DoS attack. Here we provide a solution to this problem in form of a tamper localization mechanism for reversible watermarking algorithms, which allows selective rejection of distorted cover image regions in case of authentication failure, thus avoiding rejection of the complete image. Additionally it minimizes the bandwidth requirement of the communication channel.

Cryptographic algorithms are routinely used toper form computationally intense operations over increasingly larger volumes of data, and in order to meet the high throughput requirements of the applications, are often implemented by VLSI designs. The high complexity of such implementations raises concern about their reliability. In order to improve upon the testability of sequential circuits, both at fabrication time and also in the field, Design For Testability (DFT) techniques are commonly employed. However conventional DFT methodologies for digital circuits have been found to compromise the security of the cryptographic hardware. In this tutorial we first discuss the challenges and potential attacks on cipher hardware through standard DFT techniques, and then potential solutions against them. Also, as the electronic design industry has grown globally, economic reasons dictate the widespread participation of external agents in modern design and manufacture of integrated circuits(ICs), which decreases the control that the IC design houses used to traditionally have over their own designs. This issue raises the question of ensuring Trust in an integrated circuit, and whether the IC can be certified to be free of malicious, hard-to detect circuitry, commonly referred to as Hardware Trojans. In this tutorial, we would explore the unique challenges and testing solutions to detect/prevent such malicious modifications.

Modern hardware and software implementations of cryptographic algorithms are subject to multiple sophisticated attacks, such as differential power analysis (DPA) and fault-based attacks. In addition, modern integrated circuit (IC) design and manufacturing follows a horizontal business model where different third-party vendors provide hardware, software and manufacturing services, thus making it difficult to ensure the trustworthiness of the entire process. Such business practices make the designs vulnerable to hard-to-detect malicious modifications by an adversary, termed as “Hardware Trojans”. In this paper, we show that malicious nexus between multiple parties at different stages of the design, manufacturing and deployment makes the attacks on cryptographic hardware more potent. We describe the general model of such an attack, which we refer to as Multi-level Attack, and provide an example of it on the hardware implementation of the Advanced Encryption Standard (AES) algorithm, where a hardware Trojan is embedded in the design. We then analytically show that the resultant attack poses a significantly stronger threat than that from a Trojan attack by a single adversary. We validate our theoretical analysis using power simulation results as well as hardware measurement and emulation on a FPGA platform.

Malicious hardware Trojan circuitry inserted in safety-critical applications is a major threat to national security. In this work, we propose a novel application of a key–based obfus-cation technique to achieve security against hardware Tro-jans. The obfuscation scheme is based on modifying the state transition function of a given circuit by expanding its reachable state space and enabling it to operate in two dis-tinct modes – the normal mode and the obfuscated mode. Such a modification obfuscates the rareness of the internal circuit nodes, thus making it difficult for an adversary to insert hard-to-detect Trojans. It also makes some inserted Trojans benign by making them activate only in the obfus-cated mode. The combined effect leads to higher Trojan detectability and higher level of protection against such at-tack. Simulation results for a set of benchmark circuits show that the scheme is capable of achieving high levels of security at modest design overhead.

Among the emerging alternatives to CMOS, molecular electronics based diode-resistor crossbar fabric has generated considerable interest in recent times. Logic circuit design with future nano-scale molecular devices using dense and regular crossbar fabrics is promising in terms of integration density, performance and power dissipation. However, circuit design using molecular switches involve some major challenges: 1) lack of voltage gain of these switches that prevents logic cascading; 2) large output voltage level degradation; 3) vulnerability to parameter variations that affect yield and robustness of operation; and 4) high defect rate. In this article, we analyze some of the above challenges and investigate the effectiveness of asynchronous design methodology in a hybrid system design platform using molecular crossbar and CMOS interfacing elements. We explore different approaches of asynchronous circuit design and compare their suitability in terms of several circuit design parameters. We then develop the methodology and an automated synthesis flow to support two different asynchronous design approaches ( Micropipelines and Four phase Dual-rail ) for system designs using nano-crossbar logic stages and CMOS interface data-storage elements. Circuit-level simulation results for several benchmarks show considerable advantage in terms of performance and robustness at moderate area and power overhead compared to two different synchronous implementations.

Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.

There have been serious concerns recently about the security of microchips from hardware trojan horse insertion during manufacturing. This issue has been raised recently due to outsourcing of the chip manufacturing processes to reduce cost. This is an important consideration especially in critical applications such as avionics, communications, military, industrial and so on. A trojan is inserted into a main circuit at manufacturing and is mostly inactive unless it is triggered by a rare value or time event; then it produces a payload error in the circuit, potentially catastrophic. Because of its nature, a trojan may not be easily detected by functional or ATPG testing. The problem of trojan detection has been addressed only recently in very few works. Our work analyzes and formulates the trojan detection problem based on a frequency analysis under rare trigger values and provides procedures to generate input trigger vectors and trojan test vectors to detect trojan effects. We also provide experimental results.

Hardware intellectual property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs and to prevent revenue loss due to IP piracy. In this paper, we propose a novel design methodology for hardware IP protection and authentication using netlist level authentication. The proposed methodology can be integrated in the SoC design and manufacturing flow to provide hardware protection to the IP vendors, the chip designer, and the system designer. Simulation results on ISCAS-89 benchmark circuits show that we can achieve high levels of security through a well-formulated obfuscation scheme at less than 10% area overhead under delay constraint.

High defect rate in emerging nano-devices mandates new computational models that can tolerate defects thereby rendering reliability of operation and reasonable manufacturing yield. In a bottom-up system design approach using nano-crossbar applications are typically mapped into a crossbar using either PLA or lookup table (LUT) implementation of a logic circuits. LUT-based implementation has some definite advantages over PLA-based one due its easy reconfigurability. In this paper, we consider a LUT-based logic design paradigm using nano-crossbar and propose a novel application mapping technique that can effectively take advantage of certain defects in the LUTs. The main idea is: 1) to identify and localize the unidirectional stuck-at faults in the LUTs and 2) then map an application in such a way that the a particular defective LUT is used to map a Boolean function which is compatible with the behavior of the LUT. The idea of exploiting certain defects to implement a function (as opposed to discard the defective location as unusable), improves yield considerably in LUT-based configurable nanocomputing. Our simulation with 5times5 and 5times1 LUT shows an average improvement of 87% in number of mapped function over conventional mapping for a defect rate of 10%.

Scan-based DFT enhances the testability of a system by making its internal nodes more observable and controllable. However, in case of a secure chip, scan chain increases its vulnerability to attack, where the attacker can extract secret information by scanning out states of internal nodes. This paper presents VIm-Scan: a low overhead scan design methodology that maintains all the advantages of a traditional scan-based testing yet prevents secure key extraction through the scan out process. Experimental results show that the proposed approach entails significantly lesser design overhead (~5times reduction in number of additional gates) with comparable or better protection against attack than existing techniques.