Vision Transformers (ViTs) have achieved high performance across various computer vision tasks by leveraging the attention mechanism. However, the attention module in ViTs severely hindered inference performance due to its low operational intensity. Existing approaches improve ViTs efficiency through pruning, sparsity, and linearization, but at the cost of fine-tuning overhead and accuracy degradation. In this paper, we propose PipeViT, a memory-efficient and low-latency accelerator for ViTs inference. The key insight of PipeViT is to exploit intra-layer acceleration opportunities. Specifically, we first fuse the attention operations into a single operator to reduce memory access overhead. Then, we divide the input of attention into multiple tiles to reduce the on-chip memory requirement. Finally, we pipeline the tiled attention computation to improve overall throughput. Based on the optimized dataflow, we design a heterogeneous dual-core architecture for efficient pipeline execution. Furthermore, to maximize hardware utilization, the architecture can be reconfigured into a single core with higher parallelism during the execution of the feed-forward network. Experimental results show that PipeViT achieves up to $19.3 \times 1.5 \times, 2.1 \times$, and $2.0 \times$ improvements in Frames Per Second (FPS) compared to state-of-the-art accelerators, including ViTA, Auto-ViT, MEViT, and HeatViT. Additionally, PipeViT achieves up to $8.0 \times$ and $2.6 \times$ higher energy efficiency compared to CPU and GPU implementations, respectively.

Sparse matrix-sparse matrix multiplication (SpMSpM) is widely used in modern scientific applications, including high-performance computing, linear algebra, and graph processing. However, the highly variable distribution of nonzero elements in these matrices presents a significant challenge to computational efficiency. While existing sparse matrix accelerators often rely on specialized architectures tailored for specific dataflow, these designs sacrifice generality and fail to fully exploit potential data reuse opportunities.

Detailed routing constitutes a critical phase in the very large-scale integration (VLSI) physical design, widely regarded as the most time-consuming and computationally intensive step in the back-end design process. Due to its iterative nature and strong data dependencies, conventional parallel acceleration techniques often suffer from limited scalability and effectiveness. To address these challenges, we propose RouterAcc, an FPGA-based software–hardware co-design acceleration framework tailored for VLSI detailed routing. RouterAcc incorporates an access analysis mechanism and a termination condition strategy to accelerate convergence. Furthermore, we employ a hierarchical storage mapping scheme and a flexible dimension-partitioning architecture to alleviate memory bottlenecks and enhance data locality. Additionally, RouterAcc leverages a hierarchical comparison pipeline with fully parallelized computing units and a data preprocessing strategy to maximize computational efficiency. Experimental results on the ISPD’18 benchmarks demonstrate that RouterAcc achieves consistent speedups of 2.1×–2.3× over TritonRoute with less than 1% quality degradation. With further co-optimization, RouterAcc attains speedups of 2.7×–11.8× while maintaining routing quality comparable to TritonRoute and surpassing Dr.CU 2.0 as well as the state-of-the-art (SOTA) FPGA-based approaches.

As integrated circuit technology nodes scale down, high via density challenges multiple patterning lithography (MPL). Existing methods for addressing via coloring conflicts mainly focus on detailed routing, yet they cannot resolve conflicts arising from vias that are fixed before routing, such as Power/Ground vias and obstruction vias. This paper presents a co-optimization framework to eliminate such inherent via coloring conflicts and boost routing efficiency. It proposes a conflict detection method identifying odd cycle and odd wheel violation patterns, balancing efficiency and precision well. It dynamically marks Forbidden Box and Forbidden Pair for mask-decomposition-aware placement and routing. A placement adjustment based on Directed Acyclic Graph (DAG) simultaneously handles overlaps between a cell’s Forbidden Box and Power/Ground vias, as well as illegal abutment of Forbidden Pair cells. During routing, Forbidden Box constraints guide pin access and via locations, while a final check resolves remaining conflicts through rip-up and reroute. Industrial benchmark experiments show the framework completely eliminates via coloring conflicts, and slightly reduces wirelength, via count and runtime.

Nonlinear activation plays an essential role in neural networks (NNs) for their generalization ability. However, implementing intricate mathematical operations on hardware platforms, including Field-Programmable Gate Arrays (FPGAs), presents significant challenges. Prior works based on piecewise functions or look-up table (LUT) have encountered difficulties in balancing precision requirements with fair hardware overhead and often necessitating complex manual interventions. To address these issues, this paper proposes DIF-LUT Pro, an automated tool for simple yet scalable approximation for various nonlinear activations on FPGA. Specifically, the proposed algorithm achieves self-adaptive hardware design oriented towards target precision, by piecewise linear matching to fit the function derivative roughly and range addressable LUT to offset the difference. Moreover, DIF-LUT Pro integrates the algorithm into an automated tool, allowing users to configure the customized interface and generate the corresponding hardware description language (HDL) code with a single click. Experimental results show that (1) DIF-LUT Pro features robust automation and fair generality, capable of generating equitable hardware designs under various user configurations across different FPGA platforms; (2) DIF-LUT Pro produces approximations that are simple yet effective, achieving competitive performance compared to previous expert-crafted designs. Furthermore, two detailed case studies demonstrate the efficient application of DIF-LUT Pro on NeRF and SEResnet, proving its practical value. Our source code is open-source and available at https://github.com/AdrianLiu00/DIF-LUT-Tool.

Field-Programmable Gate Array (FPGA) has shown great application potential in deploying Neural Networks (NNs) due to the characteristics of programmability, low power consumption, etc. However, deploying NNs on FPGA is non-trivial because (1) Mainstream NNs pose significant FPGA architecture design challenges due to their large number of parameters, complex operations, and the need for data optimization, and (2) Supporting the deployment of different machine learning frameworks to FPGA requires significant manual effort, consuming a large amount of time. In this paper, we propose AutoCompiler, a unified compiler for mapping NNs to different FPGAs, along with overlay techniques to enable fast and efficient implementation. To the best of our knowledge, we are the first work to support both Deep Neural Networks (DNNs) and Transformer-based networks for overlay-based FPGA deployment. AutoCompiler comprises three integrated enablers: (1) Model Translator, built on top of a topology-based NNs representation, which can optimize the topology and data representation of the models from an algorithmic level based on different hardware configurations, e.g., DSP utilization, (2) Instruction Generator, which generates pipeline data streams according to various FPGA resource configurations by manipulating the instruction set at the upper level rapidly, and (3) End-to-end optimization, which moves as much of the computational processes as possible onto the FPGA chip and minimizes the interaction between CPU and FPGA. Extensive experiments on various Xilinx FPGAs show that AutoCompiler outperforms state-of-the-art overlay-based compiler by 1.2× - 1.35× and same-level GPUs by 1.15× - 1.59× for classic DNN models, and ViT inference, respectively.

In recent years, Neural Networks developed rapidly to deal with tasks in the field of Computer Vision and Natural Language Process, etc. With the development of AI Generated Content, U-Net based Diffusion Models (DM) take image synthesis to new heights. U-Net performs the noise prediction of DM, the latency of which accounts for the majority of the end-to-end latency. Although FPGA has been proven to be a high performance platform to deploy NN, a series of facts still pose challenges for efficient U-Net based DMs deployment based on FPGA. The input vector length and type of the special function vary between different layers. The absence of model periodicity increases the granularity and complexity of operator scheduling. Skip-connection and residual connection inside model cause meta-data retaining in the memory, which is not conductive to avoiding memory overflow and decreasing total off-chip memory access.

Transformers have delivered exceptional performance and are widely used across various natural language processing (NLP) tasks, owing to their powerful attention mechanism. However, the high computational complexity and substantial memory usage pose significant challenges to inference efficiency. Numerous quantization and value-level sparsification methods have been proposed to overcome these challenges. Since higher sparsity leads to greater acceleration efficiency, leveraging both value-level and bit-level sparsity (hybrid sparsity) can effectively exploit the acceleration potential of the attention mechanism. However, increased sparsity exacerbates load imbalance across compute units, potentially limiting the extent of acceleration benefits. To fully exploit the acceleration potential of hybrid sparsity, we propose Libra, an attention accelerator developed through algorithm-hardware co-design. At the algorithm level, we design the bit-group-based algorithm consisting of filtered bit-group sparsification (FBS) and dynamic bit-group quantization (DBQ) to maximize the utilization of sparsity in attention. FBS imposes structured sparsity on weights, while DBQ introduces dynamic sparsification during the computation of activations. At the hardware level, we design task pool to achieve multi-level workload balance, effectively mitigating the load imbalance among compute units induced by hybrid sparsity. Additionally, different stages in DBQ can be executed in parallel, with each stage operating at distinct bit-widths. To support this, we design an adaptive bit-width architecture that enables simultaneous computations at varying bitwidths. Our experiments demonstrate that, compared to state-of-the-art (SOTA) attention accelerators, Libra achieves up to $1.49 \times \sim 5.89 \times$ speedup and $2.65 \times \sim 10.82 \times$ enhancement in energy efficiency.

The attention mechanism is a core neural network primitive widely utilized in state-of-the-art models of Natural Language Processing (NLP) applications. However, the high computational complexity and substantial power consumption hinder its deployment and efficient inference. To address these challenges, various methods leveraging sparsity and quantization have been proposed. Compared to these methods, the exploitation of abundant bit-level sparsity in attention-based models presents great potential for the performance enhancement of attention inference. Existing bit-sparsity optimization methods primarily focus on Convolutional Neural Networks (CNNs), which are not ideally suitable for the attention mechanism, and they have not effectively solved the workload imbalance and hardware under-utilization issues caused by the irregular distribution of non-zero bits in tensor data. In this work, we introduce Blaze, an efficient attention architecture that leverages both value and bit-level sparsity in tensor data along with workload orchestration optimization. To mitigate the workload imbalance issues often encountered by sparse bit-serial architecture, we propose an Approximate-Computing-Based (ACB) workload orchestration mechanism. Additionally, to fully exploit the redundancy in the attention mechanism, we propose a Leading-Booth mechanism to further enhance the performance of attention computation. We also design a reconfigurable computing engine to support both mechanisms. Experimental results indicate that, compared to state-of-the-art (SOTA) attention accelerators, our Blaze can achieve $2.37 \times \sim 6.18 \times$ improvement in performance and $9.69 \times \sim 43.96 \times$ enhancement in energy efficiency. Our accelerator can reach up to $1.58 \times$ speedup in attention computing performance compared with the SOTA bit-sparse accelerator.

Binarization is a promising approach to significantly reduce computational complexity by replacing multiplications with hardwareefficient XNOR operations. However, the binarization of LLM activations often leads to severe accuracy degradation, while weight-only binarization fails to eliminate multipliers due to the Self-Attention mechanism. Furthermore, LLMs exhibit distinctive channel-level data distribution characteristics and differing computational and memory requirements between the Pre-fill and Decoding stages, necessitating a specialized inference framework. In response, we introduce XShift, an algorithm-hardware co-design framework optimized for efficient binarized LLM inference on FPGAs. XShift incorporates three key contributions: (1) a hardwarefriendly XNOR-Shift Encoding (XSE) format that transforms traditional multiplications into XNOR and shift operations, ensuring scalability and precision; (2) Hardware Adaptive Outlier and Sparsity (HAOS) techniques, which exploit channel-level data distribution and systolic array architectures for optimized quantization and sparsification; and (3) a dedicated hardware accelerator featuring an XNOR-Shift Systolic Array (XSSA) and an enhanced Base-2 SoftMax Converter (BSMC), designed to address the specific computational demands of binarized LLMs. Experimental evaluations on the Alveo U280 and U50 FPGA demonstrate that XShift achieves a $\mathbf{1 0 - 1 5 x}$ reduction in DSP resource usage while surpassing existing accelerators and GPUs in inference performance. Specifically, XShift delivers an average speedup of 4.174.76 x and a 14.29-6.95 x improvement in energy efficiency, alongside lower perplexity compared to other low-precision LLM techniques. These results underscore the potential of XShift for edge deployment of LLMs.

The self-attention mechanism is a fundamental component within transformer-based models. Nowadays, as the length of sequences processed by large language models (LLMs) continues to increase, the attention mechanism has gradually become a bottleneck in model inference. The LLM inference process can be separated into two phases: prefill and decode. The latter contains memory-intensive attention computation, making FPGA-based accelerators an attractive solution for acceleration. However, designing accelerators tailored for the attention module poses a challenge, requiring substantial manual work. To automate this process and achieve superior acceleration performance, we propose AttentionLib, an MLIR-based framework. AttentionLib automatically performs fusion dataflow optimization for attention computations and generates high-level synthesis code in compliance with hardware constraints. Given the large design space, we provide a design space exploration (DSE) engine to automatically identify optimal fusion dataflows within the specified constraints. Experimental results show that AttentionLib is effective in generating well-suited accelerators for diverse attention computations and achieving superior performance under hardware constraints. Notably, the accelerators generated by AttentionLib exhibit at least a 25.1 × improvement compared to the baselines solely automatically optimized by Vitis HLS. Furthermore, these designs outperform GPUs in decode workloads, showcasing over a 2× speedup for short sequences.

The row-wise product algorithm shows significant potential for sparse matrix-matrix multiplication (SpGEMM) on hardware accelerators. Recent studies have made notable progress in accelerating SpGEMM using this algorithm. However, several challenges remain in accelerating imbalanced SpGEMM, where the distribution of non-zero elements across different rows is imbalanced. These challenges include: (1) the fixed dataflow of the merger tree, which leads to lower PE utilization, and (2) highly imbalanced data distributions, such as single rows with numerous non-zero elements, which result in intensive computations. This imbalance significantly challenges SpGEMM acceleration, leading to time-consuming processes that dominate overall computation time. In this paper, we propose AiSpGEMM to accelerate imbalanced SpGEMM on FPGAs. First, we improved the C2SR format to adapt it for imbalanced SpGEMM acceleration based on the row-wise product algorithm. This reduces off-chip memory bank conflicts and increases data reuse of matrix B. Secondly, we design a reconfigurable merger (R-merger) with flexible interconnects to improve PE utilization. Additionally, we propose an intra-row parallel merging algorithm and its corresponding hardware architecture, the parallel merger (P-merger), to accelerate intensive operations. Experimental results demonstrate that AiSpGEMM achieves a geometric mean (geomean) speedup of 5.8× compared to the state-of-the-art FPGA-based SpGEMM accelerator. In Geomean, AiSpGEMM achieves a 3.0× speedup and a 9.8× improvement in energy efficiency compared to the NVIDIA cuSPARSE library running on an NVIDIA A6000 GPU. Moreover, AiSpGEMM-21 demonstrated a 4× increase in average throughput compared to the same GPU.

This paper introduces FAMERS, a tile-based hardware accelerator designed for efficient 3D Gaussian Splatting (3DGS) inference on edge-deployed Field Programmable Gate Arrays (FPGAs). 3DGS has emerged as a powerful technique for photorealistic image rendering, leveraging anisotropic Gaussians to balance computational efficiency and visual fidelity. However, the high memory and processing demands of 3DGS pose significant challenges for real-time applications on resource-constrained edge devices. To address these limitations, we present a novel architecture that optimizes both computational and memory overheads through model pruning and compression techniques, enabling high-quality rendering within the constrained memory and processing capabilities of edge platforms. Experimental results demonstrate that our implementation on the Xilinx XC7K325T FPGA achieves a 1.99× speedup and 13.46× energy efficiency compared to NVIDIA RTX 3060M Laptop GPU, underscoring the viability of our approach for real-time applications in virtual and augmented reality.

Dynamic scheduling in high-level synthesis (HLS) maximizes pipeline performance by enabling out-of-order scheduling of load and store requests at runtime. However, this method introduces unpredictable memory dependencies, leading to data disambiguation challenges. Load-store queues (LSQs), commonly used in superscalar CPUs, offer a potential solution for HLS. How-ever, LSQs in dynamically scheduled HLS implementations often suffer from high resource overhead and scalability limitations. In this paper, we introduce PreVv, an architecture based on premature value validation designed to address memory disambiguation with minimal resource overhead. Our approach substitutes LSQ with several PreVv components and a straightforward premature queue. We prevent potential deadlocks by incorporating a specific tag that can send ‘fake’ tokens to prevent the accumulation of outdated data. Furthermore, we demonstrate that our design has scalability potential. We implement our design using several hardware templates and an LLVM pass to generate targeted dataflow circuits with PreVv. Experimental results on various benchmarks with data hazards show that, compared to state-of-the-art dynamic HLS, PreVV16 (a version with a premature queue depth of 16) reduces LUT usage by 43.91% and FF usage by 33.09%, with minimal impact on timing performance. Meanwhile, PreVV64 (a version with a premature queue depth of 64) reduces LUT usage by 27.21% and FF usage by 33.10%, without affecting timing performance.

In the back-end verification of integrated circuits (IC), design rule checking (DRC) plays a critical role in ensuring that the layout complies with process constraints and guarantees manufacturability. Traditional DRC for 2D layouts involves checks on parameters including line width, spacing, and density. With the advancement of 3D IC and advanced packaging technologies, new DRC requirements have emerged. These include checks on inter-die spacing, alignment relationships, and the handling of non-Manhattan geometries. Previous academic research has focused almost exclusively on optimizing 2D DRC. Meanwhile, industrial tools such as Calibre 3DSTACK can only perform 3D rule checks on layouts that have already passed 2D DRC, which increases both workflow complexity and time consumption. Targeted at these limitations, we propose 3D DRC, a U-Net-based DRC tool designed for 3D IC. Our method performs both 2D and 3D rule checks in a single pass on 3D structures, with specific optimizations for non-Manhattan geometries in 3D IC. Additionally, the tool also supports traditional 2D DRC when applied to purely 2D layouts. We evaluated the performance of 3D DRC on a variety of open-source PDK rule sets. Extensive experiments demonstrate that the model exhibits strong generalization and high accuracy, achieving an average recall of 97.5% and precision of 97.7%. Furthermore, the model demonstrates high runtime efficiency, with the 2D mode running 22.3× faster than Calibre nmDRC, and the 3D mode being 13.3× faster than Calibre 3DSTACK.

Electromigration-related reliability concerns in very large-scale integration (VLSI) circuits have garnered increasing attention as technology continues to scale. As integrated circuits shrink and their density rises, solving Korhonen's equation for the multi-segment interconnect line model becomes increasingly challenging. Recent advances in neural network-based approaches have demonstrated notable efficacy in addressing differential equations arising in physical modeling frameworks. Inspired by Physics-Informed Graph Neural Network (PIGNN) methodologies, we propose a novel Physics-Informed Message Passing (PIMNEM) architecture designed to solve coupled multi-domain Korhonen equations. At the same time, we introduce AdaptEM, which incorporates a graph partitioning mechanism with a hierarchical training strategy and employs the PIM-NEM architecture as a subgraph computation unit. AdaptEM enables multi-scale decomposition of interconnected circuits and facilitates hierarchical unsupervised learning via its hierarchical architecture. Unsupervised training is first applied to partitioned subgraphs using the PIMP mechanism, followed by global graph fine-tuning, where inter-subgraph boundary constraints are explicitly enforced through differentiable penalty terms. AdaptEM achieves a 20× speedup over FEM-based methods at the cost of about 0.5% accuracy loss. While AdaptEM may not match the absolute computational speed of state-of-the-art EM tools, its end-to-end unsupervised training framework, enhanced by a hierarchical subgraph training strategy, offers superior generalization capabilities and greater tuning flexibility.

Hyperdimensional computing (HDC) has emerged as a promising cognitive computing paradigm, offering exceptional robustness and energy efficiency for intelligent applications. However, the computational demands of HDC, particularly during the encoding and associative search phases, pose significant challenges due to their time and resource intensity. In this paper, we propose LUT-HD, a software-hardware co-design framework that accelerates HDC inference by leveraging efficient table lookup techniques. First, we introduce a binary code quantization (BCQ) algorithm based on a lookup table (LUT) that transforms costly matrix-vector multiplications in HDC into simple table lookups using precomputed results. Next, we propose a custom FPGA-based accelerator tailored for LUT-based HDC to strike a balance between accuracy and efficiency. This accelerator incorporates a performance-optimized pipeline for encoding and associative search, enhancing computational speed and resource utilization. Experimental results demonstrate that LUT-HD achieves up to 14.6 × inference speedup and reduces 97.3% energy consumption compared to the GPU platform. In addition, compared to state-of-the-art (SOTA) HDC solutions, LUT-HD offers a 5.5× speedup with negligible accuracy loss and reduces 44.8% energy consumption.

The State Space Model (SSM), particularly the Mamba implementation, has demonstrated impressive capabilities across various domains. It offers a significant reduction in computational complexity compared to Transformers while achieving higher algorithm accuracy. However, the ineffectiveness of spatially unfolding the SSM layer leads to increased latency as sentence length grows, especially when being deployed on FPGA. Previous token reduction methods introduced in Transformers fail to maintain high performance in Mamba. Moreover, the dispersed outliers, complex model structure and variety of non-linear operators obstruct its efficient implementation on FPGA. To address these challenges, we propose ToMamba, the first algorithm-architecture co-design to optimize Mamba implementation. At the algorithmic level, ToMamba incorporates a novel progressive token merging algorithm with minimal hardware consumption and a hardware-aware fine-grained quantization strategy. On the hardware side, a dualflow systolic array is designed to unify convolution and matrix multiplication, supporting both weight stationary and output stationary dataflow. A fine-grained pipeline design is adopted for SSM computation to maximize hardware efficiency and enhance throughput. Furthermore, efficient hardware architecture and approximation method for nonlinear function units are proposed. To enable merging after the Mamba layer, ToMamba also adopts a dedicated data mapping scheme. Comprehensive evaluations across multiple benchmarks demonstrate that the token reduction method of ToMamba achieves 10% sparsity with only 0.25% accuracy loss, improving up to 16.89% in accuracy compared to previous methods. ToMamba hardware implementation on U280 FPGA achieves up to 636.00×/11.01×/1.39× speedup compared to Intel Xeon Platinum 8369B CPU, NVIDIA Tesla A100 GPU and ASIC platforms and 1280×/44.32× energy efficiency improvement compared to CPU and GPU platforms.

The rapid evolution of 3D integrated circuits (ICs) has ushered in unprecedented integration density and performance gains. However, this advancement intensifies the challenges of multi-physics interactions, particularly the intricate coupling between electromagnetic (EM) and thermal fields. Thermal and EM optimizations of 3D ICs often require extensive and complex Partial Differential Equation (PDE) simulations. Neural network-based field solvers are renowned for their high efficiency and accuracy. However, existing approaches are often trained using results from traditional physical field solvers, which are time-consuming and lack compatibility with more complex design configurations. In this paper, for the first time, we propose 3D CoSim, a Physics-Informed Neural Network (PINN) based simulator for multi-physics analysis with arbitrary 3D IC configurations. 3D CoSim has a sophisticated computational framework that learns the nonlinear functional mappings from geometrical and physical setups to multiphysics fields. Leveraging a Multi-input DeepONet architecture, 3D CoSim integrates multiple PDE configurations. This integration encompasses the heat equation, Maxwell’s equations, and a diverse range of boundary conditions, thereby enabling the derivation of a unified solution for both EM and thermal fields. This integration delivers a paradigm shift in simulation efficiency. Experimental results demonstrate that 3D CoSim achieves a speedup of 844× to 7600× compared to traditional COMSOL while maintaining comparable accuracy of 97% for EM simulation and 99.8% for thermal simulation.

Transformers have increasingly become the backbone of modern AI, excelling in tasks across natural language processing (NLP) and computer vision (CV). Despite their effectiveness, calculating them is costly, especially on source-constrained platforms like FPGAs. Among the three main computation modules in a Transformer model (QKV generation, attention computation, FFN), most prior research has primarily focused on the attention computation. However, it is typically the QKV generation and the FFN that dominate the overall computational cost in most cases. To address this gap, we propose SiST, an innovative algorithm-architecture co-design to optimize all three modules of Transformer with both sparsity and token similarity. We first propose a cross-stage sparsity prediction mechanism before QKV generation to minimize computations involved in both QKV generation and attention computing. The prediction mechanism avoids large overhead through off-line weight clustering. Further, we leverage token similarity to adapt token clustering in FFN module, thereby reducing computational load. Moreover, the sparsity of weights in FFN is explored to further optimize the computational load. Our dedicated hardware architecture can effectively handle the unstructured sparsity and token clustering, ensuring high hardware resource utilization. Comprehensive evaluations across multiple benchmarks demonstrate that SiST reduces computational overhead by 45.9% to 52.2% with less than 2% loss in accuracy. It achieves a 2.35× to 8.44× speedup, 1.50× to 14.09× normalized throughput improvement and 2.43× to 3.44× improvement in energy efficiency compared with other FPGA-based Transformer accelerators.

Abstract Container-based virtualization is increasingly popular in cloud computing due to its efficiency and flexibility. Isolation is a fundamental property of containers and weak isolation could cause significant performance degradation and security vulnerability. However, existing works have almost not discussed the isolation problems of system log which is critical for monitoring and maintenance of containerized applications. In this paper, we present a detailed isolation analysis of system log in current container environment. First, we find several system log isolation problems which can cause significant impacts on system usability, security, and efficiency. For example, system log accidentally exposes information of host and co-resident containers to one container, causing information leakage. Second, we reveal that the root cause of these isolation problems is that containers share the global log configuration, the same log storage, and the global log view. To address these problems, we design and implement a system named private logs (POGs). POGs provides each container with its own log configuration and stores logs individually for each container, avoiding log configuration and storage sharing, respectively. In addition, POGs enables private log view to help distinguish which container the logs belong to. The experimental results show that POGs can effectively enhance system log isolation for containers with negligible performance overhead.

Instant-NGP is the state-of-the-art (SOTA) algorithm of Neural Radiance Field (NeRF) and shows great potential to be adopted in ARNR. However, the high cost of memory and computation limits Instant-NGP’s implementation on edge devices. In light of this, we propose a novel FPGA-based accelerator to reduce power consumption, called Booth-NeRF. Booth-NeRF adopts a fully-pipelined technique and is built upon the Booth algorithm. In addition, it introduces a new instruction set to accommodate Multi-Layer Perceptrons (MLPs) of different sizes, ensuring flexibility and efficiency. Moreover, we propose an FPGA-friendly multiplier architecture for matrix multiplication which is capable of performing exact or approximate multiplication using the Booth algorithm and the select-shift-add technique. Evaluations with a Xilinx Kintex XC7K325T board show that Booth-NeRF achieves $2.20\times$ speedup and $1.31\times$ energy efficiency compared with NVIDIA Jetson Xavier NX-16G GPU.

Transformer-based models have achieved huge success in various artificial intelligence (AI) tasks, e.g., natural language processing (NLP) and computer vision (CV). However, transformer-based models always suffer from high computation density, making them hard to be deployed on resource-constrained devices like field-programmable gate array (FPGA). Among the overall process of transformers, self-attention contributes to most of the computation load and becomes the bottleneck of transformer-based models. In this paper, we propose TransFRU, a novel FPGA-based accelerator for self-attention mechanism with full utilization of hardware resources. Specifically, we first leverage 4-bit and 8-bit processing elements (PEs) to package multiple signed multiplications into one DSP block. Second, we skip the zero and near-zero values in the intermediate result of self-attention by a sorting engine. The sorting engine is also responsible for operand sharing to boost the computation efficiency of one DSP block. Experimental results show that our TransFRU achieves $7.86-49.16 \times$ speedup and $151.1 \times$ energy efficiency compared with CPU, $1.41 \times$ speedup and $5.9 \times$ energy efficiency compared with GPU. Furthermore, we observe $1.91- 13.56 \times$ better throughput per DSP block and $3.53-9.62 \times$ energy efficiency compared with previous FPGA accelerators.

In this paper, we propose a fused-pipeline architecture that leverages the layer fusion technique to harness the strengths of both non-pipeline and full-pipeline architectures while mitigating their disadvantages. In particular, we observe that the performance of the fused-pipeline accelerators is significantly influenced by the layer fusion strategies and intra-layer mapping schemes. To optimize and rapidly employ the fused-pipeline architecture, we present an end-to-end automation framework, named PipeFuser. At the core of PipeFuser is a genetic algorithm (GA)-based co-design engine, which is used to acquire near-optimal hardware configurations in the vast design space. Experimental results demonstrate that our fused-pipeline architecture achieves 2.3 × to 3.3 × higher performance over the non-pipeline design and 1.9 × to 2.5 × speedup compared to the full-pipeline architecture, with greater deployment flexibility.

With the evolution of network infrastructure, the pattern of network traffic becomes unprecedentedly complex. Conventional machine learning algorithms struggle to cope with the high-dimensional data and real-time processing speeds required in such complex networks. Fortunately, Hyperdimensional Computing (HDC), which is power-efficient and supports parallel processing, provides a potential solution to this challenge. In this paper, we present TrafficHD, a novel classification framework that leverages HDC to analyze network traffic in real-time. By transforming network traffic features into high-dimensional binary vectors, TrafficHD enables the rapid execution of recognition tasks within the constraints of real-time systems. Extensive evaluations on a wide range of network tasks show that TrafficHD is 30.57× and 98.32× faster than state-of-the-art (SOTA) machine learning and HDC algorithms while providing 3× higher robustness to network noise.

A few overlay processors for transformer networks emerge to achieve reconfigurable architectures and dynamic instructions. However, these processors consistently neglect exploring network sparsity, while existing sparse accelerators inefficiently utilize resources with separate computation parts. Furthermore, mainstream compilers for instruction generation are intricate and demand significant engineering efforts. In this work, we propose CSTrans-OPU, an FPGA-based overlay processor with full compilation for transformer networks via sparsity exploration. Specifically, we customize a multi-precision processing element (PE) array with DSP-packing for unified computation format with full resource utilization. Additionally, the introduced sorting and computation mode selection modules make it possible to explore the token sparsity. Moreover, equipped with a user-friendly compiler, CSTrans-OPU enables model parsing, operation fusion, model quantization, instruction generation and reordering directly from model files. Experimental results show that CSTrans-OPU achieves 6.92-20.06× speedup and 182.48× higher energy efficiency compared with CPU, and 1.47-3.85× latency reduction with 4.63-52.53× better energy efficiency compared with GPU. Furthermore, we observe up to 4.28× better latency and 4.94× higher energy efficiency compared with previously customized accelerators, and can be up to 1.93× faster and 4.39× more energy efficient than FPGA processors. To the best of our knowledge, our CSTrans-OPU is the first overlay processor for transformer networks considering sparsity.

MoE (Mixture-of-Experts) mechanism has been widely adopted in transformer-based models to facilitate further expansion of model parameter size and enhance generalization capabilities. However, the practical deployment of MoE mechanism for transformer on resource-constrained platforms, such as FPGA, remains challenging due to heavy memory footprints and impractical runtime costs introduced by the MoE mechanism. Diving into the MoE mechanism, we raise two key observations: (1) Expert weights are heavy but cold, making it ideal to leverage expert weight sparsity. (2) There exists highly skewed expert activation paths for MoE layers in transformer-based models, making it feasible to conduct expert prediction and prefetching. Motivated by these two observations, we propose FLAME, the first algorithm-hardware co-optimized MoE accelerating framework designed to fully leverage MoE sparsity for efficient transformer deployment on FPGA. First, to leverage expert weight sparsity, we integrate an N:M pruning algorithm, allowing for the pruning of expert weights without significantly compromising model accuracy. Second, to settle expert activation sparsity, we propose a circular expert prediction (CEPR) strategy. CEPR prefetches expert weights from external storage to on-chip cache before the activated expert index is determined. Last, we co-optimize both MoE sparsity through the introduction of an efficient pruning-aware expert buffering (PA-BUF) mechanism. Experimental results demonstrate that FLAME achieves 84.4% accuracy of expert prediction with merely two expert caches on-chip. In comparison with CPU and GPU, FLAME achieves 4.12× and 1.49× speedup, respectively.

Transformer models have become popular in various AI applications due to their exceptional performance. However, their impressive performance comes with significant computing and memory costs, hindering efficient deployment of Transformer-based applications. Many solutions focus on leveraging sparsity in weight matrix and attention computation. However, previous studies fail to exploit unified sparse pattern to accelerate all three modules of Transformer (QKV generation, attention computation and FFN). In this paper, we propose FNM-Trans, an adaptable and efficient algorithm-hardware co-design aimed at optimizing all three modules of the Transformer by fully harnessing N : M sparsity. At the algorithm level, we fully explore the interplay of dynamic pruning with static pruning under high N : M sparsity. At the hardware level, we develop a dedicated hardware architecture featuring a custom computing engine and a softmax module, tailored to support varying levels of N : M sparsity. Experiment results show that, our algorithm optimizes accuracy by 11.03% under 2:16 attention sparsity and 4:16 weight sparsity, compared to other methods. Additionally, FNM-Trans achieves speedups of 27.13× and 21.24× over Intel i9-9900X and NVIDIA RTX 2080 Ti, respectively, and outpaces current FPGA-based Transformers by 1.88× to 36.51×.

Graph Convolutional Networks (GCNs) have garnered significant attention in recent years, finding applications across various domains, including recommendation systems, knowledge graphs, and biological prediction. One prominent GCN-based recommendation model, LightGCN, optimizes embeddings for final prediction through graph convolution operations, and has achieved outstanding performance in commodity recommendation and molecular property prediction. However, LightGCN suffers from suboptimal layer combination parameters and limited nonlinear modeling capabilities on the software side. On the hardware side, due to the irregularity of the aggregation phase of LightGCN, CPU and GPU executions are not efficient, and designing a accelerator will be constrained by transmission bandwidth and the efficiency of the sparse matrix multiplication kernel. In this paper, we optimize the layer combination parameters of LightGCN by Q-learning and add hardware-friendly activation function to enhance its nonlinear modeling capability. The optimized LightGCN not only performs well on the original dataset and some molecular prediction tasks, but also does not incur significant hardware overhead. Subsequently, we propose an efficient architecture to accelerate the inference of LightGCN to improve its adaptability to real-time tasks. Comparing S-LGCN to Intel(R) Xeon(R) Gold 5218R CPU and NVIDIA RTX3090 GPU, we observe that S-LGCN is 1576.4 × and 21.8 × faster with energy consumption reductions of 3211.6 × and 71.6 ×, respectively. Compared to FPGA-based accelerator, S-LGCN demonstrates 1.5-4.5 × lower latency and 2.03 × higher throughput.

Stable Diffusion has become one of the mainstream image synthesis algorithms. The mainstream computing platform for Stable Diffusion is GPU. However, the deployment of Stable Diffusion on GPU still faces the problems of power consumption. With dedicated hardware design and optimization, FPGA based Stable Diffusion accelerator can achieve better performance of energy efficiency. In this paper, we propose SDAcc for realizing efficient inference of Stable Diffusion on FPGA. SDAcc is 4.40× faster than CPU. Compared to GPU and CPU, SDAcc achieves 1.27× and 19.66× energy efficiency improvement, respectively.

Field-Programmable Gate Array (FPGA) has shown great potential in accelerating Deep Neural Networks (DNNs) due to its characteristics of programmability and high power efficiency. In address the compilation challenges between DNNs and FPGA, we propose AutoHammer, an automated compiler for mapping DNNs to different FPGAs. Specifically, AutoHammer leverages overlay techniques to enable fast and effective implementation. Moreover, three enablers are integrated into AutoHammer. First, the Model Translator optimizes the topology and predicts a DNN's results based on different hardware configurations, built on top of a topology-based representation of DNNs. Second, the Instruction Generator generates pipeline data streams in various FPGA resource configurations by manipulating the instruction set at the upper level rapidly. Last, we realize the End-to-end Optimization, moving the whole computational processes onto the FPGA. Extensive experimental results show that AutoHammer improves great deployment efficiency when validated by 14 types of DNN models on 3 companies' (Xilinx, Fudan Micro, and Pango Micro) mainstream FPGA chips.

Recent years have witnessed Transformers emerge as a groundbreaking innovation in the Natural Language Processing (NLP) field. Unlike Recurrent Neural Network (RNN) models, Transformers process sequences in parallel, boosting accuracy for longer sequences. However, Transformers face challenges with extended processing time. This is particularly due to the requirement of padding inputs to match the longest sentence in a batch, thereby increasing computational demands. In this paper, we present Fitop-Trans, the first algorithm-hardware co-optimized framework using Fixed-Length Token Pruning strategy while deploying Transformers on FPGA. At the algorithmic level, we propose Fixed-Length Token Pruning. It is a novel pruning method which can maximize hardware efficiency in attention computation, aimed at eliminating unimportant tokens before the first layer. On the hardware side, a token selector is designed for Fixed-Length Token Pruning, which minimizes off-chip memory traffic. In addition, a partitionable Systolic Array (SA) is adopted, which is capable of handling varying input lengths and maximizing Digital Signal Processor (DSP) resource utilization. Furthermore, a scheduling module is designed to optimize hardware resource allocation and enhance pipeline attention throughput. Experimental results reveal that our hardware design on FPGA achieves a speedup of $580 \times$ and $6.39 \times$ in latency compared to Intel Xeon Gold CPU and NVIDIA GeForce RTX 3090.

Graph mining is an important and complex emerging algorithmic model with extensive applications in fields including social sciences, chemoinformatics, and bioinformatics. However, contemporary graph mining accelerators still face challenges related to excessive on-chip resource utilization, and low set processing efficiency. To address these issues, we propose FLOP, a memory-optimized processor that leverages a new on-chip and off-chip memory partitioning design scheme. First, FLOP's memory design can accommodate the varying memory requirements of graph vertex sets. Second, we devise input-size aware processing engines (PEs) to optimize resource utilization and maximize computation efficiency. Third, FLOP adopts a pattern-aware instruction set architecture and a two-stage compiler to satisfy the mining needs of different patterns. We evaluated FLOP using five commonly used datasets and different pattern mining tasks. Experiment results show that, FLOP outperforms the state-of-the-art FPGA-based accelerator Gramer by 3.09× ~ 15.93× and compared to the CPU-based design GraphPi, FLOP achieves an average of 6.55× speedup. Additionally, FLOP also has competitive performance compared to the ASIC-based design FINGERS.

Transformers have increasingly become the backbone of modern AI, excelling in tasks across natural language processing (NLP) and computer vision (CV). However, deploying them on resource-constrained platforms is challenging due to their high computational and energy demands. Previous efforts primarily focused on reducing the computational load of the self-attention module in Transformers, often neglecting optimization for other parts, like feed-forward network (FFN) modules. To address this gap, we propose FAS-Trans, an innovative algorithm-architecture co-design accelerator that efficiently optimizes both self-attention and FFN modules. FAS-Trans incorporates an innovative approximate prediction mechanism utilizing shifted-adders, which pre-estimates matrix sparsity to further reduce computational loads. This mechanism also enables reusing approximate prediction values in subsequent exact computations. Moreover, our approach includes cross-stage sparsity prediction for self-attention module to minimize computations involved in both QKV generation and attention computing. In the FFN module, we predict and exploit sparsity of FC1 block and employ low-precision multipliers for values close to zero, significantly cutting down FFN computational overhead. Our dedicated hardware architecture can effectively handle the irregularities of sparsity and multi-precision, ensuring high hardware resource utilization. Comprehensive evaluations across multiple benchmarks demonstrate that FAS-Trans reduces normalized computational overhead by 41.9% on average with 1% loss in accuracy. FAS-Trans can achieve 2.39-27.98× speedup and 18.9--72.6× energy efficiency improvement compared with CPU and GPU acceleration. Furthermore, we observe that FAS-Trans achieves 2.15--3.80× speedup, 1.87--19.89× improvement in throughput and 2.4--5.6× improvement in energy efficiency compared with other FPGA-based Transformer accelerators.

Binarized Transformer (BiT) networks have emerged as a notable advancement in artificial intelligence, reducing computational complexity by replacing traditional multiply-accumulate operations with simpler XNOR-popcount operations. This paper proposes Edge-BiT, a framework that employs software-hardware co-design to optimize BiT networks inference on edge FPGAs. We design a training method tailored for hardware acceleration, including the Exponential-Sparse Data Format (ESDF). This format is not only compatible with a broad range of existing BiT networks but also enhances their accuracy while reducing inference time on hardware platforms. Additionally, we develope a Compiler and an Instruction Set Architecture (ISA) based on a trigger-update mechanism to support inference across various BiT networks. On the hardware side, Edge-BiT features a unique Sparse Matrix XNOR Unit (SMXNOR) and an optimized Post Process Unit (PPU), both specifically tailored for efficient binary operations. Our empirical evaluations show that our training strategy, coupled with ESDF, increases the accuracy of BiT tasks by 4.6--34.1%. Edge-BiT significantly outperforms traditional CPU and GPU solutions, achieving speedups of up to 23.54× and 9.34×, respectively, and demonstrating up to 424.75× and 121.91× greater energy efficiency. Compared to existing FPGA accelerators for Transformer networks, Edge-BiT exhibits superior performance while utilizing fewer resources, achieving latency reductions of 1.16--2.78 × and improving energy efficiency by 1.34--7.43 ×. To the best of our knowledge, Edge-BiT is the first study on a software-hardware co-design framework for various BiT networks that achieves both high accuracy and excellent performance.

Deep Neural Networks (DNNs) have stimulated intensive FPGA-based acceleration solutions, and multi-die FPGAs offer abundant resources for implementing large-scale DNN workloads. However, current FPGA frameworks overlook the opportunities of optimization on multi-die FPGAs. In this paper, we propose an automated framework named DNNMapper, for mapping DNNs to multi-die FPGAs. With careful consideration of the unique architectural characteristics and resource constraints of multi-die FPGAs, DNNMapper involves model partitioning and resource allocation as two critical processes that map DNN layers onto respective FPGA dies and efficiently allocate hardware resources. DNNMapper employs a co-design engine based on a genetic algorithm, which co-optimizes model partitioning and resource allocation. Experimental results demonstrate that accelerators generated by DNNMapper offer superior performance and scalability, achieving up to 2× higher throughput and 1.3× to 1.9× higher DSP density. Moreover, our accelerator demonstrates a frequency improvement from 1.28× to 1.69×.

Field-programmable gate arrays (FPGAs) are an ideal candidate for accelerating graph neural networks (GNNs). However, the FPGA redeployment process is time-consuming when updating or switching between diverse GNN models across different applications. Existing GNN processors eliminate the need for FPGA redeployment when switching between different GNN models. However, adapting matrix multiplication types by switching processing units decreases hardware utilization. In addition, the bandwidth of DDR limits further improvements in hardware performance. This article proposes a highly flexible FPGA-based overlay processor for GNN accelerations. Graph-OPU provides excellent flexibility and programmability for users, as the executable code of GNN models is automatically compiled and reloaded without requiring FPGA redeployment. First, we customize the compiler and instruction sets for the inference process of different GNN models. Second, we customize the datapath and optimize the data format in the microarchitecture to fully leverage the advantages of high bandwidth memory (HBM). Third, we design a unified matrix multiplication to handle both sparse-dense matrix multiplication (SpMM) and general matrix multiplication (GEMM), enhancing Graph-OPU performance. During Graph-OPU execution, the computational units are shared between SpMM and GEMM instead of being switched, which improves the hardware utilization. Finally, we implement a hardware prototype on the Xilinx Alveo U50 and test the mainstream GNN models using various datasets. Experimental results show that Graph-OPU achieves up to 1,654 \(\times\) and 63 \(\times\) speedup, as well as up to 5,305 \(\times\) and 422 \(\times\) energy efficiency boosts, compared to implementations on CPU and GPU, respectively. Graph-OPU outperforms state-of-the-art (SOTA) end-to-end overlay accelerators for GNN, reducing latency by an average of 1.36 \(\times\) and improving energy efficiency by 1.41 \(\times\) on average. Moreover, Graph-OPU exhibits an average 1.45 \(\times\) speed improvement in end-to-end latency over the SOTA GNN processor. Graph-OPU represents an in-depth study of an FPGA-based overlay processor for GNNs, offering high flexibility, speedup, and energy efficiency.

In modern circuits, mixed-cell-height standard cells have been prevailing to meet various requirements and achieve better trade-offs among timing, power, and routability. Besides, the constraints of the minimum-implant-area (MIA) and drain-to-drain-abutment (DDA) arise as emerging challenges at advanced technology nodes. In this paper, we present an algorithm to address the mixed-cell-height placement problem with MIA and DDA constraints in three major stages: (1) post-global placement, (2) legalization, and (3) detailed placement. In the post-global stage, we first align mixed-cell-height standard cells to the desired rows by conjugate gradient method with dynamic step size and then reorder them by the shortest path algorithm to distribute the source nodes evenly. In the legalization stage, we propose a two-step combination algorithm to cluster cells and repack the clusters to minimize the wirelength, after which we presented a queue based method to address the inter-row MIA violations. In the detailed placement, an MIA-aware DDA reduction algorithm is adopted after multi-region partitioning to eliminate DDA violations without introducing MIA violations. Experimental results show that our algorithm can resolve all MIA and almost all DDA violations with a 13% reduction in displacement, a 4% reduction in HPWL, and 25% less runtime compared with the state-of-the-art work.

Deep learning models rely on highly optimized tensor libraries for efficient inference on heterogeneous hardware. Current deep compilers typically predetermine layouts of tensors and then optimize loops of operators. However, such unidirectional and one-off workflow strictly separates graph-level optimization and operator-level optimization into different system layers, missing opportunities for unified tuning.

Transformer-based models have achieved remarkable performance across various tasks, while the computational complexity presents an obstacle for deploying on resource-constrained devices. To this end, this paper proposes an efficient approximation framework termed NPLA for approximating non-linear operations during Transformer inference on hardware accelerators. Specifically, NPLA enables the approximation of non-linear operations using non-uniform piecewise linear functions and directly converts coefficients into LUTs for hardware implementation. Experimental results demonstrate that NPLA can reduce the hardware cost by 13.43× in LUTs and 1.98× in DSP compared to the state-of-the-art method.

Existing implementations of transformer networks by field-programmable gate array (FPGA) focus only on attention computation, or suffer from fixed model structure without flexibility. In this article, we propose an FPGA-based overlay processor, named Transformer-OPU for general accelerations of transformer networks. Experimental result shows that our Transformer-OPU achieves 5.19-15.06× and 1.14-2.89× speedup compared with CPU and GPU, respectively. We also observe 1.10-2.47× better latency compared with previously customized FPGA accelerators, and is 1.45× faster than NPE.

Neural Radiance Field (NeRF) is a state-of-the-art algorithm in the field of novel view synthesis and has the potential to be used in AR/VR. However, the inference of NeRF is time-consuming. Motivated by resource-constraint scenarios on the edge and mixed reality devices, our essential idea is to bridge this gap while improving throughput and power consumption. This paper proposes a high-performance FPGA-based accelerator, with a fully-pipelined design tailored for the vanilla NeRF algorithm. We also design a mechanism to monitor the output of the rendering module to reduce operations. Experimental results show that our accelerator achieves 3.63× energy efficiency over implementation on GPU NVIDIA V100, and 1.31× speed up over state-of-the-art ASIC design if running under the same clock frequency as ASIC.

Graph Neural Networks (GNNs) have outstanding performance on graph-structured data and have been extensively accelerated by field-programmable gate array (FPGA) in various ways. However, existing accelerators significantly lack flexibility, especially in the following two aspects: 1) Many FPGA-based accelerators only support one GNN model. 2) The processes of re-synthesizing and bitstream re-generating are very time-consuming for new GNN models. To this end, we propose a highly integrated FPGA-based overlay processor for general GNN accelerations named Graph-OPU. Regarding the data structure and operation irregularity, we customize the instruction sets to support irregular operation patterns in the inference process of GNN models. Then, we customize our datapath and optimize the data format in the microarchitecture to take full advantage of high bandwidth memory (HBM). Moreover, we design the computation module to ensure a unified and fully-pipelined process of sparse matrix multiplication (SpMM) and general matrix multiplication (GEMM). Users can avoid the process of FPGA reconfiguration or RTL regeneration for the newly invented GNN models. We implement the hardware prototype on Xilinx Alveo U50 and test the mainstream GNN models with 9 datasets. Graph-OPU can achieve an average of 435× and 18× speedup, while 2013× and 109× better energy efficiency, compared with the Intel I7-12700KF processor and NVIDIA RTX3090 GPU, respectively. To the best of our knowledge, Graph-OPU is the first in-depth study on FPGA-based general processors for GNN acceleration with high speedup and energy efficiency.

Existing accelerators for transformer networks with field-programmable gate array (FPGA) either focus only on attention computation or suffer from fixed data streams without flexibility. Moreover, compression and approximation methods of transformer networks have the potential for further optimization. In this article, we propose a low-latency FPGA-based overlay processor, named LTrans-OPU for general accelerations of transformer networks. Specifically, we design a domain-specific overlay architecture, including a computation unit for matrix multiplication of arbitrary dimensions. An instruction set customized for our overlay architecture is also introduced, dynamically controlling data flows by generated instructions. In addition, we introduce a hybrid pruning method common to various transformer networks, along with an efficient non-linear function approximation method. Experimental results show that our design is rather competitive and has low latency. LTrans-OPU achieves 11.10-32.20× speedup compared with CPU and 2.44-6.18 × latency reduction compared with GPU. We also observe 2.36-12.43 × lower latency compared with customized FPGA/ASIC accelerators, and can be 3.10× faster than NPE.

Field-programmable gate array (FPGA) is an ideal candidate for accelerating graph neural networks (GNNs). However, FPGA reconfiguration is a time-consuming process when updating or switching between diverse GNN models across different applications. This paper proposes a highly integrated FPGA-based overlay processor for GNN accelerations. Graph-OPU provides excellent flexibility and software-like programmability for GNN end-users, as the executable code of GNN models are automatically compiled and reloaded without requiring FPGA reconfiguration. First, we customize the instruction sets for the inference qprocess of different GNN models. Second, we propose a microarchitecture ensuring a fully-pipelined process for GNN inference. Third, we design a unified matrix multiplication to process sparse-dense matrix multiplication and general matrix multiplication to increase the Graph-OPU performance. Finally, we implement a hardware prototype on the Xilinx Alveo U50 and test the mainstream GNN models using various datasets. Graph-OPU takes an average of only 2 minutes to switch between different GNN models, exhibiting average 128× speedup compared to related works. In addition, Graph-OPU outperforms state-of-the-art end-to-end overlay accelerators for GNN, reducing latency by an average of 1.36× and improving energy efficiency by an average of 1.41×. Moreover, Graph-OPU achieves up to 1654× and 63× speedup, as well as up to 5305× and 422× energy efficiency boosts, compared to implementations on CPU and GPU, respectively. To the best of our knowledge, Graph-OPU represents the first in-depth study of an FPGA-based overlay processor for GNNs, offering high flexibility, speedup, and energy efficiency.

Machine learning has been used extensively in the bioactivity value (BAV) prediction of G Protein-Coupled Receptors (GPCR) targeting ligands. However, the performance of over 140 types of GPCR endogenous ligands, also called orphan GPCRs (oGPCRs), is still unsatisfactory due to the limited sample size. Also, current works are far from meeting the demand for fast inference time and energy efficiency. We propose the Multi-Source Transfer-Graph Attention Network (MSTL-GAT), as well as its FPGA-based accelerator. Firstly, we make use of the three ideal data sources for transfer learning, oGPCRs, experimentally validated GPCRs, and invalidated GPCRs similar to the former one. Secondly, we transform GPCRs from the SIMLEs format to graphics as the input of GAT to improve prediction accuracy. Moreover, we propose an FPGA-based accelerator tailored for the inference phase of MSTL-GAT. Finally, our experimental results show that MSTL-GAT remarkably improves the prediction of GPCRs ligand activity value compared with previous studies. On average, the two evaluation indexes we adopt, R2 and RMSE, improve by 34.76% and 13.16%, respectively. The proposed FPGA accelerator achieves 2.7× and 4.7× speedup, 29.7×, and 3.6× energy efficiency compared with works on GPU implementation and the state-of-the-art FPGA accelerator, respectively.

Non-linear activation function plays an essential role in neural networks (NNs) for their generalization ability. However, deploying the intricate mathematical operations on hardware platforms like Field-Programmable Gate Array (FPGA) turns out a great challenge. Prior works based on piecewise functions or look-up table (LUT) either involve complex manual operations or neglect hardware overhead. To this end, this paper proposes a simple yet scalable and effective approximation called DIF-LUT, which is applicable to various non-linear functions. Specifically, the proposed method can achieve accurate approximation by piecewise linear matching to fit the function derivative roughly and range addressable LUT to offset the difference. Moreover, self-adaptive mechanisms are applied to automatically minimize hardware cost in terms of different accuracies. The experiments show that compared to state-of-the-art methods, DIF-LUT costs 43.68% fewer LUTs and 70.8% fewer flip-flops (FFs) without any digital signal processor (DSP), while achieving 2.7x approximation accuracy at 554.1MHz on Xilinx Zynq UltraScale+.

Transformer-based models has achieved remarkable success in extensive tasks for natural language processing. To face the variable-length sentences in human language, popular deep learning frameworks rely on zero padding for batch processing, which introduces significant computation and memory overhead. Existing works attempt to eliminate padding redundancy but results in low hardware efficiency due to the mismatch between the variable shape of operations and fixed shape of processing elements (PEs). This paper proposes a reconfigurable systolic array with token packing in three folds to boost hardware efficiency. First, matrix multiplications for different tokens can be packed along the array columns to improve spatial efficiency. Meanwhile, for temporal efficiency, we develop a coarse-grained pipeline for attention, where stages can run on different parts of the array at the same time. We further exploit the masking redundancy in the Transformer decoder with runtime reconfigurable inter-PE connection and buffer switching. Applied to GPT, our FPGA design has achieved 1.16× higher normalized throughput and 1.94× better runtime MAC utilization over the state-of-the-art GPU performance for variable-length input sequences from GLUE and SQuAD dataset.

Transformer-based models suffer from large num-ber of parameters and high inference latency, whose deployment are not green due to the potential environmental damage caused by high inference energy consumption. In addition, it is difficult to deploy such models on devices, especially on resource constrained devices such as FPGA. Various model pruning methods are proposed to shrink the model size and resource consumption, so as to fit the models on hardware. However, such methods often introduce floating point of operations (FLOPs) as an agent of hardware performance, which is not accurate. Furthermore, structural pruning methods are always in a single head-wise or layer-wise pattern, which fails to compress the models to the extreme. To resolve the above issues, we propose a green BERT deployment method on FPGA via hardware-aware and hybrid pruning, named g-BERT. Specifically, two hardware-aware metrics are introduced by High Level Synthesis (HLS) to evaluate the latency and power consumption of inference on FPGA, which can be optimized directly while pruning. Moreover, we simultaneously consider pruning of heads and full encoder layers. To efficiently find the optimal structure, g-BERT applies differentiable neural architecture search (NAS) with a special 0–1 loss function. Compared with the BERT-base, g-BERT achieves$2.1\times$speedup,$1.9\times$power consumption reduction and$1.8\times$model size reduction with comparable accuracy, on par with the state-of-the-art methods.

Convolutional Neural Networks (CNNs), a widely recognized deep learning algorithm, have been utilized in various domains such as smart cities and healthcare. However, the remarkable performance of CNNs is accompanied by high resource overhead and deployment complexity. To address these challenges, CNN compilers have been developed to simplify convolutional operations for edge device deployment. One of the crucial components in CNN models is the General Matrix Multiply (GEMM) operation, which serves as the main computational kernel. In previous studies, efforts were made to improve the computation speed of GEMM by modifying the matrix calculation sequence, but they did not fully exploit the computing resources of edge devices. In this paper, we propose a novel GEMM-based acceleration algorithm, named microGEMM. The microGEMM algorithm divides convolutional data to reduce the memory access times during the GEMM calculation process. Moreover, the algorithm employs instruction-level optimization in the GEMM calculation unit, decreasing the cache miss rate. To better evaluate the superiority of microGEMM on resource-constrained devices, two edge-oriented metrics are proposed, namely CCPS & CCPoE. The microGEMM algorithm is implemented in C++ and compared with the standard GEMM algorithm (naiveGEMM) and the GEMM of the open-source Basic Linear Algebra Subprograms (BLAS) library (openblasGEMM). The experimental results demonstrate that microGEMM achieves a significant speedup, ranging from 5.67 × to 14.19 ×, compared to naiveGEMM.

There are already some works on accelerating transformer networks with field-programmable gate array (FPGA). However, many accelerators focus only on attention computation or suffer from fixed data streams without flexibility. Moreover, their hardware performance is limited without schedule optimization and full use of hardware resources. In this article, we propose a flexible and efficient FPGA-based overlay processor, named FET-OPU. Specifically, we design an overlay architecture for general accelerations of transformer networks. We propose a unique matrix multiplication unit (MMU), which consists of a processing element (PE) array based on modified DSP-packing technology and a FIFO array for data caching and rearrangement. An efficient non-linear function unit (NFU) is also introduced, which can calculate arbitrary single input non-linear functions. We also customize an instruction set for our overlay architecture, dynamically controlling data flows by instructions generated on the software side. In addition, we introduce a two-level compiler and optimize the parallelism and memory allocation schedule. Experimental results show that our FET-OPU achieves 7.33-21.27× speedup and 231× less energy consumption compared with CPU, and 1.56-4.08× latency reduction with 5.85-66.36× less energy consumption compared with GPU. Furthermore, we observe 1.56-8.21× better latency and 5.28-6.24× less energy consumption compared with previously customized FPGA/ASIC accelerators and can be 2.05× faster than NPE with 5.55× less energy consumption.

Transformer models have been widely adopted in the field of Natural Language Processing (NLP) and Computer Vision (CV). However, the excellent performance of Transformers comes at the cost of heavy memory footprints and gigantic computing complexity. To deploy Transformers on resource constrained platforms, e.g., FPGA, diverse weight pruning strategies have been proposed. However, pattern pruning, as an alternative pruning method, is not well explored in the context of Transformers. In this paper, we propose PP-Transformer, a framework specifically designed to efficiently deploy Transformer models on FPGA using pattern pruning. At the algorithm level, we leverage pattern pruning, a coarse-grained structured pruning strategy, to reduce parameter storage. Meanwhile, we have developed a dedicated hardware architecture, featuring a custom computing engine tailored to support pattern pruning algorithm. Experimental results demonstrate that our algorithm achieves up to$2.26\times$reduction in parameter storage with acceptable accuracy degradation. Additionally, our hardware implementation exhibits$839.72\times$and$5.72\times$speedup in comparison to CPU and GPU implementations.

The approximation of non-linear operation can simplify the logic design and save the system resources during the neural network inference on Field-Programmable Gate Array (FPGA). Prior work can approximate the non-linear operations with piecewise linear (PWL) function, but such approximation neglects considering the hardware overhead simultaneously. This paper proposes a novel approximation framework called Auto-LUT, which leverages a neural network to automatically approximate the non-linear operations. The framework formulates the approximation error and hardware overhead as a multi-objective optimization problem and employs an automated search mechanism to find the minimum number of segments and data bit width. To improve the approximation accuracy, we propose a bias clipping operation during the training of approximation networks, which enforces the model to approximate within the range of interest. Moreover, a hardware-friendly quantization scheme is further introduced to simulate the hardware behavior, thereby reducing the hardware overhead. Finally, a customized hardware architecture based on FPGA is utilized to deploy the quantized result. The experimental results show that Auto-LUT costs 56.32% less LUTs and 32.31% less flip-flops (FF) while reducing 4.32% approximation error compared to the state-of-the-art method.

Conjugate gradient (CG) is widely used in training sparse neural networks. However, CG, involving a large amount of sparse matrix and vector operations, cannot be efficiently implemented on resource-limited edge devices. In this paper, a high-performance and energy-efficient CG accelerator implemented on edge Field Programmable Gate Array is proposed for fast onsite neural networks training. According to the profiling, we propose a unified matrix multiplier that is compatible with the sparse and dense matrix. We also design a novel T-engine to handle transpose operation with the compressed sparse format. Experimental results show that our proposal outperforms the state-of-the-art FPGA work with a resource reduction of up to 41.3%. In addition, we achieve on average$10.2\times$and$2.0\times$speedup, while$10.1\times$and$3.5\times$better energy efficiency than implementations on CPU and GPU, respectively.

Symmetric Sparse Matrix-Vector Multiplication (SSpMV) is a prevalent operation in numerous application domains (e.g., physical simulations, machine learning, and graph processing). Existing researches focus on the SSpMV implementation and its improvement on high-performance computing platforms but ignore the resource-limited edge platforms due to the main challenges: memory access overload and limited computing parallelism feasibility. To this end, this paper proposes an embedded-FPGA-based hardware accelerator for SSpMV, called eSSpMV. We first propose an optimized data format, named Symmetric Compressed Sparse Row (SCSR), to reduce memory consumption. Moreover, a fully-pipelined computation unit is proposed to be compatible with the optimized data format. Experimental results show that eSSpMV outperforms the state-of-the-art FPGA implementation for 2.9 x speedup, while still achieving a computing resource reduction of 39.3% and 32.3% for LUT and DSP, respectively. As for edge CPU and GPU implementations, eSSpMV achieves 9.3x speedup over CPU while acquiring 13.1 x better power latency product than GPU.

In this paper, we present the Integer Lightweight Softmax (ILS) algorithm for approximating the Softmax activation function. The accurate implementation of Softmax on FPGA can be huge resource-intensive and memory-hungry. Then, we present the implementation of ILS on a Xilinx XCKU040 FPGA to evaluate the effectiveness of ILS. Evaluations on CIFAR 10, CIFAR 100 and ImageNet show that ILS achieves up to$2.47\times, 40\times$and$323\times$speedup over CPU implementation, and$4\times, 63\times$and$51\times$speedup over GPU implementation, respectively. In comparison to previous FPGA-based Softmax implementations, ILS strikes a better balance between resource consumption and precision accuracy.

Industrial Internet of Things (IIoT) is experiencing rapid developments in the era of Industry 4.0. However, the ever-increasing applications put forward higher requirements for authentication. Facing such a problem, researchers combine two cutting-edge techniques, i.e., physical unclonable function (PUF) and blockchain. In detail, PUF can generate multiple challenge–response pairs (CRPs) for IIoT devices by leveraging their unique physical features. Moreover, blockchain platforms are employed for storing/synchronizing CRPs, thereby resisting the single-point failure. Although realizing the unclonable authentications, the existing works ignore the device heterogeneity of IIoT and fail to develop the specified blockchain platform for supporting PUF. In this article, we present a hybrid-PUF-based consortium blockchain for IIoT authentication, named HPCchain. Specifically, we first present the notion of hybrid-PUF, which assigns different devices to generate different types of PUFs, and then employs them to play different roles in HPCchain. In this way, we can overcome the IIoT heterogeneity. Moreover, we propose the PUF-empowered credit scheme for HPCchain and realize the dynamic endorsement with which we develop a PUF-based consensus mechanism for HPCchain. Finally, we design the registration and authentication schemes for IIoT nodes, atop HPCchain. Extensive experiments demonstrate the validity of our proposals.

With the continuing growth of voice-controlled devices, voice metrics have been widely used for user identification. However, voice biometrics is vulnerable to replay attacks and ambient noise. We identify that the fundamental vulnerability in voice biometrics is rooted in its indirect sensing modality (e.g., microphone). In this paper, we presentVocalPrint, a resilient mmWave interrogation system which directly captures and analyzes the vocal vibrations for user authentication. Specifically,VocalPrintexploits the unique disturbance of the skin-reflect radio frequency (RF) signals around the near-throat region of the user, caused by the vocal vibrations. The complex ambient noise is isolated from the RF signal using a novel resilience-aware clutter suppression approach for preserving fine-grained vocal biometric properties. Afterward, we extract the vocal tract and vocal source features and input them into an ensemble classifier for authentication.VocalPrintis practical as it allows the effortless transition to a smartphone while having sufficient usability due to its non-contact nature. Our experimental results from 41 participants with different interrogation distances, orientations, and body motions show thatVocalPrintachieves over 96 percent authentication accuracy even under unfavorable conditions. We demonstrate the resilience of our system against complex noise interference and spoof attacks of various threat levels.

Graph convolutional networks (GCNs) have been introduced to effectively process non-Euclidean graph data. However, GCNs incur large amounts of irregularity in computation and memory access, which prevents efficient use of traditional neural network accelerators. Moreover, existing dedicated GCN accelerators demand high memory volumes and are difficult to implement onto resource limited edge devices. In this work, we propose LW-GCN, a lightweight FPGA-based accelerator with a software-hardware co-designed process to tackle irregularity in computation and memory access in GCN inference. LW-GCN decomposes the main GCN operations into Sparse Matrix-Matrix Multiplication (SpMM) and Matrix-Matrix Multiplication (MM). We propose a novel compression format to balance workload across PEs and prevent data hazards. Moreover, we apply data quantization and workload tiling, and map both SpMM and MM of GCN inference onto a uniform architecture on resource limited hardware. Evaluation on GCN and GraphSAGE are performed on Xilinx Kintex-7 FPGA with three popular datasets. Compared to existing CPU, GPU, and state-of-the-art FPGA-based accelerator, LW-GCN reduces latency by up to 60×, 12×, and 1.7× and increases power efficiency by up to 912×, 511×, and 3.87×, respectively. Furthermore, compared with NVIDIA’s latest edge GPU Jetson Xavier NX, LW-GCN achieves speedup and energy savings of 32× and 84×, respectively.

The fast-growing capacity and complexity are challenging for FPGA global placement. Besides, while many recent studies have focused on the eDensity-based placement as its great efficiency and quality, they suffer from redundant frequency translation. This paper presents a CNN-inspired analytical placement algorithm to effectively handle the redundant frequency translation problem for large-scale FPGAs. Specifically, we compute the density penalty by a fully-connected propagation and gradient to a discrete differential convolution backward. With the FPGA heterogeneity, vectorization plays a vital role in self-adjusting the density penalty factor and the learning rate. In addition, a pseudo net model is used to further optimize the site constraints by establishing connections between blocks and their nearest available regions. Finally, we formulate a refined objective function and a degree-specific gradient preconditioning to achieve a robust, high-quality solution. Experimental results show that our algorithm achieves an 8% reduction on HPWL and 15% less global placement runtime on average over leading commercial tools.

In the drug discovery process, the biological activity value (BAV) of G Protein-Coupled Receptors (GPCRs) targeting ligands is a large consideration. Past BAV prediction on CPU consumes tremendous time and power, yet there is rarely any related acceleration research. Therefore, this paper proposes a series of heterogeneous FPGA-based accelerators for well-performing algorithms to predict GPCRs ligands BAV. Communication delay is reduced by compressing the sparse matrix and directly coupling accelerators on the system BUS. Computation is accelerated by the remapping during the weight storage. Experimental results show that our FPGA accelerator implemented on Xilinx XCZU7EV performs 54.5× faster than CPU and 35.2× more energy-efficient than GPU.

Graph Convolutional Networks (GCNs) have shown great results but come with large computation costs and memory overhead. Recently, sampling-based approaches have been proposed to alter input sizes, which allows large GCN workloads to align to hardware constraints. Motivated by this flexibility, we propose an FPGA-based GCN accelerator, named SkeletonGCN, along with multiple software-hardware co-optimizations to improve training efficiency. We first quantize all feature and adjacency matrices of GCN from FP32 to SINT16. We then simplify the non-linear operations to better fit the FPGA computation, and identify reusable intermediate results to eliminate redundant computation. Moreover, we employ a linear time sparse matrix compression algorithm to further reduce memory bandwidth while allowing efficient decompression on hardware. Finally, we propose a unified hardware architecture to process sparse-dense matrix multiplication (SpMM) and dense matrix multiplication (MM), all on the same group of PEs to increase DSP utilization on FPGA. Evaluation is performed on a Xilinx Alveo U200 board. Compared with existing FPGA-based accelerator on the same network architecture, SkeletonGCN can achieve up to 11.3x speedup while maintaining the same training accuracy. In addition, SkeletonGCN can achieve up to 178x and 13.1x speedup over state-of-art CPU and GPU implementation on popular datasets, respectively.

Convolutional neural network (CNN) accelerator has been gradually deployed on edge Field-Programmable Gate Arrays (FPGAs) for satellite remote sensing. However, the considerable complexity of software/hardware co-design inhibits the development of data processing applications on edge FPGAs. Moreover, the performance of edge FPGAs is restricted due to limited bandwidth and excessive software/hardware communication overhead in satellite remote sensing. To reduce co-design complexity, we propose a software/hardware data mapping framework for the deployment efficiency of the remote sensing data accelerator, called Fast-Pipe. Especially the software design of Fast-Pipe takes into account the interaction requirements of accelerator deployment and the poll and copy latency of data transfers. The data transfer driver is implemented in the user space to reduce latency with a new scheduling method and an interrupt policy for sending and receiving data. Meanwhile, an associated hardware structure is designed with Direct Memory Access (DMA) to implement data scheduling and mapping. With Fast-Pipe, the data in the software buffer is mapped into multiplexed data streams. Experimental results show that Fast-Pipe speed up 46.38× in small data transfer, and average 2× higher in large data transfer than previous work with stable data transfer speed.

As an emerging technique, blockchain becomes widely-adopted in numerous fields, including supply chain, cloud computing, smart healthcare, etc. Nonetheless, some drawbacks, especially the high resource cost, also expose with the deepening of blockchain applications. Moreover, we lack the standard tools for benchmarking blockchain’s resource efficiency. In this case, even researchers keep on proposing lightweight blockchains, we have no idea about their actual validity. Generally speaking, two daunting challenges are yet to be addressed, i.e., the compatible framework and the resource-oriented benchmarking metrics. Motivated by such facts, this paper presents a resource-oriented blockchain benchmarking tool, named BCadvisor. Specifically, we develop a modular architecture, with three collaborating models. Such framework not only realizes a pipeline for data parsing, metric storage, and result visualization but also can easily support any new blockchain. Furthermore, we design a novel process named Three-step Resource-oriented Benchmarking (TsRoB), which divides the blockchain into 4 layers and evaluates the resource efficiency of each layer. Finally, we conduct comprehensive benchmarking on four representative blockchains and discuss the results. Our experiments can serve as a guideline for researchers in pursuing green blockchain running.

Serverless edge computing is booming as an efficient carrier of deploying complex applications composed of dependent functions, whose assignment decisions highly influence the application performance. Although similar problem has been widely studied, none of existing approaches considers the diversity of communication styles, which is specially introduced in serverless computing and also imposes high influence to the performance efficiency. We compare two communication styles, called direct-passing and remote-storage, to transmit intermediate data between functions. We find that there is no single communication style that can prevail under all scenarios and the optimal selection depends on several factors, such as fanout degree, data size, and network bandwidth. Hence, how to select the appropriate communication style for each inter-function communication link, together with the function assignment decision, is essential to the application performance. To this end, we propose a Priority-based ASsignment and Selection (PASS) algorithm with joint consideration of function assignment and communication style selection. We theoretically analyze the approximation ratio of PASS algorithm and extensive experiments on real-world applications show that PASS can averagely reduce the completion time by 24.1% in comparison with state-of-the-art approaches.

With the ever-increasing applications of the Internet of Things (IoT), e.g., smart homes, smart cities, smart factories, etc., data security and device trustworthiness become the major concerns. Although blockchain contributes to achieve the data traceability and fault tolerance, the huge resource consumption and limited performance severely restrict its deployments in IoT. Moreover, the unique features of IoT, such as mobility, resource constraints, and security vulnerabilities, create even greater difficulties for blockchain running. Observing the lack of blockchain analyzing tools for IoT, we intend to provide a fair means with standard metrics for better understanding IoT-oriented blockchain. In this article, we present BCmaster, a blockchain analyzing and monitoring framework focusing on IoT scenarios. Based on the detailed modeling of blockchain-assisted IoT, we propose a novel metric set named 5-D quantitative metric framework, which can conduct the comprehensive blockchain analysis from five dimensions. Moreover, we design a modular architecture for BCmaster, wherein the interaction requests (IRs)-based data parser ensures a high system compatibility and the synchronous metric visualizer facilitates the real-time blockchain monitoring in IoT. Extensive evaluations in a real IoT environment demonstrate the validity of BCmaster and explore the performance of four IoT-oriented blockchain systems. Last but not least, we discuss the ways to customize IoT-oriented blockchain with the help of BCmaster.

Data collection in big data is an effective way to aggregate information that the collector is interested in. However, there is no assurance for the data that the users provide. Since collector does not have the ability to check the authenticity of every piece of information, the trustworthiness of users participated in the collection become important. In this paper, we design an efficient approach to calculate users’ trustworthiness in data collection for big data context. We divide the trustworthiness into familiarity trustworthiness and similarity trustworthiness, and study the influences of user actions on trustworthiness. To prevent malicious users from raising their trustworthiness and providing false information that may mislead final results, we also design a security queue to record users’ historical trust information, so that we can detect malicious users with high accuracy. Simulation results show that our model can sensitively resist the malicious actions of users.

Currently, increasing attention is devoted to artificial intelligence (AI) enabled software defined industrial networks (AI-SDINs). Toward energy-efficient and secure data transmission in AI-SDINs, a metric called energy-cost-per-useful-bit (ECPUB), which means energy cost of transmitting per useful bit is presented to evaluate energy efficiency and a novel energy-efficiency based secure multipath routing scheme is then put forward. Specifically, the ECPUB incorporates the utility and the law of diminishing marginal utility, for revealing the relationship among energy consumption, residual energy, and useful bits required. Moreover, in this article, an energy-efficiency based secure multipath routing scheme (E2SMR) is proposed by adopting the ECPUB and (t,n) threshold secret sharing scheme, for enhancing the security under the premise of guaranteeing energy efficiency. Extensive simulation results show that ECPUB can evaluate the energy efficiency and facilitate the balance of network load, while E2SMR can prolong the lifetime of the network and simultaneously ensure the network functionality securely.

Due to the premise of uniqueness and acceptance, fingerprint has been the most adopted biometric technologies in high-impact applications (e.g., smartphone security, monetary transactions and international-border verification). Although there are an array of commercial fingerprint scanners across different sensing modalities including optical, capacitive, thermal and ultrasonic, existing fingerprint technologies are vulnerable to spoofing attacks via fake-finger in Kanget al., 2003. In this paper, we investigate a new dimension of fingerprint sensing based on the friction-excited sonic wave (in simpler words, ”voice of fingerprint”) from a user swiping his fingertip on everyday surfaces. Specifically, we developSonicPrintto leverage the intrinsic fingerprint ridge information in sonic wave for user identification. First, the complex ambient noise is isolated from the sonic wave using background isolation and adaptive segmentation models. Afterward, a series of multi-level friction descriptors that highlight the target fingerprint information is extracted. These descriptors are fed to a specially designed ensemble classifier for user identification.SonicPrintis practical as it leverages in-built microphones in smart devices, requiring no hardware modifications. As the first exploratory study, our experimental results with 31 participants over three different swipe actions on 12 different types of materials show up to a 98 percent identification accuracy.

Low-precision data representation is important to reduce storage size and memory access for convolutional neural networks (CNNs). Yet, existing methods have two major limitations: (1) requiring re-training to maintain accuracy for deep CNNs and (2) needing 16-bit floating-point or 8-bit fixed-point for a good accuracy. In this article, we propose a low-precision (8-bit) floating-point (LPFP) quantization method for FPGA-based acceleration to overcome the above limitations. Without any re-training, LPFP finds an optimal 8-bit data representation with negligible top-1/top-5 accuracy loss (within 0.5%/0.3% in our experiments, respectively, and significantly better than existing methods for deep CNNs). Furthermore, we implement one 8-bit LPFP multiplication by one 4-bit multiply-adder and one 3-bit adder, and therefore implement four 8-bit LPFP multiplications using one DSP48E1 of Xilinx Kintex-7 family or DSP48E2 of Xilinx Ultrascale/Ultrascale+ family, whereas one DSP can implement only two 8-bit fixed-point multiplications. Experiments on six typical CNNs for inference show that on average, we improve throughput by over existing FPGA accelerators. Particularly for VGG16 and YOLO, compared to six recent FPGA accelerators, we improve average throughput by 3.5 and 27.5 and average throughput per DSP by 4.1 and 5 , respectively.

Panoramic X-ray (PX) provides a 2D picture of the patient's mouth in a panoramic view to help dentists observe the invisible disease inside the gum. However, it provides limited 2D information compared with cone-beam computed tomography (CBCT), another dental imaging method that generates a 3D picture of the oral cavity but with more radiation dose and a higher price. Consequently, it is of great interest to reconstruct the 3D structure from a 2D X-ray image, which can greatly explore the application of X-ray imaging in dental surgeries. In this paper, we propose a framework, named Oral-3D, to reconstruct the 3D oral cavity from a single PX image and prior information of the dental arch. Specifically, we first train a generative model to learn the cross-dimension transformation from 2D to 3D. Then we restore the shape of the oral cavity with a deformation module with the dental arch curve, which can be obtained simply by taking a photo of the patient's mouth. To be noted, Oral-3D can restore both the density of bony tissues and the curved mandible surface. Experimental results show that Oral-3D can efficiently and effectively reconstruct the 3D oral structure and show critical information in clinical applications, e.g., tooth pulling and dental implants. To the best of our knowledge, we are the first to explore this domain transformation problem between these two imaging methods.

Convolutional neural networks (CNNs) have achieved extensive success on miscellaneous artificial intelligence applications such as image classification and object detection. A plethora of models emerge with different operators and architectures, gradually shifting attention from accuracy to efficiency in terms of speed and power, since VGG-like architecture from early stage has significant redundancy. Light-weight CNNs are proposed to reduce computation complexity and parameter amount. MobileNets, one typical example of light-weight CNNs, adopt depthwise separable convolution, while others such as SqueezeNet alter model topology to spare computation power.

In recent years, transformer-based models have shown state-of-the-art results for Natural Language Processing (NLP). In particular, the introduction of the BERT language model brought with it breakthroughs in tasks such as question answering and natural language inference, advancing applications that allow humans to interact naturally with embedded devices. FPGA-based overlay processors have been shown as effective solutions for edge image and video processing applications, which mostly rely on low precision linear matrix operations. In contrast, transformer-based NLP techniques employ a variety of higher precision nonlinear operations with significantly higher frequency. We present NPE, an FPGA-based overlay processor that can efficiently execute a variety of NLP models. NPE offers software-like programmability to the end user and, unlike FPGA designs that implement specialized accelerators for each nonlinear function, can be upgraded for future NLP models without requiring reconfiguration. NPE can meet real-time conversational AI latency targets for the BERT language model with 4x lower power than CPUs and 6x lower power than GPUs. We also show NPE uses 3x fewer FPGA resources relative to comparable BERT network-specific accelerators in the literature. NPE provides a cost-effective and power-efficient FPGA-based solution for Natural Language Processing at the edge.

Low precision quantization in convolutional neural network (CNN) inference has been proved effective for reducing computation complexity and bandwidth requirement. Mixed precision CNNs manage to benefit from low precision while maintaining accuracy. In this paper, we propose a Mixed Precision FPGA-based Overlay Processor (MP-OPU) to fully leverage the advantages of mixed precision for both conventional and lightweight CNNs. The micro-architecture of MP-OPU considers sharing of computation core with mixed precision weights and activations to improve computation efficiency. In addition, run-time scheduling of external memory access and data arrangement are optimized to further leverage the advantages of mixed precision data representation. Our experimental results show that MP-OPU reaches 4.92 TOPS peak throughput when implemented on the Xilinx VC709 FPGA (with all DSPs configured to support 2-bit multipliers). Moreover, MP-OPU achieves 12.9 × latency reduction and 2.2 × better throughput/DSP for conventional CNNs while 7.6× latency reduction and 2.9× better throughput/DSP for lightweight CNNs, all on average compared with existing FPGA accelerators/processors, respectively. To the best of our knowledge, this is the first in-depth study on mixed precision FPGA-based overlay processor for both conventional and lightweight CNNs.

In big data era, utilizing the parameter server paradigm has been regarded as an efficient and practical way to improve performance in processing deep learning (DL) applications. One of the main problems is that straggler greatly hinders DL training progress, but the previous methods cannot fully consider the resource utilization of the cluster when dealing with straggler. To mitigate straggler problem in parameter server, we propose a Deep Reinforcement Learning (DRL)-based framework called Distributed Actor-critic Reinforcement Learning (DARL) that can automatically adapt each worker's training load to the dynamic cluster without parameter settings. DARL employs state-of-the-art techniques to stabilize training and improve convergence, including distributed framework, multiple actors and prioritized experience replay. Meanwhile, we also apply our customized experience sampling method to fully exploit potentially good samples. Experiments using real DL workloads show that DARL outperforms the representative Bulk Synchronous Parallel (BSP) scheme by 57.8% and Stale Synchronous Parallel (SSP) by 50.3% in terms of per-iteration time in heterogeneous environment.

Patient’s understanding on forthcoming dental surgeries is required by patient-centered care and helps reduce anxiety. Due to the complexity of dental surgeries and the patient-dentist expertise gap, conventional techniques of patient education are usually not effective for explaining surgical steps. In this paper, we present OralViewer—the first interactive application that enables dentist’s demonstration of dental surgeries in 3D to promote patients’ understanding. OralViewer takes a single 2D panoramic dental X-ray to reconstruct patient-specific 3D teeth structures, which are then assembled with registered gum and jaw bone models for complete oral cavity modeling. During the demonstration, OralViewer enables dentists to show surgery steps with virtual dental instruments that can animate effects on a 3D model in real-time. A technical evaluation shows that our deep learning model achieves a mean Intersection over Union (IoU) of 0.771 for 3D teeth reconstruction. A patient study with 12 participants shows OralViewer can improve patients’ understanding of surgeries. A preliminary expert study with 3 board-certified dentists further verifies the clinical validity of our system.

Dental forensic identification targets to identify persons with dental traces.The task is vital for the investigation of criminal scenes and mass disasters because of the resistance of dental structures and the wide-existence of dental imaging. However, no widely accepted automated solution is available for this labour-costly task. In this work, we pioneer to study deep learning for dental forensic identification based on panoramic radiographs. We construct a comprehensive benchmark with various dental variations that can adequately reflect the difficulties of the task. By considering the task's unique challenges, we propose FoID, a deep learning method featured by: (\textit{i}) clinical-inspired attention localization, (\textit{ii}) domain-specific augmentations that enable instance discriminative learning, and (\textit{iii}) transformer-based self-attention mechanism that dynamically reasons the relative importance of attentions. We show that FoID can outperform traditional approaches by at least \textbf{22.98\%} in terms of Rank-1 accuracy, and outperform strong CNN baselines by at least \textbf{10.50\%} in terms of mean Average Precision (mAP). Moreover, extensive ablation studies verify the effectiveness of each building blocks of FoID. Our work can be a first step towards the automated system for forensic identification among large-scale multi-site databases. Also, the proposed techniques, \textit{e.g.}, self-attention mechanism, can also be meaningful for other identification tasks, \textit{e.g.}, pedestrian re-identification.Related data and codes can be found at \href{https://github.com/liangyuandg/FoID}{https://github.com/liangyuandg/FoID}.

With the growing amount of data, the demand of big data storage significantly increases. Through the cloud center, data providers can conveniently share data stored in the center with others. However, one practically important problem in big data storage is privacy. During the sharing process, data is encrypted to be confidential and anonymous. Such operation can protect privacy from being leaked out. To satisfy the practical conditions, data tranmission with multi receivers is also considered. Furthermore, this paper proposes the notion of pre-authentication for the first time, i.e., only users with certain attributes that have already been authenticated can participate in the data transmission. The pre-authentication mechanism combines the advantages of proxy conditional re-encryption multi-sharing mechanism with the attribute-based authentication technique, thus achieving attributes authentication before re-encryption, and ensuring the security of the attributes and data. Finally this paper proves that the system can resist several attacks and the proposed pre-authentication mechanism could significantly enhance the system security level.

The parameter server architecture has shown promising performance advantages when handling deep learning (DL) applications. One crucial issue in this regard is the presence of stragglers, which significantly retards DL training progress. Previous solutions for solving stragglers may not fully exploit the computation resource of the cluster as evidenced by our experiments, especially in the heterogeneous environment. This motivates us to design a heterogeneity-aware parameter server paradigm that addresses stragglers and accelerates DL training from the perspective of computation parallelism. We introduce a novel methodology named straggler projection to give a comprehensive inspection of stragglers and reveal practical guidelines to solve this problem in two aspects: (1) controlling each worker's training speed via elastic training parallelism control and (2) transferring blocked tasks from stragglers to pioneers to fully utilize the computation resource. Following these guidelines, we propose the abstraction of parallelism as an infrastructure and design the Elastic-Parallelism Synchronous Parallel (EPSP) algorithm to handle distributed training and parameter synchronization, supporting both enforcedand slack-synchronization schemes. The whole idea has been implemented into a prototype called Falcon which effectively accelerates the DL training speed with the presence of stragglers. Evaluation under various benchmarks with baseline comparison demonstrates the superiority of our system. Specifically, Falcon reduces the training convergence time, by up to 61.83, 55.19, 38.92, and 23.68 percent shorter than FlexRR, Sync-opt, ConSGD, and DynSGD, respectively.

In the transportation industry, task offloading services of edge-enabled Internet of Vehicles (IoV) are expected to provide vehicles with the better Quality of Experience (QoE). However, the various status of diverse edge servers and vehicles, as well as varying vehicular offloading modes, make a challenge of task offloading service. Therefore, to enhance the satisfaction of QoE, we first introduce a novel QoE model. Specifically, the emerging QoE model restricted by the energy consumption: 1) intelligent vehicles equipped with caching spaces and computing units may work as carriers; 2) various computational and caching capacities of edge servers can empower the offloading; and 3) unpredictable routings of the vehicles and edge servers can lead to diverse information transmission. We then propose an improved deep reinforcement learning (DRL) algorithm named PS-DDPG with the prioritized experience replay (PER) and the stochastic weight averaging (SWA) mechanisms based on deep deterministic policy gradients (DDPG) to seek an optimal offloading mode, saving energy consumption. Specifically, the PER scheme is proposed to enhance the availability of the experience replay buffer, thus accelerating the training. Moreover, reducing the noise in the training process and thus stabilizing the rewards, the SWA scheme is introduced to average weights. Extensive experiments certify the better performance, i.e., stability and convergence, of our PS-DDPG algorithm compared to existing work. Moreover, the experiments indicate that the QoE value can be improved by the proposed algorithm.

The parameter server (PS) paradigm has achieved great success in deploying large-scale distributed Deep Learning (DL) systems. However, these systems implicitly assume that the cluster is homogeneous and this assumption does not hold in many realworld cases. Although the previous efforts are paid to address heterogeneity, they mainly prioritize the contribution of fast workers and reduce the involvement of slow workers, resulting in the limitations of workload imbalance and computation inefficiency. We reveal that grouping workers into communities, an abstraction proposed by us, and handling parameter synchronization at the community level can conquer these limitations and accelerate the training convergence progress. The inspiration of community comes from our exploration of prior knowledge about the similarity between workers, which is often neglected by previous work. These observations motivate us to propose a new synchronization mechanism named Community-aware Synchronous Parallel (CASP), which uses the Asynchronous Advantage Actor-Critic (A3C)-based algorithm to intelligently determine community configuration and fully improve the synchronization performance. The whole idea has been implemented in a prototype system called Petrel that achieves a good balance between convergence efficiency and communication overhead. The evaluation under various benchmarks with multiple metrics and baseline comparison demonstrates the effectiveness of Petrel. Specifically, Petrel accelerates the training convergence speed by up to 1.87 x faster and reduces communication traffic by up to 26.85 percent, on average, over the non-community synchronization mechanisms.

The multi-interface networks are efficient infrastructures to deploy distributed Deep Learning (DL) tasks as the model gradients generated by each worker can be exchanged to others via different links in parallel. Although this decentralized parameter synchronization mechanism can reduce the time of gradient exchange, building a high-performance distributed DL architecture still requires the balance of communication efficiency and computational utilization, i.e., addressing the issues of traffic burst, data consistency, and programming convenience. To achieve this goal, we intend to asynchronously exchange gradient pieces without the central control in multi-interface networks. We propose the Piece-level Gradient Exchange and Multi-interface Collective Communication to handle parameter synchronization and traffic transmission, respectively. Specifically, we design the gradient sketch approach based on 8-bit uniform quantization to compress gradient tensors and introduce the colayerabstraction to better handle gradient partition, exchange and pipelining. Also, we provide general programming interfaces to capture the synchronization semantics and build the Gradient Exchange Index (GEI) data structures to make our approach online applicable. We implement our algorithms into a prototype system called Canary by using PyTorch-1.4.0. Experiments conducted in Alibaba Cloud demonstrate that Canary reduces 56.28 percent traffic on average and completes the training by up to 1.61x, 2.28x, and 2.84x faster than BML, Ako on PyTorch, and PS on TensorFlow, respectively.

Convolutional networks (ConvNets) have achieved promising accuracy for various anatomical segmentation tasks. Despite the success, these methods can be sensitive to appearance variations that unforeseen from the training distributions. Considering the large variability of scans caused by artifacts, pathologies, and scanning setups, the robustness of ConvNets poses as a major challenge for their clinical applications, yet has not been much explored. In this paper, we propose to mitigate the challenge by enabling ConvNets’ awareness of the underlying anatomical invariances among imaging scans. Specifically, we introduce a fully convolutional Constraint Adoption Module (CAM) that incorporates probabilistic atlas priors as explicit constraints for predictions over a locally connected Conditional Random Field (CFR), which effectively reinforces the anatomical consistency of the labeling outputs. We design the CAM to be flexible for boosting various ConvNet, and compact for co-optimizing with ConvNets for fusion parameters that leads to the optimal performance. We show the advantage of such atlas priors fusion is two-fold with two brain parcellation tasks. First, our models achieve state-of-the-art accuracy among ConvNet-based methods on both datasets, by significantly reducing structural abnormalities of predictions. Second, we can largely boost the robustness of existing ConvNets, proved by: (i) testing on scans with synthetic pathologies, and (ii) training and evaluation on scans of different scanning setups across datasets. Our method is proposing to be easily adopted to existing ConvNets by fine-tuning with CAM plugged in for accuracy and robustness boosts.

Due to a lack of medical resources or oral health awareness, oral diseases are often left unexamined and untreated, affecting a large population worldwide. With the advent of low-cost, sensor-equipped smartphones, mobile apps offer a promising possibility for promoting oral health. However, to the best of our knowledge, no mobile health (mHealth) solutions can directly support a user to self-examine their oral health condition. This paper presents OralCam, the first interactive app that enables end-users' self-examination of five common oral conditions (diseases or early disease signals) by taking smartphone photos of one's oral cavity. OralCam allows a user to annotate additional information (e.g. living habits, pain, and bleeding) to augment the input image, and presents the output hierarchically, probabilistically and with visual explanations to help a laymen user understand examination results. Developed on our in-house dataset that consists of 3,182 oral photos annotated by dental experts, our deep learning based framework achieved an average detection sensitivity of 0.787 over five conditions with high localization accuracy. In a week-long in-the-wild user study (N=18), most participants had no trouble using OralCam and interpreting the examination results. Two expert interviews further validate the feasibility of OralCam for promoting users' awareness of oral health.

Low precision data representation is important to reduce storage size and memory access for convolutional neural networks (CNNs). Yet, existing methods have two major limitations: (1) requiring re-training to maintain accuracy for deep CNNs, and (2) needing 16-bit floating point or 8-bit fixed point for a good accuracy.

Lightweight convolutional neural networks (LW-CNNs) such as MobileNet, ShuffleNet, SqueezeNet, etc., have emerged in the past few years for fast inference on embedded and mobile system. However, lightweight operations limit acceleration potential by GPU due to their memory bounded nature and their parallel mechanisms that are not friendly to SIMD. This calls for more specific accelerators. In this paper, we propose an FPGA-based overlay processor with a corresponding compilation flow for general LW-CNN accelerations, called Light-OPU. Software-hardware co-designed Light-OPU reformulates and decomposes lightweight operations for efficient acceleration. Moreover, our instruction architecture considers sharing of major computation engine between LW operations and conventional convolution operations. This improves the run-time resource efficiency and overall power efficiency. Finally, Light-OPU is software programmable, since loading of compiled codes and kernel weights completes switch of targeted network without FPGA reconfiguration. Our experiments on seven major LW-CNNs show that Light-OPU achieves 5.5x better latency and 3.0x higher power efficiency on average compared with edge GPU NVIDIA Jetson TX2. Furthermore, Light-OPU has 1.3x to 8.4x better power efficiency compared with previous customized FPGA accelerators. To the best of our knowledge, Light-OPU is the first in-depth study on FPGA-based general processor for LW-CNNs acceleration with high performance and power efficiency, which is evaluated using all major LW-CNNs including the newly released MobileNetV3.

In the transportation industry, task offloading services of edge intelligent Internet of Vehicles (IoV) are expected to provide vehicles with the better Quality of Experience (QoE). However, the various status of diverse edge servers and vehicles, as well as varying vehicular offloading modes, make a challenge of task offloading service. Therefore, to enhance the satisfaction of QoE, we first introduce a novel QoE model. Specifically, the emerging QoE model restricted by the energy consumption, (1) intelligent vehicles equipped with caching spaces and computing units may work as carriers; (2) various computational and caching capacities of edge servers can empower the offloading; (3) unpredictable routings of the vehicles and edge servers can lead to diverse information transmission. We then propose an improved deep reinforcement learning (DRL) algorithm named RA-DDPG with the prioritized experience replay (PER) and the stochastic weight averaging (SWA) mechanisms based on deep deterministic policy gradients (DDPG) to seek an optimal offloading mode, saving energy consumption. Extensive experiments certify the better performance, i.e., stability and convergence, of our RA-DDPG algorithm compared to existing work. Moreover, the experiments indicate that the QoE value can be improved by the proposed algorithm.

Recently, deep learning (DL) becomes increasingly important since its transformative effect on a wide range of applications. During inference process, the DL model is deployed on the cloud to answer online queries. One crucial issue in the progress of DL inference is energy consumption, which significantly retards computation performance. Therefore, many previous investigations decrease the energy consumption via computation reuse technique based on similarity. However, if input data consists individually from mobile devices, applying these schemes will significantly decline computation performance. Because in disordered individual inputs, similarity for reuse is difficult to exploit directly. Results of initial experimental observations show that (1) individual input data also has high similarity for reuse, and (2) the total similarity during computation process has a relation with the characteristics of input data. This motivates us to design a reordering scheme to enhance similarity for computation reuse. Our main approaches are using statistical theory to predict the similarities among input data, and determining the execution sequence. Based on these approaches, we propose an effective input reordering scheme for computation reuse to save energy consumption. The evaluation under various benchmarks demonstrates that the reordering scheme significantly outperforms the previous schemes, for instance, the computation reuse is enhanced to $1.1 \times$ and the energy consumption is minimized to 40% according to the configuration of traditional computation reuse technique.

As to address the impact of heterogeneity in distributed Deep Learning (DL) systems, most previous approaches focus on prioritizing the contribution of fast workers and reducing the involvement of slow workers, incurring the limitations of workload imbalance and computation inefficiency. We reveal that grouping workers into communities, an abstraction proposed by us, and handling parameter synchronization in community level can conquer these limitations and accelerate the training convergence progress. The inspiration of community comes from our exploration of prior knowledge about the similarity between workers, which is often neglected by previous work. These observations motivate us to propose a new synchronization mechanism named Community-aware Synchronous Parallel (CSP), which uses the Asynchronous Advantage Actor-Critic (A3C), a Reinforcement Learning (RL) based algorithm, to intelligently determine community configuration and fully improve the synchronization performance. The whole idea has been implemented in a system called Petrel that achieves a good balance between convergence efficiency and communication overhead. The evaluation under different benchmarks demonstrates our approach can effectively accelerate the training convergence speed and reduce synchro-nization traffic.

Drug effectiveness management is a complicated and challenging task in chronic diseases, like Parkinson's Disease (PD). Drug effectiveness control is not only linked to personal out-of-pocket cost but also affecting the quality of life among patients with chronic symptoms. In the current practice, although that health and medical professionals still play a key role in the personalized treatment plan, the critical decision on drug selection falls upon the individual report when patients call in or visit the clinics. Unfortunately, most of the patients with chronic diseases either fail to report their day-to-day symptoms or have a limited access to medical resources due to economic constraints. In this paper, we present PDLens, a first smartphone-based system to detect drug effectiveness among Parkinson's in daily life. Specifically, PDLens can extract digital behavioral markers related to PD drug responses from everyday activities, including phone calls, standing, and walking. PDLens models the PD symptom severity on drug treatment and detects the change of severity scores before and after drug intake. A ranking-based multi-view deep neural network is developed to decide the drug effectiveness upon the symptom severity changes. To validate the performance of PDLens, we conduct a pilot study with 81 PD patients and monitor their smartphone activities and severity changes over 33693 drug intake events across six (6) months. Compared with the standard clinical drug effectiveness test developed by Motor Disorder Society, results reveal that PDLens is a promising tool to facilitate drug effectiveness detection among PD patients in their daily lives.

The advent of smart devices has caused unprecedented security and privacy concerns to its users. Although the fingerprint technology is a go-to biometric solution in high-impact applications (e.g., smart-phone security, monetary transactions and international-border verification), the existing fingerprint scanners are vulnerable to spoofing attacks via fake-finger and cannot be employed across smart devices (e.g., wearables) due to hardware constraints. We propose SonicPrint that extends fingerprint identification beyond smartphones to any smart device without the need for traditional fingerprint scanners. SonicPrint builds on the fingerprint-induced sonic effect (FiSe) caused by a user swiping his fingertip on smart devices and the resulting property, i.e., different users' fingerprint would result in distinct FiSe. As the first exploratory study, extensive experiments verify the above property with 31 participants over four different swipe actions on five different types of smart devices with even partial fingerprints. SonicPrint achieves up to a 98% identification accuracy on smartphone and an equal-error-rate (EER) less than 3% for smartwatch and headphones. We also examine and demonstrate the resilience of SonicPrint against fingerprint phantoms and replay attacks. A key advantage of SonicPrint is that it leverages the already existing microphones in smart devices, requiring no hardware modifications. Compared with other biometrics including physiological patterns and passive sensing, SonicPrint is a low-cost, privacy-oriented and secure approach to identify users across smart devices of unique form-factors.

With the continuing growth of voice-controlled devices, voice metrics have been widely used for user identification. However, voice biometrics is vulnerable to replay attacks and ambient noise. We identify that the fundamental vulnerability in voice biometrics is rooted in its indirect sensing modality (e.g., microphone). In this paper, we present VocalPrint, a resilient mmWave interrogation system which directly captures and analyzes the vocal vibrations for user authentication. Specifically, VocalPrint exploits the unique disturbance of the skin-reflect radio frequency (RF) signals around the near-throat region of the user, caused by the vocal vibrations during communication. The complex ambient noise is isolated from the RF signal using a novel resilience-aware clutter suppression approach for preserving fine-grained vocal biometric properties. Afterward, we extract the text-independent vocal tract and vocal source features and input them to an ensemble classifier for user authentication. VocalPrint is practical as it leverages a low-cost, portable, and energy-efficient hardware allowing effortless transition to a smartphone while having sufficient usability as typical voice authentication systems due to its non-contact nature. Our experimental results from 41 participants with different interrogation distances, orientations, and body motions show that VocalPrint can achieve over 96% authentication accuracy even under unfavorable conditions. We demonstrate the resilience of our system against complex noise interference and spoof attacks of various threat levels.

With the widespread applications of the Internet of Things (IoT), e.g., smart city, business, healthcare, etc., the security of data and devices becomes a major concern. Although blockchain can effectively enhance the network security and achieve fault tolerance, the huge resource consumption and limited performance of data processing restrict its deployments in IoT scenarios. Observing the heterogeneity and resource constraints, we intend to make blockchain accommodate both wimpy and brawny IoT devices. In this article, we present Tornado, a high-performance blockchain system based on space-structured ledger and corresponding algorithms, to enable blockchain in IoT. Specifically, we first design a space-structured chain architecture with novel data structures for promoting the network scalability. To address the huge heterogeneity of IoT, a novel consensus mechanism named collaborative-proof of work is developed. Moreover, we propose the space-structured greedy heaviest-observed subtree (S2GHOST) protocol for improving the resource efficiency of IoT devices. Additionally, a dynamic weight assignment mechanism in S2GHOST contributes to reflect the trustworthiness of data and devices. Extensive experiments demonstrate that Tornado can achieve a maximum throughput of 3464.76 transactions per second. The optimizations of propagation latency and resource efficiency are 68.14% and 30.56%, respectively.

In edge-enabled Internet of Things (IoT), computation offloading service is expected to offer users with better Quality of Experience (QoE) than traditional IoT. Unfortunately, the growing multiple tasks from users are occuring with the emergence of the IoT environment. Meanwhile, the current computation offloading with QoE is solved by deep reinforcement learning (DRL) with the issue of instability and slow convergence. Therefore, improving the QoE in edge-enabled IoT is still the ultimate challenge. In this article, to enhance the QoE, we propose a new QoE model to study the computation offloading. Specifically, the emerged QoE model can capture three influential elements: 1) service latency determined by local computing latency and transmission latency; 2) energy consumption according to local calculation and transmission consumption; and 3) task success rate based on the coding error probability. Moreover, we improve the deep deterministic policy gradients (DDPG) algorithm and propose a algorithm named the double-dueling-deterministic policy gradients (D3PG) based on the proposed model. Specifically, the actor network highly relies on the critic network, which makes the performance of the DDPG sensitive to the critic and thus leads to poor stability and slow convergence in the computation offloading process. To solve this, we redesign the critic network by using Double Q -learning and Dueling networks. Extensive experiments verify the better stability and faster convergence of our proposed algorithm than existing methods. In addition, experiments also indicate that our proposed algorithm can improve the QoE performance.

With the popularity of smart devices and the widespread use of machine learning methods, smart edges have become the mainstream of dealing with wireless big data. When smart edges use machine learning models to analyze wireless big data, nevertheless, some models may unintentionally store a small portion of the training data with sensitive records. Thus, intruders can expose sensitive information by careful analysis of this model. To solve this privacy issue, in this paper, we propose and implement a machine learning strategy for smart edges using differential privacy. We focus our attention on privacy protection in training datasets in wireless big data scenario. Moreover, we guarantee privacy protection by adding Laplace mechanisms, and design two different algorithms Output Perturbation (OPP) and Objective Perturbation (OJP), which satisfy differential privacy. In addition, we consider the privacy preserving issues presented in the existing literatures for differential privacy in the correlated datasets, and further provided differential privacy preserving methods for correlated datasets, guaranteeing privacy by theoretical deduction. Finally, we implement the experiments on the TensorFlow, and evaluate our strategy on four datasets, i.e., MNIST, SVHN, CIFAR-10 and STL-10. The experiment results show that our methods can efficiently protect the privacy of training datasets and guarantee the accuracy on benchmark datasets.

A modern Network Function Virtualization (NFV) service is usually expressed in a service chain that contains a list of ordered network functions, each can run in one or multiple virtual machines. Although lots of efforts have been devoted to service chain deployment, the researchers normally consider a simple model of network functions where different service chains have their own network functions no matter whether some of the network function appliances are interdependent. In this paper, we study the service chain deployment by exploiting two types of correlations between network functions: the Coordination Effect due to information exchanges among multiple VMs running the same network function, and the Traffic-Change Effect where the volume of outgoing traffic is not necessarily equal to the volume of its incoming traffic at each network function because of packet manipulations such as compression and encryption. These two effects have not been studied simultaneously in the context of service chaining. With theobjective to maximize the profit measured by the admitted traffic minus the implementation cost, we first formulate a joint service-function deployment and traffic scheduling (SUPER) problem that is proved to be NP-hard. We then devise an approximation algorithm based on the Markov approximation technique and analyze its theoretical bound on the convergence time. Simulation results show that the proposed algorithm outperforms two existing benchmark algorithms significantly.

Leveraging high-performance software-defined networks (SDNs) to manage industrial Internet of Things (IIoT) devices has become a promising trend; the SDN is expected to be the next generation as a unified and virtualized network platform that provides unprecedented automation, flexibility, and efficiency. As the core of business applications and sensitive data storage, the SDN is vulnerable to distributed denial-of-service (DDoS) attacks in IIoT environment that numerous requests are sent to the SDN to interrupt its services. In the traditional defense systems, honeypots have shown great promises in resisting DDoS attacks. In this paper, we reveal a new attack that can identify honeypots to invalidate their protection. In addition, we analyze the optimal strategies of attackers, so that they can find the best time to carry on attacks. To protect SDN from such a kind of anti-honeypot attacks, we propose a pseudo-honeypot game (PHG) strategy with theoretical performance guarantee. We prove several groups of Bayesian-Nash Equilibrium in the PHG strategy. Moreover, we show that these strategies can achieve the optimal equilibrium between legitimate users and attackers. The proposed honeypot strategies can provide dynamic protection for SDN. Hence, malicious attacks under our strategies can be effectively controlled. Finally, we evaluate our proposals on a testbed, and experimental results show that our proposals can effectively resist DDoS attacks with lower energy consumption compared with the existing methods.

With the advent of 5G, the industrial Internet of Things has developed rapidly. The industrial sensor-cloud system (SCS) has also received widespread attention. In the future, a large number of integrated sensors that simultaneously collect multifeature data will be added to industrial SCS. However, the collected big data are not trustworthy due to the harsh environment of the sensor. If the data collected at the bottom networks are directly uploaded to the cloud for processing, the query and data mining results will be inaccurate, which will seriously affect the judgment and feedback of the cloud. The traditional method of relying on sensor nodes for data cleaning is insufficient to deal with big data, whereas edge computing provides a good solution. In this article, a new data cleaning method is proposed based on the mobile edge node during data collection. An angle-based outlier detection method is applied at the edge node to obtain the training data of the cleaning model, which is then established through support vector machine. Besides, online learning is adopted for model optimization. Experimental results show that multidimensional data cleaning based on mobile edge nodes improves the efficiency of data cleaning while maintaining data reliability and integrity, and greatly reduces the bandwidth and energy consumption of the industrial SCS.

Satellite-based communication technology has gained much attention in the past few years, where satellites play mainly the supplementary roles as relay devices to terrestrial communication networks. Unlike previous work, we treat the low-earth-orbit (LEO) satellites as secure data storage mediums. We focus on data acquisition from a LEO satellite based data storage system (also referred to as the LEO based datacenters), which has been considered as a promising and secure paradigm on data storage. Under the LEO based datacenter architecture, one fundamental challenge is to deal with energy-efficient downloading from space to ground while maintaining the system stability. In this paper, we aim to maximize the amount of data admitted while minimizing the energy consumption, when downloading files from LEO based datacenters to meet user demands. To this end, we first formulate a novel optimization problem and develop an online scheduling framework. We then devise a novel coflow-like “Join the first K-shortest Queues (JKQ)” based job-dispatch strategy, which can significantly lower backlogs of queues residing in LEO satellites, thereby improving the system stability. We also analyze the optimality of the proposed approach and system stability. We finally evaluate the performance of the proposed algorithm through conducting emulator based simulations, based on real-world LEO constellation and user demand traces. The simulation results show that the proposed algorithm can dramatically lower the queue backlogs and achieve high energy efficiency.

Existing works adopt the Edge-Oriented Resource Allocation (EORA) scheme, in which edge nodes cache services and schedule user requests to distribute workloads over cloud and edge nodes, so as to achieve high-quality services and low latency. Unfortunately, EORA does not fully take into account the fact that service providers are sometimes independent from the edge operators with their own objectives. To deal with the conflict and cooperation between service providers and edge nodes, we devise a service-oriented resource allocation (SORA) scheme, where edge nodes and service providers adjust their resource allocations to provide requested services. We first prove that such resource allocation problem is NP-hard. We then propose a three-sided cyclic game (3CG) involving users, edge nodes, and service providers who make their individual decisions by choosing respectively high-quality services, high-value users, and cost-effective edge nodes for service deployment. Based on 3CG, we prove the existence and approximation ratio of pure-strategy Nash equilibriums (NEs). We also develop both centralized and distributed approximate algorithms for resource allocation. Finally, extensive experimental results validate the effectiveness and convergence of the proposed algorithms.

Although current proposed compression schemes achieve better performance than traditional data compression schemes, they have not fully exploited the spatial and temporal correlations among the data, and the design of the projection (measurement) matrix cannot satisfy the requirement of real scenarios adaptively. Hence, well-designed clustering algorithm is needed to further explore strong spatial correlation, and an adaptive measurement matrix is also needed to ensure exact data recovery. In this paper, we propose a fog-based optimized Kronecker-supported compression scheme to address the above shortcomings and achieve better compression results in the industrial Internet of Things (IIoT). Our scheme first leverages a k-means-based clustering algorithm that explores the spatial correlation among sensory data, which can obtain better compression effects with less communication overhead. It then develops a novel Kronecker-supported two-dimensional data compression mechanism at the fog node, which can ensure the recovery of the original data from the compressed data with high precision; this mechanism can also reduce the communication overhead between fog and cloud nodes significantly. Next, a Kronecker concatenated measurement matrix optimization problem is formulated for meeting the requirement of real scenarios adaptively, and an efficient solution algorithm is developed to obtain the optimal value and ensure that the stringent precision requirements of industrial applications are satisfied. Finally, simulation results show that our proposed scheme is energy efficient and can achieve better clustering results and recovery performance for sensory data, for example, the energy consumption is reduced by 6.8 percent after clustering operation, and the relative reconstruction error of temperature data is improved by an average of 15.8 percent with the same energy saving effect.

The property of performing data processing near the source of data (i.e., at the edge of the network) enables fog computing that can effectively reduce computation latency, bandwidth and energy consumption, especially for big data network scenarios. For the sake of achieving efficient and secure big sensory data collection in fog-assisted Internet of Things (IoT), this paper proposes an efficient privacy preserving data collection and computation offloading scheme. In the proposed scheme, first, the designed layer-aware fog computing architecture provides effective support for efficient and secure data collection and fog computation offloading. Then the proposed sampling perturbation encryption method protects data privacy against eavesdroppers and active attackers without sacrificing data correlation, and it also facilitates the simultaneous execution of decrypting and decompressing operations on encrypted sampling data. Furthermore, the developed data processing method at fog nodes reduces the amount of redundant data transmissions significantly, and the formulated optimization model for the measurement matrix ensures the high precision of data reconstruction at the end user. Particularly, a completion time minimization problem is formulated for fog computation offloading, and an efficient offloading decision algorithm is developed to find the minimum completion time by determining the optimal offloading proportion with joint optimal allocation of local CPU, external CPU and channel bandwidth resources. Finally, the illustrative results reveal that the proposed scheme is an efficient data collection and computation offloading scheme with a strong privacy preservation property. For example, when the temporal compression ratio is 0.5, the redundant data can be reduced by 65 percent at fog node with a low relative recovery error 0.0139. At the same time when the task size is 9 Mb, the completion time of compression computation task at fog node can be reduced by 14.6 percent compared with other computation offloading method.

Field-programmable gate array (FPGA) provides rich parallel computing resources with high energy efficiency, making it ideal for deep convolutional neural network (CNN) acceleration. In recent years, automatic compilers have been developed to generate network-specific FPGA accelerators. However, with more cascading deep CNN algorithms adapted by various complicated tasks, reconfiguration of FPGA devices during runtime becomes unavoidable when network-specific accelerators are employed. Such reconfiguration can be difficult for edge devices. Moreover, network-specific accelerator means regeneration of RTL code and physical implementation whenever the network is updated. This is not easy for CNN end users. In this article, we propose a domain-specific FPGA overlay processor, named OPU to accelerate CNN networks. It offers software-like programmability for CNN end users, as CNN algorithms are automatically compiled into executable codes, which are loaded and executed by OPU without reconfiguration of FPGA for switch or update of CNN networks. Our OPU instructions have complicated functions with variable runtimes but a uniform length. The granularity of instruction is optimized to provide good performance and sufficient flexibility, while reducing complexity to develop microarchitecture and compiler. Experiments show that OPU can achieve an average of 91% runtime multiplication and accumulation unit (MAC) efficiency (RME) among nine different networks. Moreover, for VGG and YOLO networks, OPU outperforms automatically compiled network-specific accelerators in the literature. In addition, OPU shows 5.35× better power efficiency compared with Titan Xp. For a real-time cascaded CNN networks scenario, OPU is 2.9× faster compared with edge computing GPU Jetson Tx2, which has a similar amount of computing resources.

In this article, we design the first full software/ hardware stack, called Uni-OPU, for an efficient uniform hardware acceleration of different types of transposed convolutional (TCONV) networks and conventional convolutional (CONV) networks. Specifically, a software compiler is provided to transform the computation of various TCONV, i.e., zero-inserting-based TCONV (zero-TCONV), nearest-neighbor resizing-based TCONV (NN-TCONV), and CONV layers into the same pattern. The compiler conducts the following optimizations: 1) eliminating up to 98.4% of operations in TCONV by making use of the fixed pattern of TCONV upsampling; 2) decomposing and reformulating TCONV and CONV into streaming parallel vector multiplication with a uniform address generation scheme and data flow pattern; and 3) efficient scheduling and instruction compilation to map networks onto a hardware processor. An instruction-based hardware acceleration processor is developed to efficiently speedup our uniform computation pattern with throughput up to 2.35 TOPS for the TCONV layer, consuming only 2.89 W dynamic power. We evaluate Uni-OPU on a benchmark set composed of six TCONV networks from different application fields. Extensive experimental results indicate that Uni-OPU is able to gain 1.45× to 3.68× superior power efficiency compared with state-of-the-art zero-TCONV accelerators. High acceleration performance is also achieved on NN-TCONV networks, the acceleration of which have not been explored before. In summary, we observe 1.90× and 1.63× latency reduction, as well as 15.04× and 12.43× higher power efficiency on zero-TCONV and NN-TCONV networks compared with Titan Xp GPU on average. To the best of our knowledge, ours is the first in-depth study to completely unify the computation process of zero-TCONV, NN-TCONV, and CONV layers.

The location privacy issue has become a critical research topic recently. The existing solutions do not solve one typical problem in practice: people may only want to protect certain privacy-sensitive locations among a group of temporal and spatial correlated points in a trajectory. As an effort towards this issue, we analyze the impact of space-time relationship on location privacy preservation. In addition, we propose new privacy definitions to better evaluate the privacy level and prove that the target location's privacy can be enhanced by randomizing its time and space related points. Moreover, under the constraint of the total noise power, the problem of obfuscating a location in a temporal and spatial correlated trajectory is formulated as finding the best noise allocation vector which can achieve the highest privacy level. This problem is solved by our proposed location privacy preserving method which applies differential privacy scheme on a series of points with noise budget allocation. Lastly, the performance of the proposed scheme is evaluated by simulations.

Parameter Server (PS) has been widely used to train a large amount of data on multiple machines in parallel. In parameter server, a critical problem is how to effectively schedule multiple training jobs to minimize the job completion time. Some existing work has proposed methods of setting the number of concurrent workers. However, they do not effectively consider the topology of GPU placement which affects the efficiency of communication. This paper proposes a novel resource-to-time model based on the number of workers and the topology of GPU placement. According to the model, we propose an algorithm called TOPO-PS particularly for topology problem in parameter servers. The algorithm achieves the placement strategy based on graph mapping algorithm. Evaluation under various algorithms evidences the superiority of our algorithm. TOPO-PS yields shorter job completion, by up to 53.48% of that of FIFO and 88.77% of OASIS.

Fog computing emerges as a promising mode to meet the stringent requirement of low latency in industrial Internet of Things (IIoT). By offloading partial computation-intensive tasks from fog node to cloud server, the computation experience of users can be further improved in fog computing system. In this paper, we develop an energy-efficient computation offloading scheme for IIoT in fog computing scenario. The purpose is to minimize energy consumption when computation tasks are accomplished within a desired energy overhead and delay. It has a comprehensive consideration on the components of energy consumption at fog node, which includes the energy consumption of local computing, transmitting and waiting states. To address this energy minimization problem, an accelerated gradient algorithm is proposed, it can find the optimal offloading ratio with a fast speed that improves the convergence speed of traditional method. Finally, the numerical results reveal that the proposed offloading scheme is superior to the local computing and full offloading schemes in terms of energy consumption and completion time, and further confirm the advantage of convergence rate.

Predicting service demand of users based on the historical network traffic data in a large area has been of great importance towards better service management for geo-distributed systems, such as edge computing. Existing works relying on complete information of historical service demands cannot deal with real-world scenarios that a significant portion of historical data is not available because collecting such data comprehensively is either costly or impossible. Motivated by the challenge of data incompleteness for the demand prediction, in this paper, we propose a deep neural network model based on the encoder-decoder architecture consisting of an encoder, a converter, and a decoder. This model successfully extracts global features from incomplete historical data, predicts the future information in the feature space, and finally generates complete future demands of the whole area from future features. We devise an encoder with mixed 3D and 2D convolutional layers such that rich temporal and spatial features of service demands can still be captured even when historical data are partially missing. We embed the conditional generative adversarial networks (GANs) into our decoder that generates real demand distribution with magnified quality. Another major difference from the traditional encoder-decoder architecture is to establish a fine-grained association between the features of history and future by adding the converter in the middle of encoder and decoder. With the three components, our model can overcome the data incompleteness challenge and use the extracted global features to make an accurate prediction of service demands. We conduct experiments on a real-world dataset with demands of telecommunications services in an urban environment. The experimental results show that our model achieves much higher prediction accuracy than the state-of-the-art approaches when only incomplete historical data are available.

Managing edge resources is one of key issues in edge computing. Recent works of resource allocation in edge computing focus on service caching and request scheduling on edge nodes by distributing tasks over cloud and edge nodes, so as to achieve high-quality services and low latency. Unfortunately, most schemes do not pay enough attention on service providers which also have their own resources. To serve users, service providers cooperate with edge nodes and are sometimes independent of the edge operators with their own objectives. To deal with the cooperation and conflict among users, service providers and edge nodes, we propose a cyclic selection model to depict the resource allocation among users, edge nodes and service providers where they cooperate for completing user requests and compete for their own interest. Such resource allocation problem can be formulated as a non-linear integer programming which is very difficult to solve. Thus, we propose a three-sided cyclic game (3CG) involving users, edge nodes, and service providers who make their decisions: users select preferred services, service providers select cost-effective edge nodes, edge nodes select high-value users. 3CG is proved to have pure-strategy Nash equilibriums and an approximation ratio. We develop central and distributed approximate algorithms for resource allocation. The evaluation results of 3CG show the effectiveness and efficiency of the proposed algorithms.

Parameter server paradigm has shown great performance superiority for handling deep learning (DL) applications. One crucial issue in this regard is the presence of stragglers, which significantly retards DL training progress. Previous solutions for solving straggler may not fully exploit the computation capacity of a cluster as evidenced by our experiments. This motivates us to make an attempt at building a new parameter server architecture that mitigates and addresses stragglers in heterogeneous DL from the perspective of computation parallelism. We introduce a novel methodology named straggler projection to give a comprehensive inspection of stragglers and reveal practical guidelines for resolving this problem: (1) reducing straggler emergence frequency via elastic parallelism control and (2) transferring blocked tasks to pioneer workers for fully exploiting cluster computation capacity. Following the guidelines, we propose the abstraction of parallelism as an infrastructure and elaborate the Elastic-Parallelism Synchronous Parallel (EPSP) that supports both enforced-and slack-synchronization schemes. The whole idea has been implemented in a prototype called Falcon which efficiently accelerates the DL training progress with the presence of stragglers. Evaluation under various benchmarks with baseline comparison evidences the superiority of our system. Specifically, Falcon yields shorter convergence time, by up to 61.83%, 55.19%, 38.92% and 23.68% reduction over FlexRR, Sync-opt, ConSGD and DynSGD, respectively.

Voice-user interface (VUI) has become an integral component in modern personal devices (\textite.g., smartphones, voice assistant) by fundamentally evolving the information sharing between the user and device. Acoustic sensing for VUI is designed to sense all acoustic objects; however, the existing VUI mechanism can only offer low-quality speech sensing. This is due to the audible and inaudible interference from complex ambient noise that limits the performance of VUI by causing denial-of-service (DoS) of user requests. Therefore, it is of paramount importance to enable noise-resistant speech sensing in VUI for executing critical tasks with superior efficiency and precision in robust environments. To this end, we investigate the feasibility of employing radio-frequency signals, such as millimeter wave (mmWave) for sensing the noise-resistant voice of an individual. We first perform an in-depth study behind the rationale of voice generation and resulting vocal vibrations. From the obtained insights, we presentWaveEar, an end-to-end noise-resistant speech sensing system.WaveEar comprises a low-cost mmWave probe to localize the position of the speaker among multiple people and direct the mmWave signals towards the near-throat region of the speaker for sensing his/her vocal vibrations. The received signal, containing the speech information, is fed to our novel deep neural network for recovering the voice through exhaustive extraction. Our experimental evaluation under real-world scenarios with 21 participants shows the effectiveness ofWaveEar to precisely infer the noise-resistant voice and enable a pervasive VUI in modern electronic devices.

Inventory management is pivotal in the supply chain to supervise the non-capitalized products and stock items. Item counting, indexing and identification are the major jobs of inventory management. Currently, the most adopted inventory technologies in product counting/identification are using either the laser-scannable barcode or the radio-frequency identification (RFID). However, the laser-scannable barcode is entangled by an alignment issue (i.e., the laser reader must align with one barcode in line-of-sight), and the RFID is economically and environmentally unfriendly (i.e., high-cost and not naturally disposable). To this end, we propose FerroTag which is a paper-based mmWave-scannable tagging infrastructure for the next generation inventory management system, featuring ultra-low cost, environment-friendly, battery-free and in-situ (i.e., multiple tags can be simultaneously processed outside the line-of-sight). FerroTag is developed on top of the FerroRF effects. Specifically, the magnetic nanoparticles within the ferrofluidic ink reply to probing mmWave with classifiable features (i.e., the FerroRF response). By designating the ink pattern and hence the location of particles, the related FerroRF response can be modified. Thus, a specifically designated ferrofluidic ink printed pattern, which is associated with a unique FerroRF response, is a remotely retrievable (a.k.a., mmWave-scannable) identity. Furthermore, we augment FerroTag by designing a high capacity pattern system and a fine-grained identification protocol such that the capacity and robustness of FerroTag can be systematically improved in mass product management in inventory. Last but not least, we evaluate the performance of FerroTag with 201 different tag design patterns. Results show that FerroTag can identify tags with an accuracy of more than 99% in a controlled lab setup. Moreover, we examine the reliability, robustness and performance of FerroTag under various real-world circumstances, where FerroTag maintains the accuracy over 97%. Therefore, FerroTag is a promising tagging infrastructure for the applications in inventory management systems.

Localization plays a pivotal role in wireless sensor networks. Many range-based localization algorithms have been proposed for 2-D sensor networks or densely deployed 3-D sensor networks. However, range-based localization in sparse 3-D sensor networks is still a challenging problem, because the sparseness of the network makes it difficult to obtain a proper order of nodes to be sequentially localized. The patch-and-stitching localization strategy can conquer the sparseness problem in 2-D networks, but for 3-D networks it is still unknown how to uniquely merge two patches when there are not enough common nodes. In this paper, we solve this challenging problem by deriving the conditions under which two subnetworks can be uniquely merged. In the proposed approach, we treat the translation parameters as unknowns and form a set of equations with which the unknowns can be uniquely solved. The novelty of our algorithm also lies in that we exploit both common nodes and connecting edges among adjacent subnetworks to merge them, resulting in very high chances that two subnetworks can be merged. We conduct extensive simulation experiments to evaluate the performance of the proposed algorithm. The results show that the proposed algorithm could localize more than 90% of nodes in sparse 3-D networks with average node degree of 11 and anchor ratio of 5%, while the best existing solution can localize only 52% of nodes in the same situation.

As an innovated and revolutionized technology, blockchain has been applied in many fields, such as cryptocurrency, food traceability, identity management, or even market prediction. To discover its great potential, both industry and academia have paid great attention to it and numerous researches have been conducted. Based on the literature and industry whitepapers, in this survey, we unroll and structure the blockchain related discoveries and scientific results in many aspects. Particularly, we classify blockchain technologies into four layers and carry out a comprehensive study on the consensus strategies, the network, and the applications of blockchain. Different blockchain applications are put into the corresponding categories based on the fields, especially in Internet of Things (IoT). When introducing each layer, we not only organize and summarize the related works, but also discuss the fundamental issues and future research directions. We hope this survey could shed some light on the research of blockchain and serve as a guide for further studies.

Energy-saving (ES) systems developed on the basis of the Internet-of-Things (IoT) by heavily relying on automated understanding of human behaviors and activities recognition is of paramount importance in smart home. However, classic approaches are incapable to understand the relations among users' contexts and ES of appliances very well, and they cannot handle massive metering and time-varying user context datasets. Moreover, privacy concern is thoroughly aroused from both the residential and utility provider sides as to its essentiality. To tackle these problems, we propose a privacy-preserving and residential context-aware online ES (PRCOES) system in an IoT-enabled smart home environment. We model the repeated interaction of ES of appliances and the activity recognition of user context as a contextual multiarmed bandits (CMAB) problem, where the context-aware online learning algorithm can predict appropriate energy offers (EOs) that could meet the users' satisfaction, task completion rate, and ES purposes for appliances. We utilize a tree-based structure expanding from top to bottom to recommend EOs, which supports ever-increasing big metering datasets with user context-awareness. Theoretical analysis shows that our proposal achieves sublinear regret and differential privacy for both residents and utility provider. Experiments results validate that PRCOES could enhance users' experience and prolong users' engagement in everyday ES while guarantee the privacy for both residents and utility provider.

Electricity price forecasting is a significant part of smart grid because it makes smart grid cost efficient. Nevertheless, existing methods for price forecasting may be difficult to handle with huge price data in the grid, since the redundancy from feature selection cannot be averted and an integrated infrastructure is also lacked for coordinating the procedures in electricity price forecasting. To solve such a problem, a novel electricity price forecasting model is developed. Specifically, three modules are integrated in the proposed model. First, by merging of Random Forest (RF) and Relief-F algorithm, we propose a hybrid feature selector based on Grey Correlation Analysis (GCA) to eliminate the feature redundancy. Second, an integration of Kernel function and Principle Component Analysis (KPCA) is used in feature extraction process to realize the dimensionality reduction. Finally, to forecast price classification, we put forward a differential evolution (DE) based Support Vector Machine (SVM) classifier. Our proposed electricity price forecasting model is realized via these three parts. Numerical results show that our proposal has superior performance than other methods.

Big data analytics in datacenters often involve scheduling of data-parallel jobs. Traditional scheduling techniques based on improving network resource utilization are subject to limited bandwidth in datacenter networks. To alleviate the shortage of bandwidth, some cluster frameworks employ techniques of traffic compression to reduce transmission consumption. However, they tackle scheduling in a coarse-grained manner at task level and do not perform well in terms of flow-level metrics due to high complexity. Fortunately, the abstraction of coflow pioneers a new perspective to facilitate scheduling efficiency. In this paper, we introduce a coflow compression mechanism to minimize the completion time in data-intensive applications. Due to the NP-hardness, we propose a heuristic algorithm called Fastest-Volume-Disposal-First (FVDF) to solve this problem. For online applicability, FVDF supports stage pipelining to accelerate scheduling and exploits recurrent neural networks (RNNs) to predict compression speed. Meanwhile, we build Swallow, an efficient scheduling system that implements our proposed algorithms. It minimizes coflow completion time (CCT) while guaranteeing resource conservation and starvation freedom. The results of both trace-driven simulations and real experiments show the superiority of our algorithm, over existing one. Specifically, Swallow speeds up CCT and job completion time (JCT) by up to 1.47χ and 1.66χ on average, respectively, over the SEBF in Varys, one of the most efficient coflow scheduling algorithms so far. Moreover, with coflow compression, Swallow reduces data traffic by up to 48.41 percent on average.

On-chip thermal sensors are essential for temperature management in 3-D network-on-chip (NoC) systems. However, due to the physical (area and power) or economical constraints, the number of sensors is limited. Therefore, the two critical issues we face are: 1) how to figure out an efficient thermal sensor placement with the limited number of sensors and 2) how to reconstruct the entire thermal profile based on sensor observations. Another major issue for the thermal reconstruction is the sensor measurement accuracy. Thus, online accurate full-chip thermal reconstruction under Gaussian and non-Gaussian noises is another great challenge. In this paper, a greedy thermal sensor placement algorithm maximizing the rank of the observability Gramian is proposed. A good placement algorithm always relies on a specific reconstruction method. The proposed placement algorithm is designed for the state-space-based thermal model, thus the combination of the proposed placement algorithm and the Kalman filter-based reconstruction method provides a high reconstruction accuracy under Gaussian noise. For accurate temperature reconstruction under non-Gaussian noise, the Gaussian-Sum filter is applied to 3-D NoC. Compared with the Kalman filter, the Gaussian-Sum filter can reduce the root-mean-squared-error and the max error by 29.27%–35% and 33.26%–40.6%, respectively. A reusable architecture for the Kalman filter and the Gaussian-Sum filter has been proposed. Its hardware implementation details are presented in this paper. Besides, the performance and the area are evaluated as well.

In cyber-physical social systems (CPSS), a group of volunteers report data about the physical environment through their cyber devices and data aggregation is widely utilized. An important issue in data aggregation for CPSS is to protect users’ privacy. In this article, we use bitwise XOR and propose a bit-choosing algorithm to realize privacy-preserving min, k -th min, and percentile computation. By our algorithm, the aggregator can confirm whether a user’s data value is equal to certain value or within certain scale. Consequently, it is also possible to count the number of users satisfying given conditions. Our bit-choosing algorithm makes sure that the users send non-repetition replies to the aggregator to raise the aggregation accuracy. We analyze the communication cost and the achievable accuracy of our algorithm. Via performance comparison against existing protocols, the efficiency and accuracy of our algorithm are verified.

While the intersection of blockchain and Industrial Internet of Things (IIoT) has received considerable research interest lately, the conflict between the high resource requirements of blockchain and the generally inadequate performance of IIoT devices has not been well tackled. On one hand, due to the introductions of mathematical concepts, including Public Key Infrastructure, Merkle Hash Tree, and Proof of Work (PoW), deploying blockchain demands huge computing power. On the other hand, full nodes should synchronize massive block data and deal with numerous transactions in peer-to-peer network, whose occupation of storage capacity and bandwidth makes IIoT devices difficult to afford. In this paper, we propose a lightweight blockchain system called LightChain, which is resource-efficient and suitable for power-constrained IIoT scenarios. Specifically, we present a green consensus mechanism named Synergistic Multiple Proof for stimulating the cooperation of IIoT devices, and a lightweight data structure called LightBlock to streamline broadcast content. Furthermore, we design a novel Unrelated Block Offloading Filter to avoid the unlimited growth of ledger without affecting blockchain's traceability. The extensive experiments demonstrate that LightChain can reduce the individual computational cost to 39.32% and speed up the block generation by up to 74.06%. In terms of storage and network usage, the reductions are 43.35% and 90.55%, respectively.

In the past decade, network data communication has experienced a rapid growth, which has led to explosive congestion in heterogeneous networks. Moreover, the emerging industrial applications, such as automatic driving put forward higher requirements on both networks and devices. On the contrary, running computation-intensive industrial applications locally are constrained by the limited resources of devices. Correspondingly, fog computing has recently emerged to reduce the congestion of content-centric networks. It has proven to be a good way in industry and traffic for reducing network delay and processing time. In addition, device-to-device offloading is viewed as a promising paradigm to transmit network data in mobile environment, especially for autodriving vehicles. In this paper, jointly taking both the network traffic and computation workload of industrial traffic into consideration, we explore a fundamental tradeoff between energy consumption and service delay when provisioning mobile services in vehicular networks. In particular, when the available resource in mobile vehicles becomes a bottleneck, we propose a novel model to depict the users' willingness of contributing their resources to the public. We then formulate a cost minimization problem by exploiting the framework of Markov decision progress (MDP) and propose the dynamic reinforcement learning scheduling algorithm and the deep dynamic scheduling algorithm to solve the offloading decision problem. By adopting different mobile trajectory traces, we conduct extensive simulations to evaluate the performance of the proposed algorithms. The results show that our proposed algorithms outperform other benchmark schemes in the mobile edge networks.

Hashing-based image retrieval methods have become a cutting-edge topic in the information retrieval domain due to their high efficiency and low cost. In order to perform efficient hash learning by simultaneously preserving the semantic similarity and data structures in the feature space, this paper presents the semi-supervised metric learning-based anchor graph hashing method. Our proposed approach can be divided into three parts. First, we exploit a transformation matrix to construct the anchor-based similarity graph of the training set. Second, we propose the objective function based on the triplet relationship, in which the optimal transformation matrix can be learned by using the smoothness of labels and the margin hinge loss incurred by the triplet constraint. Moreover, the stochastic gradient descent (SGD) method leverages the gradient on each triplet to update the transformation matrix. Finally, a penalty factor is designed to accelerate the execution speed of SGD. Through comparison with the retrieval results of several state-of-the-art methods on several image benchmarks, the experiments validate the feasibility and advantages of our proposed methods.

Time-sync comments (TSCs) reveal a new way of extracting the online video tags. However, such TSCs have lots of noises due to users’ diverse comments, introducing great challenges for accurate and fast video tag extractions. In this article, we propose an unsupervised video tag extraction algorithm named Semantic Weight-Inverse Document Frequency (SW-IDF). Specifically, we first generate corresponding semantic association graph (SAG) using semantic similarities and timestamps of the TSCs. Second, we propose two graph cluster algorithms, i.e., dialogue-based algorithm and topic center-based algorithm, to deal with the videos with different density of comments. Third, we design a graph iteration algorithm to assign the weight to each comment based on the degrees of the clustered subgraphs, which can differentiate the meaningful comments from the noises. Finally, we gain the weight of each word by combining Semantic Weight (SW) and Inverse Document Frequency (IDF). In this way, the video tags are extracted automatically in an unsupervised way. Extensive experiments have shown that SW-IDF (dialogue-based algorithm) achieves 0.4210 F1-score and 0.4932 MAP (Mean Average Precision) in high-density comments, 0.4267 F1-score and 0.3623 MAP in low-density comments; while SW-IDF (topic center-based algorithm) achieves 0.4444 F1-score and 0.5122 MAP in high-density comments, 0.4207 F1-score and 0.3522 MAP in low-density comments. It has a better performance than the state-of-the-art unsupervised algorithms in both F1-score and MAP.

The emergence of edge computing has witnessed a fast-growing volume of data on edge devices belonging to different stakeholders which, however, cannot be shared among them due to the lack of the trust. By exploiting blockchain's non-repudiation and non-tampering properties that enable trust, we develop a blockchain-based big data sharing framework to support various applications across resource-limited edges. In particular, we devise a number of novel resource-efficient techniques for the framework: (1) the PoC (Proof-of-Collaboration) based consensus mechanism with low computation complexity which is especially beneficial to the edge devices with low computation capacity, (2) the blockchain transaction filtering and offloading scheme that can significantly reduce the storage overhead, and (3) new types of blockchain transaction (i.e., Express Transaction) and block (i.e., Hollow Block) to enhance the communication efficiency. Extensive experiments are conducted and the results demonstrate the superior performance of our proposal.

With the increasing computation and storage capabilities of mobile devices, the concept of fog computing was proposed to tackle the high communication delay inherent in cloud computing, and also improve the security to some extent. This paper concerns with the privacy issue inherent in the sustainable fog computing platform. However, there is no universal solution to the privacy problem in fog computing due to the device heterogeneity. In this paper, we proposed a differential privacy-based query model for sustainable fog computing supported data center. We designed a method that can quantify the quality of privacy preserving through rigorous mathematical proof. The proposed method uses the query model to capture the structure information of the sustainable fog computing supported data center, and the datasets for the query result are mapped to real vectors. Then, we implemented the differential privacy preserving by injecting Laplacian noise. The experiment results demonstrated that the proposed method can effectively resist various popular privacy attacks, and achieve relatively high data utility under the premise of better privacy preserving.

The video streaming technique and 4G LTE networks have been developing at a high speed, while the advancement of the battery technology is relatively slow. A lot of efforts have been made on understanding the power consumption in general 4G LTE networks, while little attention has been focused on reducing the power consumption of mobile devices for online video streaming in 4G LTE networks. In this paper, we attempt to develop efficient optimization techniques to address this problem. It is an important and also interesting problem, while there are many challenges needing to be alleviated (e.g., the uncertainty of users' behavior modes). To attack the challenges, we suggest a self-adaptive method that can allow us to adjust various parameters dynamically and efficiently, achieving a relatively small energy consumption. We give the rigorous theoretical analysis for the proposed method, and conduct the empirical study to validate its effectiveness.

The property of performing data processing near the source of the data (i.e., at the edge of the network) makes the fog computing more suitable for networking environment of big data. For the sake of achieving efficient big sensory data collection with privacy preservation, this paper proposes a fog computing assisted efficient privacy preserving data collection scheme for big sensory data. In the proposed scheme, the designed layer-aware fog computing architecture provides effective support for exploring the spatio-temporal correlations and avoids long-distance communication with cloud center for utilizing the computation capabilities of local devices. Meanwhile, the proposed sampling perturbation encryption method protects the data privacy against eavesdropper and active attackers without sacrificing the data correlation, and it facilitates the simultaneous executing of decrypting and decompressing operations for encrypted sampling data. Furthermore, the developed data processing at fog node reduces the amount of redundant data transmission significantly, and the formulated optimization model for measurement matrix ensures the high precision of data reconstruction. Finally, the illustrative results reveal that the proposed scheme is an efficient data collection scheme with strong privacy preservation property.

According to efficient performance requirement of big sensory data compression and collection, this paper proposes a fog computing based optimized compressive data collection scheme to enhance recovery quality of original data. In this scheme, mutual correlations of big sensory data are exploited fully owing to the designed data collection architecture. The data processing of fog node urges the computation capability of edge device can be utilized effectively, and which reduces the amount of data transmission significantly. At the same time the constructed encoding and decoding methods among sensory, fog and cloud nodes guarantee successful performing of conventional compressed sensing (CS) reconstruction algorithm with overwhelming probability. In addition, since recovery error is proportional to the mutual coherence among measurement matrix, network coding (NC) transformation matrix and sparsifying basis, a measurement matrix optimization algorithm is constructed to minimize the mutual coherence for stabilizing and enhancing data recovery quality. The desired solution of mutual coherence can be achieved by integrating the alternating minimization and low-pass filtering methods. Simulation results illustrate that the constructed optimization algorithm can obtain the optimal value of mutual coherence, and reconstruction quality of our developed scheme is higher as compared with other compressive data collection schemes.

In the era of information, the services of fog computing environment with content delivery are expected to offer users the better satisfaction of Quality-of- Experience (QoE) than that in a conventional environment. Nevertheless, the dataflow and new demands from users increase along with the promising of content-centric computing system in fog computing environment. Therefore, the satisfaction of QoE will become the major challenge. In this article, to enhance the satisfaction of QoE, we propose QoE models to evaluate the quality of service in fog computing environment concerning both system and users. The value of QoE does not only refer to the system cost, but also the Mean Opinion Score (MOS) of users. Therefore, our models could capture influential factors from system cost based on system states and services for users. Specially, we mainly focus on issues of cache allocation and transmission rate. Under this fog computing environment, aiming to the capacity of cache allocation among fog nodes and handle transmission rates under a constrained total system cost and MOS, we devote our efforts to the following two aspects. First, we formulate the QoE as a joint resource allocation problem under different transmission rates to acquire best QoE. Then, we propose a dynamic algorithm based on shortest path tree (SPT), which is suitable for fog computing environment with content delivery frequently. Simulation results reveal that the benefit for using the dynamic allocation (DA) method to allocate resource can achieve high QoE performance.

Fuel cells are promising power sources for green data centers thanks to its high energy-efficiency, low greenhouse gas emissions and high reliability. However, fuel cells have a unique feature called limited load following, i.e., they are slow in adjusting power supply due to mechanical limitation of fuel delivery. When power demand of data centers suddenly grows, fuel cells would fail to provide sufficient power supply. On the other hand, fuel cells are slow to reduce its power supply when demand decreases, leading to energy waste. In this paper, we study to mitigate the impact of limited load following by associating a set of heterogeneous batteries with fuel cells. These batteries with different characteristics (e.g., capacity, charging and discharging rate) can power data centers when the energy supply of fuel cells is insufficient. They are charged by excessive power supply when demand decreases. Given future power demand, we formulate the energy management problem as a mixed-integer nonlinear programming. An online algorithm is designed to solve the problem without future knowledge. We conduct extensive simulations using real-world traces and results show that our proposed algorithm significantly outperforms existing solutions.

As the critical supplementary to terrestrial communication networks, the low-earth-orbit (LEO) satellite based communication networks regain growing attentions in recent few years. In this paper, we focus on data gathering for geo- distributed Internet-of-Things (IoT) networks via LEO satellites. Normally, the power supply in IoT data-gathering gateways is a bottleneck resource that constrains the network throughput. Thus, the challenge is how to upload data from IoT gateways to LEO satellites under dynamic uplinks in an energy-efficient way. To address this problem, we first formulate a novel optimization problem, and then propose an online algorithm for green data-uploading in geo-distributed IoT networks. In the proposed framework, we aim to jointly maximize the network throughput and minimize the energy consumption at gateways, while avoiding the buffer overflow at gateways. We finally evaluate the performance of the proposed algorithm through simulations using both real-world and synthetic traces. The simulation results demonstrate that the proposed approach can achieve high efficiency on the power consumption and significantly reduce queue backlogs compared with a benchmark using greedy policy.

In the age of big data, the services in pervasive edge environment are expected to offer end-users better Quality of Experience (QoE) than that in a normal edge environment. Nevertheless, various types of edge devices with storage, delivery, and sensing are coming into our environment and produce the high-dimensional big data accompanied by a volume of pervasive big data increasingly with a lot of redundancy. Therefore, the satisfaction of QoE becomes the primary challenge in high dimensional big data on the basis of pervasive edge environment. In this paper, we first propose a QoE model to evaluate the quality of service in pervasive edge environment. The value of QoE does not only include the accurate data, but also the transmission rate. Then, on the basis of the accuracy, we propose a Tensor-Fast Convolutional Neural Network (TF-CNN) algorithm based on Deep Learning, which is suitable for pervasive edge environment with high-dimensional big data analysis. Simulation results reveal that our proposals could achieve high QoE performance.

With the emergence of edge computing in various applications domains, end users are now surrounded by a fast growing volume of data from edge devices belonging to different stakeholders. However, these edge devices cannot cooperate to share big data because of the distrust among them. In this paper, the blockchain is deployed in collaborative edges by exploiting the non-repudiation and non-tampering properties to enable trust. First, we develop a blockchain based big data sharing framework in collaborative edges for adapting to the limited computational and storage resources in edge devices. Then, a consensus mechanism called Proof-of-Collaboration (PoC) is proposed for computational resources reduction in our proposed framework, where edge devices offer their credits of PoC to compete for the block generation. Moreover, we put forward a futile transaction filter algorithm for transaction offloading, greatly reducing the storage resources occupied by the blockchain in edges. Extensive experiments are performed to demonstrate the superior performance of our proposal.

Big data analytics in datacenters often involves scheduling of data-parallel job, which are bottlenecked by limited bandwidth of datacenter networks. To alleviate the shortage of bandwidth, some existing work has proposed traffic compression to reduce the amount of data transmitted over the network. However, their proposed traffic compression works in a coarse-grained manner at job level, leaving a large optimization space unexplored for further performance improvement. In this paper, we propose a flow-level traffic compression and scheduling system, called Swallow, to accelerate data-intensive applications. Specifically, we target on coflows, which is an elegant abstraction of parallel flows generated by big data jobs. With the objective of minimizing coflow completion time (CCT), we propose a heuristic algorithm called Fastest-Volume-Disposal-First (FVDV) and implement Swallow based on Spark. The results of both trace-driven simulations and real experiments show the superiority of our system, over existing algorithms. Swallow can reduce CCT and job completion time (JCT) by up to 1.47 × and 1.66 × on average, respectively, over the SEBF in Varys, one of the most efficient coflow scheduling algorithms so far. Moreover, with coflow compression, Swallow reduces data traffic by up to 48.41% on average.

In this paper, we investigate the problem of minimizing the long-term total cost (i.e., the sum of energy cost and thermal discomfort cost) associated with a heating, ventilation, and air conditioning (HVAC) system of a multizone commercial building under smart grid environment. To be specific, we first formulate a stochastic program to minimize the time average expected total cost with the consideration of uncertainties in electricity price, outdoor temperature, the most comfortable temperature level, and external thermal disturbance. Due to the existence of temporally and spatially coupled constraints as well as unknown information about the future system parameters, it is very challenging to solve the formulated problem. To this end, we propose a real-time HVAC control algorithm based on the framework of Lyapunov optimization techniques without the need to predict any system parameters and know their stochastic information. The key idea of the proposed algorithm is to construct and stabilize virtual queues associated with indoor temperatures of all zones. Moreover, we provide a distributed implementation of the proposed real-time algorithm with the aim of protecting user privacy and enhancing algorithmic scalability. Extensive simulation results based on real-world traces show that the proposed algorithm could reduce energy cost effectively with small sacrifice in thermal comfort.

Energy router (ER) based system is a crucial part of the energy transmission and management under the circumstance of energy Internet for green cities. During its design process, a sound formal verification and a performance monitoring scheme are needed to check its reliability and meaningful quantitative properties. In this paper, we provide formal verification solutions for an ER-based system by proposing a continuous-time Markov chain model describing the architecture of the ER-based system. To verify real-world function of the ER-based system, we choose electricity trading to propose a Markov decision process model based on an ER subsystem to describe the trading behavior. To monitor the system performance, we project the energy scheduling process in the ER-based system, and then implement this scheduling process on top of a cloud computing experiment tool. Finally, we perform extensive experiment evaluations to investigate the system reliability properties, quantitative properties, and scheduling behaviors. The experiment verifies the effectiveness of the proposed models and the monitoring scheme.

This paper studies the secure transmission rate issue between sensors and the remote controller to defend the jamming and eavesdropping attacks in green cyber-physical transportation systems. In this system, the traffic sensor transmits the transportation state information to the remote controller via wireless networks. Due to the broadcast characteristics of the wireless communication, the systems are vulnerable to the eavesdropping and jamming attacks. In this paper, we study how to maximize the secure transmission rate between sensors and the controller in the presence of a malicious eavesdropper and a jammer. Specifically, the malicious jammer is smart and can choose the optimal power strategy to maximize the side effect with the knowledge of sensor's transmission power. For the purpose of achieving the maximum utility, the optimal strategy is determined via adjusting the sensor's transmission power according to the control feedback conditions. We consider the single-antenna model and the multiantenna model to formulate this problem as an optimization problem based on a Stackelberg game. We then prove the existence of the Stackelberg equilibrium via the interaction between the sensor and the jammer. Moreover, we present two algorithms to obtain the optimal transmission strategy, i.e., a stochastic algorithm with feedback and renewed intelligent simulated annealing. Finally, extensive simulations and trace experimental results are presented to verify our theoretical analysis.

The widely used RFID systems are vulnerable to the denial-of-service (DoS) attacks launched by malicious blocker tags. This paper studies how to quickly and completely identify the valid RFID tags that are blocked. The existing work that can seemingly address this problem suffers from either low time-efficiency or serious false positives. This paper proposes a hybrid approach that consists of two complementary component protocols, namelyAloha Filtering(AF) andPoll&Listen(PL).AFis fast but inaccurate, whilePLis accurate but slow. Taking the merit of each protocol, our hybrid approach is to first repeat the fastAFfor multiple rounds to quickly filter out the target tags that are definitely not blocked. Then, on the size-reduced remaining set that just contains a small number of suspicious tags, we invoke the accuratePLto verify the intactness of each suspicious tag with 100 percent confidence. We optimize the round count ofAFthat trades off between the time costs ofAFandPLto minimize the total time ofAF+PL. As required in the optimization process, we need to know the size of the blocked tag set and that of the unknown tag set, which, however, are not known in advance. To estimate these two set sizes, we propose a supplementary protocol calledSimultaneous Estimation of the Blocked tag size and the Unknown tag size(SEBU). The key advantages of our approach over the prior art are four-fold. First, unlike the detection protocol that just discovers the existence of blocking attacks, our approach exactly identifies all the blocked target tags. Second, our approach is compliant with the C1G2 standard, and does not require any modifications to be made to the commercial RFID tags. It only needs to be installed on readers as a software module. Third, our approach does not involve any false positives. Finally, our approach significantly reduces the execution time when compared with the state-of-the-art schemes that can completely identify the blocked tags.

Green energy router (ER) system is a crucial part in the energy transmission and management under the circumstance of Energy Internet and green communication. During its design process a sound formal verification is needed to check its reliability and meaningful quantitative properties. In this paper, we first propose two models describing the architecture of ER system using continuous-time Markov chains. To verify real world function of the ER, we choose electricity trading to propose an Markov decision process model based on an ER subsystem to describe the trading behaviour. Finally, we perform extensive experiment evaluations to investigate the system reliability properties, quantitative properties. The experiment verifies the effectiveness of the proposed models.

With the ubiquitous deployment of the mobile devices and the explosive growth of Internet traffic, an emerging method called association rules mining (ARM) is proposed to solve the problem of mining potential value of existing big data. However, massive ARM methods focus on positive rules which are easy to ignore interesting information because of negative ones. This paper studies a practical problem of combing negative rules in ARM research. Specifically, we propose a rule certainty updating strategy (RCUS) to combine positive rules with negative rules, which consists of two parts: initialization and updating. To solve the large scale problem with negative rules, the proposed strategy decomposes the large scale problem into several relatively small ones by an improved multiobjective evolutionary algorithm (MOEA) with gene representation and certainty. Simulation results show that our method is outstanding when the scale of attributes and examples is increasing.

Device-to-device (D2D) communication is a promising technology for expanding the next generation wireless cellular network. To deal with the security challenges and optimize the system communication quality, this paper investigates the security and efficiency problem in D2D underlay communication with the presence of malicious eavesdroppers. Fairness and strategy space of both D2D user equipment (DUE) and cellular user equipment (CUE) are taken into consideration under the control of proposed efficiency functions. Problems are formulated as a series of utility functions built on the unit price of jamming power and the amount of jamming service. Extracting system model into a price negotiation under Bargaining Game (PNBG) that a buyer and a seller both desiring maximum its profits, we solve the problems by reaching an agreement of the two sides. The step number of bargain process is also a restriction under consideration. For the Non-Step scheme, an Evaluation Function (EF) and a Comprehensive Utility Function (CUF) are demonstrated to analyze the negotiation process. For Step-Contained scheme, the step number of iteration is involved and an Attenuation Function (AF) is introduced to modify the Bargaining Game. Algorithms of two schemes are designed to derive the equilibrium point for reaching an agreement. Finally, simulations are illustrated for verifying proposed approach.

Some sleep disorders, such as sleep apnea, restless legs syndromes (RLS), and periodic limb movement disorder (PLMD), require a full-night sleep monitoring for diagnosis. Conventional sleep monitoring devices are disturbing and inconvenient for daily scene applications. In this poster paper, we propose a sleep monitoring system by embedding RFID tags into bed cloth and realize two main functions: breath monitoring and body movement detection. We apply a finite impulse response low pass filter to get smooth breath signal wave and use a convolutional neural network (CNN) algorithm to identify the movement of person objects. Finally, we conduct experiments to evaluate the breath monitoring in a real world scenario. The experiment results show that our monitoring system can monitor breath with a high accuracy.

With the ubiquitous deployment of the mobile devices with increasingly better communication and computation capabilities, an emerging model called spatial crowdsourcing is proposed to solve the problem of unstructured big data by publishing location-based tasks to participating workers. However, massive spatial data generated by spatial crowdsourcing entails a critical challenge that the system has to guarantee quality control of crowdsourcing. This paper first studies a practical problem of task assignment, namely reliability aware spatial crowdsourcing (RA-SC), which takes the constrained tasks and numerous dynamic workers into consideration. Specifically, the worker confidence is introduced to reflect the completion reliability of the assigned task. Our RA-SC problem is to perform task assignments such that the reliability under budget constraints is maximized. Then, we reveal the typical property of the proposed problem, and design an effective strategy to achieve a high reliability of the task assignment. Besides the theoretical analysis, extensive experimental results also demonstrate that the proposed strategy is stable and effective for spatial crowdsourcing.

This paper focuses on the security issue in Cyber-Physical Systems. The sensor transmits the state estimation information to the remote controller via wireless networks. Due to the broadcast characteristics of wireless communication, the systems are vulnerable to the eavesdropping attacks and jamming attacks. In this paper, we study how to maximize the secure transmission rate between sensors and controller with the presence of malicious eavesdropper and jammer. The malicious jammer is smart and can choose the optimal power strategy to maximize the side effect with the knowledge of sensor's transmission power. When the sensor adjusts its transmission power to achieve the maximum utility, the control feedback is used to adjust the optimal strategy in CPS. We formulate this proposed problem as a Stackelberg game such that the optimal power allocation strategy is achieved. We further prove the existence of Stackelberg equilibrium by obtaining the interaction between the sensor and the jammer. To tackle this optimization problem, we present a stochastic algorithm with feedback (SAF) algorithm. As a result, the optimal transmission strategy is obtained. Finally, extensive simulations are presented to verify our theoretical analysis.

Time-sync comments reveal a new way of extracting the online video tags. However, such time-sync comments have lots of noises due to users' diverse comments, introducing great challenges for accurate and fast video tag extractions. In this paper, we propose an unsupervised video tag extraction algorithm named Semantic Weight-Inverse Document Frequency (SW-IDF). SW-IDF first generates corresponding semantic association graph (SAG) using semantic similarities and timestamps of the time-sync comments. Then it clusters the comments into sub-graphs of different topics and assigns weight to each comment based on SAG. This can clearly differentiate the meaningful comments with the noises. In this way, the noises can be identified, and effectively eliminated. Extensive experiments have shown that SW-IDF can achieve 0.3045 precision and 0.6530 recall in high-density comments; 0.3800 precision and 0.4460 recall in low-density comments. It is the best performance among the existing unsupervised algorithms.

For better service provision and utilization of renewable energy, Internet service providers have already built their data centers in geographically distributed locations. These companies balance quality of service (QoS) revenue and power consumption by migrating virtual machines (VMs) and allocating the resource of servers adaptively. However, existing approaches model the QoS revenue by service-level agreement (SLA) violation, and ignore the network communication cost and immigration time. In this paper, we propose a reinforcement learning-based adaptive resource management algorithm, which aims to get the balance between QoS revenue and power consumption. Our algorithm does not need to assume prior distribution of resource requirements, and is robust in actual workload. It outperforms other existing approaches in three aspects: (1) The QoS revenue is directly modeled by differentiated revenue of different tasks, instead of using SLA violation. (2) For geodistributed data centers, the time spent on VM migration and network communication cost are taken into consideration. (3) The information storage and random action selection of reinforcement learning algorithms are optimized for rapid decision making. Experiments show that our proposed algorithm is more robust than the existing algorithms. Besides, the power consumption of our algorithm is around 13.3% and 9.6% better than the existing algorithms in non-differentiated and differentiated services.

In this paper, we present a robust beamforming (BF) scheme to improve the physical layer security (PLS) of a cognitive satellite terrestrial network (CSTN) at millimeter wave (mmWave) frequency. By employing the standard recommendations and the mmWave propagation model, a PLS framework is first defined for the CSTN in the presence of multiple eavesdroppers (Eves). A constrained optimization problem is then formulated to maximize the worst-case achievable secrecy rate of the cellular user subject to an allowable interference level for the satellite user. By expressing the imperfect Eve''s channel state information (CSI) as a combination of many given angle-of-arrival (AOA) based discrete sets, we propose a method to transform the worst-case optimization problem into a min-max problem and then develop an iterative BF scheme to yield an analytical solution for the weight vectors. Finally, simulation results confirming the effectiveness and superiority of the proposed BF scheme are provided.

Summary By applying the cloud manufacturing paradigm in the regional enterprise cluster, the enterprises or facilities may collaborate extensively for efficiently utilizing the manufacturing resources. It is valuable to explore and design the strategies of facilities selection for the autonomic control of the collaboration behaviors in production. In this paper, we model the collaboration relations in the regional enterprise cluster as a generalized social collaboration network and explore the dynamic growth process of the Facilities Collaboration Network for different strategies of facilities selection, including the random selection with and without preference, and the balanced selection with and without preference. With performance indexes such as network size, the distribution of node degree and act degree, clustering coefficient, the average shortest distance, and the number of n‐cliques, we present and analyze the characteristics of these strategies for cloud manufacturing. Next, based on these characteristics, we propose 2 mechanisms for self‐optimization in facilities collaboration, including the dynamic weighing of facilities and the concentrated processing of successive subtasks in the process. We also analyze the mechanisms' effects on the characteristics of Facilities Collaboration Network and the performance in manufacturing. Copyright © 2016 John Wiley & Sons, Ltd.

According to the practical requirements of high recovery precision and low latency in wireless big sensory data networks, this paper proposes an accelerated distributed rate control method for minimizing the recovery error of big sensory data. This method can guarantee the error minimization of reconstructed data and converge to the optimal value fast with a lower latency. In order to achieve these effects, an accelerated distributed solving algorithm is constructed by designing accelerated subgradient method for dual decomposition. This solving algorithm achieves convergence rate O(1/t2) in practical implementation, which significantly improves the convergence rate of regular solving algorithms. Meanwhile, the convergence analysis testifies the convergence property of the proposed distributed solving algorithm, and this algorithm is applicable to other convex optimization problems. Finally, the performance evaluation shows that the proposed accelerated method can converge to the unique optimal value successfully and the convergence speed is faster than the regular optimization method, and this proposed method can be extended to networks of different sizes without sacrificing the accelerated effect.

Thermal sensor noise has a great impact on the efficiency and effectiveness of a dynamic thermal management (DTM) strategy. To address the problem of forecasting temperature based on noisy thermal sensors, we first propose a Kalman-based runtime thermal prediction scheme. To obtain accurate temperature predictions, a multivariate linear power model and a physically-based state space thermal model for 3-D network-on-chip are also proposed. Simulation results show that it reduces the standard deviations of the prediction error by 46%–53% compared with the auto-regressive based one under sensor noise with${\sigma =2}$. Conventional reactive DTM techniques suffer from significant performance degradation due to their pessimistic reaction, thus, based on the proposed prediction scheme, we further propose a proactive DTM strategy that primarily consists of a thermal-aware routing algorithm and a proactive throttling scheme: 1) to take into account both thermal and congestion issues, we propose a proactive congestion and thermal aware routing algorithm. Simulation results demonstrate that it can achieve better throughput as well as approach better thermal balance. Specifically, under uniform traffic, the proposed scheme reduces the maximum chip temperature by about 3.9 °C and achieves 78.3% higher throughput compared with the competing thermal optimization approach based on dynamic programming network and 2) when the temperature exceeds the threshold, existing coarse-grained reactive throttling schemes cool down the overheated nodes at the penalty of significant performance loss. In this paper, a proactive quota-based throttling scheme is proposed. Simulation results show that it improves the throughput up to 11.1% compared with the reactive throttling schemes.

Transmembrane proteins play important roles in cellular energy production, signal transmission, and metabolism. Many shallow machine learning methods have been applied to transmembrane topology prediction, but the performance was limited by the large size of membrane proteins and the complex biological evolution information behind the sequence. In this paper, we proposed a novel deep approach based on conditional random fields named as dCRF-TM for predicting the topology of transmembrane proteins. Conditional random fields take into account more complicated interrelation between residue labels in full-length sequence than HMM and SVM-based methods. Three widely-used datasets were employed in the benchmark. DCRF-TM had the accuracy 95 percent over helix location prediction and the accuracy 78 percent over helix number prediction. DCRF-TM demonstrated a more robust performance on large size proteins (>350 residues) against 11 state-of-the-art predictors. Further dCRF-TM was applied to ab initio modeling three-dimensional structures of seven-transmembrane receptors, also known as G protein-coupled receptors. The predictions on 24 solved G protein-coupled receptors and unsolved vasopressin V2 receptor illustrated that dCRF-TM helped abGPCR-I-TASSER to improve TM-score 34.3 percent rather than using the random transmembrane definition. Two out of five predicted models caught the experimental verified disulfide bonds in vasopressin V2 receptor.

Underwater acoustic sensor networks (UASNs) are susceptible to a large number of security threats, e.g., jamming attacks at the physical layer, collision attacks at the data link layer, and DoS attacks at the network layer. Because of the communication, computation, and storage constraints of underwater sensor nodes, traditional security mechanisms, e.g., encryption algorithms, are not suitable for UASNs. A trust model has been recently suggested as an effective security mechanism for open environments such as terrestrial wireless sensor networks (TWSNs), and considerable research has been done on modeling and managing trust relationships among sensor nodes. However, the trust models proposed for TWSNs cannot be directly used in a UASN due to its unique characteristics such as unreliable acoustic channel, dynamic network structure, and weak link connectivity. In this paper, we propose a novel trust model based on cloud theory (TMC) for UASNs. The objective of TMC is to solve uncertainty and fuzziness of trust based on cloud theory, which ultimately improves trust evaluation accuracy. Moreover, simulation results demonstrate that our algorithm outperforms other related works in terms of detection ratio of malicious nodes, successful packet delivery ratio, and network lifetime.

With the significant improvements in the Energy Internet, we have witnessed the explosion of multisource energy big data, whose characteristics of vast volume, fast velocity, and diverse variety not only formulate an essential infrastructure of the Energy Internet, but also bring threats to the system's stability. In this paper, we concern with the system-level stability issues in the Energy Internet and study how to maintain a stable and healthy energy network environment. To this end, we propose a system-level stability evaluation model in the Energy Internet based on a critical energy function to explore small disturbance stability region (SDSR), where SDSR can be acquired via estimating the operational data threshold of distributed generations. The threshold is estimated based on energy consumption rather than equilibrium nodes, which applies the energy function theory and reduces the computation complexity. Moreover, in our proposed model, we add the big data approximate analytics algorithm into hyperplane fitting to optimize and analyze the SDSR. Simulation results on SDSR in a single dominant oscillation mode and multiple dominant oscillation mode have demonstrated the advantages and superiority of our proposed method over the prior schemes.

For categorized RFID systems, this paper studies the practically important problem of top-k queries, which is to find the top-k smallest and (or) the top-k largest categories, as well as the sizes of such categories. In this paper, we propose a Top-k Query (TKQ) protocol and two supplementary techniques called segmented perfect hashing (SPH) and switching to framed slotted aloha (STA) for optimizing TKQ. First, TKQ lets each tag choose a time slot to respond to the reader with a single-one geometric string using the ON-OFF Keying modulation. TKQ leverages the length of continuous leading 1 s in the combined signal to estimate the corresponding category size. TKQ can quickly eliminate most categories whose sizes are significantly different from the top-k boundary, and only needs to perform accurate estimation on a limited number of categories that may be within the top-k set. We conduct rigorous analysis to guarantee the predefined accuracy constraints on the query results. Second, to alleviate the low frame utilization of TKQ, we propose the SPH scheme, which improves its average frame utilization from 36.8% to nearly 100% by establishing a bijective mapping between tag categories and slots. To minimize the overall time cost, we optimize the key parameter that trades off between communication cost and computation cost. Third, we observed from the simulation traces that TKQ+SPH pays most execution time on querying a small number of remaining categories whose sizes are close to the top-k boundary, which sometimes even exceeds the time cost for precisely identifying these remaining tags. Motivated by this observation, we propose the STA scheme to dynamically determine when we should terminate TKQ+SPH and switch to use FSA to finish the rest of top-k query. Experimental results show that TKQ+SPH+STA not only achieves the required accuracy constraints, but also achieves several times faster speed than the existing protocols.

Big data analytics has attracted close attention from both industry and academic because of its great benefits in cost reduction and better decision making. As the fast growth of various global services, there is an increasing need for big data analytics across multiple data centers (DCs) located in different countries or regions. It asks for the support of a cross-DC data processing platform optimized for the geo-distributed computing environment. Although some recent efforts have been made for geo-distributed big data analytics, they cannot guarantee predictable job completion time, and would incur excessive traffic overthe inter-DC network that is a scarce resource shared by many applications. In this paper, we study to minimize the inter-DC traffic generated by MapReduce jobs targeting on geo-distributed big data, while providing predicted job completion time. To achieve this goal, we formulate an optimization problem by jointly considering input data movement and task placement. Furthermore, we guarantee predictable job completion time by applying the chance-constrained optimization technique, such that the MapReduce job can finish within a predefined job completion time with high probability. To evaluate the performance of our proposal, we conduct extensive simulations using real traces generated by a set of queries on Hive. The results show that our proposal can reduce 55 percent inter-DC traffic compared with centralized processing by aggregating all data to a single data center.

Energy Internet (EI) is proposed as the evolution of smart grid, aiming to integrate various forms of energy into a highly flexible and efficient grid that provides energy packing and routing functions, similar to the Internet. As an essential part in EI system, a scalable and interoperable communication infrastructure is critical in system construction and operation. In this article, we survey the recent research efforts on EI communications. The motivation and key concepts of EI are first introduced, followed by the key technologies and standardizations enabling the EI communications as well as security issues. Open challenges in system complexity, efficiency, reliability are explored and recent achievements in these research topics are summarized as well.

Demand side management (DSM) is a key mechanism to make smart grids cost efficient using electricity price forecasting issue. Price forecasting method takes the big price data into account, and gives estimates of the future electricity price. However, most of existing price forecasting methods cannot avoid redundancy at feature selection and lack of an integrated framework that coordinates the steps in forecasting. To address this issue, we first propose a new electricity price forecasting framework. It is significant to design a system tool chain based on big data analytics for ensuring that the users can make appropriate decisions. To this end, three algorithms are proposed integratedly. First, feature redundancy elimination is implemented by the fusion of Grey Correlation Analysis (GCA) and ReliefF algorithm. Second, a combination of Kernel function and Principle Component Analysis (KPCA) is designed to achieve dimensionality reduction. Finally, Support Vector Machine (SVM) optimization algorithm based on differential evolution (DE) is proposed to forecast price classification. These three modules jointly power the price forecasting system. Simulation results show the superiority of our proposed framework.

The advances of network technology and mobile communication technology are making eHealth possible. In eHealth systems, physiological data and relevant context-aware data are acquired continuously and in real time. At the same time, such large-scale data results in huge challenges in the aspect of real-time big data processing since eHealth data appears in the form of data stream. Therefore, we propose a novel incremental learning algorithm, namely α-SVMSGD, which improves the SVMSGD (Support Vector Machine-Stochastic Gradient Descent) algorithm by updating the training data with the continuous data stream. Besides, this α-SVMSGD may handle the problem that original SVMSGD cannot further mine the useful information in unclassified data. In α-SVMSGD, the process of training data updating is completed by introducing the concept of forgetting mechanism, in which the forgetting factor α is introduced to weed out useless training data. α-SVMSGD is applied into ambient assisted living communications, and further incorporated into the data filtering layer of a local data processing architecture (LDPA) to reduce data redundancy. Simulation results confirm that the proposed algorithm is a promising data redundancy solution for classification without loss of accuracy in the case of real-time data stream.

To avoid an additional demand charge incurred by the adoption of electric vehicles (EVs), we study an online cost minimization problem for geo-distributed data centers and EVs of their employees without violating heterogeneous EV charging delays and the given peak power limits in all geographical locations, where the total cost consists of the electricity bill, revenue loss, and the penalty imposed on unfinished EV demands. We first formulate a stochastic programming problem with the considerations of uncertainties in data center workloads, electricity prices, and EV energy demands. Since the future parameters are uncertain, an online algorithm is proposed to solve the formulated problem. Moreover, the performance analysis of the online algorithm is conducted. Simulation results indicate the advantages of the proposed algorithm over other baselines.

Thermal sensor noise has great impact on the efficiency and effectiveness of a dynamic thermal management (DTM) strategy. Conventional reactive thermal management techniques suffer significant performance degradation due to the pessimistic reaction. In this paper, to address the problem of forecasting temperatures based on noisy thermal readings, we propose a Kalman predictor based runtime thermal prediction scheme, which can predict temperatures N step ahead. An activity-based power model for 3D NoC power estimation is also proposed; the model is an essential prerequisite of accurate temperature predictions. Besides that, we propose a distributed multi-input single-output (MISO) thermal model for 3D NoC systems, which reduces the computational complexity of temperature updating from m2 to m compared with the centralized multi-input multi-output (MIMO) model for the system with m units. The experimental results show that the proposed prediction scheme reduces the mean absolute error (MAE) by 42.8%-72.6% compared with the auto-regressive (AR) based prediction scheme.

Machine-to-Machine (M2M) mobile networks are distributed systems which include various actuators and sensors. In terms of the security of M2M mobile networks, one very significant issue is the security of Sensor Networks (SNs). Particularly, the security of transferring data from sensors to their destinations is very critical. In this paper, focusing on intrusion detection techniques, we propose an attack-defense game model to detect malicious nodes using a repeated game approach. In the proposed game model, attackers and defenders make different strategies to achieve optimal payoffs. The existences of pure nash equilibrium and mixed nash equilibrium are analyzed and proved. In the Intrusion Detection System (IDS), a game tree model is introduced to solve the error detection and missing detection problems. Simulation results present that the proposed model can reduce energy consumption by up to 50% compared with the All Monitor (AM) model, and improve the detection rate by up to 10-15% compared with the Cluster Head (CH) monitor model.

Focusing on the leak-points in petrochemical industries, this paper discusses the key factors (i.e., equipment temperature, gas pressure, and diffusion rate) in petrochemical industries. Data from sensors of petrochemical industries need to be timely operated because of time sensitivity and it is hard to achieve associated information from sensors located in production sites. To this end, we propose a three-level framework based on improved back propagation (TLBP). The real-time data streams are processed according to the arriving time in input layer. At the same time, a neuron-optimizing solution is introduced in learning process to deal with redundant and invalid neurons, thereby accelerating the response speed of learning and reducing the prediction time. Finally, we propose an improved mechanism of the multidimensional learning factor to lower the learning error and higher convergence rate. Meanwhile, to fulfill the distributed prediction on leak-points, we see one three-level data-processing unit as a logic machine with multiple operators. Using the assignment scheduling, the general scheduling problem is split into the common subproblem of every operator and the system overhead is reduced. With the processed data we can obtain the relative location or diffusion radius of leak-points, as well as the area of leak-points. Simulation results show that the TLBP performs better than related algorithms in different metrics. Besides, the adaptability of TLBP is verified in leak-points prediction of petrochemical equipment from the processed data.

In the age of multimedia big data, the popularity of mobile devices has been in an unprecedented growth, the speed of data increasing is faster than ever before, and Internet traffic is rapidly increasing, not only in volume but also in heterogeneity. Therefore, data processing and network overload have become two urgent problems. To address these problems, extensive papers have been published on image analysis using deep learning, but only a few works have exploited this approach for video analysis. In this article, a hybrid-stream model is proposed to solve these problems for video analysis. Functionality of this model covers Data Preprocessing, Data Classification, and Data-Load-Reduction Processing. Specifically, an improved Convolutional Neural Networks (CNN) classification algorithm is designed to evaluate the importance of each video frame and video clip to enhance classification precision. Then, a reliable keyframe extraction mechanism will recognize the importance of each frame or clip, and decide whether to abandon it automatically by a series of correlation operations. The model will reduce data load to a dynamic threshold changed by σ, control the input size of the video in mobile Internet, and thus reduce network overload. Through experimental simulations, we find that the size of processed video has been effectively reduced and the quality of experience (QoE) has not been lowered due to a suitably selected parameter η. The simulation also shows that the model has a steady performance and is powerful enough for continuously growing multimedia big data.

Due to the limited energy of sensors and the difficulties in battery replacement in DTMSN (Delay Tolerant Mobile Sensor Network), unbalanced energy consumption will exhaust the batteries of active sensors soon, which can significantly reduce the network lifetime. Fortunately, this problem can be solved through multi-hop relay transmission where those energy-aware sensors with the maximum remaining energy will be selected to forward packets. However, one of the major challenges of multi-hop relay transmission in DTMSN is how to schedule these mobile sensors travelling paths in an energy-balanced way so that their overall lifetime is maximized. In this paper, an energy-balanced multi-hop relay transmission scheme based on RVNS (Reduced Variable Neighborhood Search) in DTMSN is proposed. Firstly, several parameters are designed to calculate the remaining energy of each sensor. Then RVNS is applied to obtain the global optimal solution. RVNS is implemented to select a sensor node with maximum remaining energy as the next hop relay, delivering packets to destination through multi-hop relay transmission. Simulation results demonstrate that in a delay-tolerant condition, the proposed scheme significantly balances the energy consumption and improves the packet delivery ratio.

In Delay Tolerant Networks (DTN), the resource utilization is decreased because of the limited resources and redundant copies. This paper proposes an improved Socially Aware Feedback Mechanism (SAFM). In this mechanism, the historical information of the encountered nodes are utilized to construct social links which indicates the level of social relationship between nodes. In the feedback process, acknowledgements are forwarded to the nodes whose Social Link (SL) is higher than a given threshold α. After getting the acknowledgements, nodes will delete the copies of messages which have been received by the destination nodes, so as to reduce the redundancy. In simulation, the threshold α is obtained to reach the best performance of SAFM. Compared with active and passive receipt approaches in an acceptable range of delay, SAFM improves the delivery probability, decreases the buffer occupancy and reduces the overhead.

Due to the limited resources of DTMSN (Delay Tolerant Mobile Sensor Networks), network congestion becomes a critical problem to resolve. Traditional congestion control methods where the number of copies is restricted to limit data packet forwarding cannot adapt to constantly changing network environment because of fixed number of copies. Fortunately, this problem can be solved through a real-time algorithm by modifying data packet forwarding conditions. However, one of the major challenges of this algorithm is detecting characteristics of the network environment accurately and efficiently. In this paper, an optimized routing algorithm, RVNS (Reduced Variable Neighborhood Search)-based Spray and Wait (SW) is proposed. In this algorithm, nodes will transmit and store the counter record of each other when they meet, based on which, RVNS is introduced to calculate a real-time threshold for the forwarding condition to control packet delivery. Simulation results show that the proposed algorithm increases delivery probability and dramatically reduces the overhead ratio. In some extreme cases, this algorithm can reach an extremely low overhead ratio (ten times lower than that of SW), meaning that the proposed algorithm suits challenged networks well.

In the probabilistic routing algorithms of DT-MSN (Delay Tolerant-Mobile Sensor Networks), packet delivery only depends on the probability of transmitting to its destination node. The prediction of probability is not reasonable because of not considering every node's activity level. In this paper, by mixing a node activity factor into the prediction of delivery probability, we propose a Node Activity-based Probabilistic Routing algorithm (NAPR). First, a physical quantity denoted by node activity is introduced to indicate the nodes' active level in the network. The proposed algorithm takes the encountering records and the nodes' active level into consideration. Second, by using parameter α to weigh the original probabilistic factor and the active level factor, a new weighted average value serves as a packet Delivery Predictability (DP). Nodes will compare the DP to decide whether the packet is delivered and the change of weighted factor α will have an impact on the relationship between nodes' active level factor and DP. Besides, NAPR adopts the TTL (Time To Live)-based discarding strategy to manage nodes' buffer space. Simulation results show that NAPR improves the DP and delivery ratio of packets and shortens the average delivery delay. Meanwhile, the number of packet copies and overhead ratio decreases accordingly.

This paper investigates the problem of link scheduling in a single-hop energy harvesting wireless body area network (EH-WBANs) where sensor devices's energy harvesting rates and data rates are spatially heterogeneous and temporally variant. To maximize the channel utilization with the lifetime operation, an adaptive TDMA-based protocol (AT-MAC) is proposed, which is suitable for communication in an EH-WBAN for remote monitoring of physiological signals. In this protocol, a duty cycle can be dynamically adjusted to maintain the harvested energy amount, which is always greater than power consumption. Also, a novel time-slot allocation algorithm is designed to automatically adjust duty cycle with various data traffic and harvesting rates. This algorithm is decomposed into two sub-processes: predistribution of time-slot and redistribution of time-slot. The former process takes the information of energy harvesting rates into account, regardless of the rates varying in a nondeterministic manner and among various sensor nodes. For the latter process, the number of distributed time slots will be further adjusted to cope with data traffic of spatially heterogeneousness. Simulation results demonstrate the proposed protocal is a promising candidate for realizing the lifetime operation in EH-WBANs.

In Energy-Harvesting Wireless Body Area Networks (EH-WBANs), how to realize a power management strategy to enable lifetime operation is one of the most concern problems. To solve this problem, a feasible solution should be used to manage the harvested energy in sensor nodes in an EH-WBAN. So far, there are extensive studies about this issue for EH-WBANs. Unfortunately, the significant character of energy harvesting rates is ignored in existing solutions, which has immediate impact on the effectiveness and efficiency of energy harvesting in EH-WBANs. To handle this critical challenge, this paper propose a harvesting-rate oriented self-adaptive algorithm for enabling lifetime operation in EH-WBANs, in which a duty cycle can be dynamically adjusted to maintain the harvested energy amount always greater than the power consumption. In this study, the widely cited TDMA-based frame structure is chosen as the EH-WBAN architecture as well. To exploit the full potentials of the TDMA-based frame structure for energy harvesting, a self-adaptive mechanism is devised to adjust the on-to-off ratio within a duty cycle automatically in the proposal, in which the information of energy harvesting rates can be taken into account, regardless of the rates how varying in a nondeterministic manner and among various sensor nodes in EH-WBANs. To evaluate this algorithm, a demo is configured, which test results demonstrate the proposal is a promising candidate for realizing the lifetime operation in EH-WBANs.

Distributed devices in smart grid systems are decentralized and connected to the power grid through different types of equipment transmit, which will produce numerous energy losses when power flows from one bus to another. One of the most efficient approaches to reduce energy losses is to integrate distributed generations (DGs), mostly renewable energy sources. However, the uncertainty of DG may cause instability issues. Additionally, due to the similar consumption habits of customers, the peak load period of power consumption may cause congestion in the power grid and affect the energy delivery. Energy management with DG regulation is considered to be one of the most efficient solutions for solving these instability issues. In this paper, we consider a power system with both distributed generators and customers, and propose a distributed locational marginal pricing (DLMP)-based unified energy management system (uEMS) model, which, unlike previous works, considers both increasing profit benefits for DGs and increasing stability of the distributed power system (DPS). The model contains two parts: 1) a game theory-based loss reduction allocation (LRA); and 2) a load feedback control (LFC) with price elasticity. In the former component, we develop an iterative loss reduction method using DLMP to remunerate DGs for their participation in energy loss reduction. By using iterative LRA to calculate energy loss reduction, the model accurately rewards DG contribution and offers a fair competitive market. Furthermore, the overall profit of all DGs is maximized by utilizing game theory to calculate an optimal LRA scheme for calculating the distributed loss of every DG in each time slot. In the latter component of the model, we propose an LFC submodel with price elasticity, where a DLMP feedback signal is calculated by customer demand to regulate peak-load value. In uEMS, LFC first determines the DLMP signal of a customer bus by a time-shift load optimization (LO) algorithm based on the changes of customer demand, which is fed back to the DLMP of the customer bus at the next slot-time, allowing for peak-load regulation via price elasticity. Results based on the IEEE 37-bus feeder system show that the proposed uEMS model can increase DG benefits and improve system stability.

The popularization and application of Cloud Computing have provided a new approach for users to get computing resources in recent years. Meanwhile, due to the advantages including programmability and power-efficiency, FPGAs have been applied to custom computing in many domains. Previous work has made resources of FPGA available under the cloud environment. However, the effective usage of FPGAs in the cloud requires efficient online task scheduling: to properly assign as many tasks from different tenants as possible to the FPGAs. In this paper, we propose a benefit-based scheduling metric to evaluate the task assignment Based on the metric, we accelerate task execution according to our benefit-based scheduling algorithms. By applying our benefit-based scheduling metric to a real OpenStack-based cloud environment, 60.32% computing resources are saved compared with the conventional throughput-based metric. Furthermore, a Replacement-Considering algorithm, which considers the task replacement, is proposed taking the characteristics of cloud into account. The results show that our FPGA accelerated cloud system is 1.386 times faster than using the previous algorithm.

The routing efficiency in Delay Tolerant Networks (DTN) with social characteristics degrades owing to intermittent connection and high latency. Additionally, congestion is another issue because of the limited resources of nodes. To solve these problems, an improved Socially Aware Congestion Control algorithm (SACC) is proposed. In this algorithm, the social features and the congestion level of the node are utilized to construct a Social Congestion Metric (SCM). In the forwarding process, messages are forwarded to the nodes with higher SCM. When the congestion occurs, the node calculates the social links of itself with every message's destination node, and then drops the message with minimum social link rather than random dropping. Simulation results show that in the acceptable range of delay tolerance, the proposed algorithm improves the delivery probability, decreases the dropping probability and reduces the overhead.

Due to the explosive increment of data in big data era, it is a challenging task to analyze and extract meaningful data for users. Data needs to be timely operated because of the time sensitivity, so it faces enormous pressure in storage and computing. To deal with the problem that it is hard to achieve valuable information from out-of-order streams over big data in short time, a model-matching algorithm based on improved BP (Back Propagation) is proposed. In the algorithm, the matching model is set dynamically. Information is extracted for users according to the order of data's arriving time. Furthermore, the algorithm parameters are automatically adjusted in the process of learning and matching. Accordingly, the responding speed of learning is accelerated and the time of matching reduces. In the simulation, a group of optimum parameters of improved BP are achieved by using self-adapting adjusting mechanism. The threshold (TH), connecting weight (CW) and learning rate (LR) are equal to 1.5, 3 and 1, respectively. We implement our model-matching algorithm on 10000 sets of out-of-order streams with these parameters. Results indicate that the proposed algorithm can obviously improve the accuracy and speed of matching and achieve better stability.

In petrochemical industries, one of the most concerned problems is the leaking of toxic gas. Once leaking occurs, the safety of equipments located in production site is greatly threatened, thereby affecting surrounding environment. In order to solve this problem, it is necessary to predict the possible location of leak points from sensors which are located in gas pipe. On the other hand, data from sensors of petrochemical industries need to be timely operated because of time sensitivity, and it is hard to achieve associated information from sensors located in production site. To this end, an OLA-IBP (Online Learning Algorithm based on Improved Back Propagation) is proposed. The adaptive structure of this algorithm is settled online. Meanwhile, real-time data streams are parallelly processed according to arriving time in input layer. Simulation results show that OLA-IBP can efficiently improve learning time and accuracy rate. Finally, the adaptability of OLA-IBP is verified in leak points prediction of petrochemical equipments from processed data.

Big Data is changing this world at a surprising speed, and MapReduce plays a critical role in finding insights in Big Data. However, to efficiently extract insights from Big Data, performance optimization of MapReduce applications is a challenging task. To facilitate the full-system optimization of MapReduce applications, we propose a correlation-based performance analysis approach to efficiently identify critical outliers. The basic intuition is that critical outliers are key to the overall performance and they can only be accurately identified by correlating different phases, tasks and resources. Based on the proposed approach, we further implement a correlation-based performance analysis tool, called Sonata. It can efficiently identify critical outliers, and then, recommend optimization suggestions for practitioners based on embedded rules. Since the performance overhead is key to the applicability of a performance tool, we conduct experiments to demonstrate that Sonata is a practical tool with less than 5% overhead and good scalability. To demonstrate the effectiveness of Sonata, we share several cases during the performance tuning of IBM Platform SymphonyTM with the help of Sonata.

Due to the unpredictability of continuous data in distributed applications, it is hard for system to deal with data explosion in limited time. As a result, traditional static data storage technology fails to meet the demands for real-time data processing. To improve processing ability, many parallel processing structures are proposed, which brings up the problem that how the parallel machines can be scheduled to maximize their efficiency. Accordingly, a dynamic assignment scheduling algorithm for stream computing is proposed and a stream query graph is built to calculate the weight of every edge. The edge with the minimum weight is selected to send tuples. Simulation results show that the proper number of the logic machines could dramatically reduce system response time. Furthermore, system context switching is reduced by increasing the number of tuples sent every time.

Virtualization has become an important technology that is used across many platforms, particularly servers, to increase utilization, multi-tenancy and security. Virtualization introduces additional overhead that often relates to memory management, interrupt handling and hypervisor mode switching. Among those, memory management and translation lookaside buffer (TLB) management have been shown to have a significant impact on the performance of systems. Two principal mechanisms for TLB management exist in today's systems, namely software and hardware managed TLBs. In this paper, we analyze and quantify the overhead of a pure software virtualization that is implemented over a software managed TLB. We then describe our design of hardware extensions to support virtualization in systems with software managed TLBs to remove the most dominant overheads. These extensions were implemented in the Power embedded A2 core, which is used in the PowerEN and in the Blue Gene/Q processors. They were used to implement a KVM port. We evaluate each of these hardware extensions to determine their overall contributions to performance and efficiency. Collectively these extensions demonstrate an average improvement of 232% over a pure software implementation.

MapReduce plays an critical role in finding insights in Big Data. The performance optimization of MapReduce programs is challenging because it requires a comprehensive understanding of the whole system including both hardware layers (processors, storages, networks and etc), and software stacks (operating systems, JVM, runtime, applications and etc). However, most of the existing performance tuning and optimization are based on empirical and heuristic attempts. It remains a blank on how to build a systematical framework which breaks the boundary of multiple layers for performance optimization. In this paper, we propose a performance evaluation framework by correlating performance metrics from different layers, which provides insights to efficiently pinpoint the performance issue. This framework is composed of a series of predefined patterns. Each pattern indicates one or more potential issues. The behavior of a MapReduce program is mapped to the corresponding resource utilization. The framework provides a holistic approach which allows users at different levels of experience to conduct MapReduce program performance optimization. We use Terasort benchmark running on a 10-node Power7R2 cluster as a real case to show how this framework improves the performance. By this framework, we finally get the Terasort result improved from 47 mins to less than 8 mins. In addition to the best practice on performance tuning, several key findings are summarized as valuable workload analysis for JVM, MapReduce runtime and application design.

This paper presents an improved routing algorithm based on the social link awareness. In this algorithm, multiple social features of the nodes' behaviors are utilized to quantify the nodes pairs' social links. The social links of the nodes pairs are computed based on their encounter history. These social links can be used to construct the friendship communities of the nodes. The intra-community and inter-community forwarding mechanisms are implemented to raise the successful delivery ratio with low overhead and decrease the transmission delay. Simulation results show that the proposed algorithm shortens the routing delay and the overhead, and increases the successful delivery ratio, thereby improving the routing efficiency.

In many computing domains, hardware accelerators can improve throughput and lower power consumption, instead of executing functionally equivalent software on the general-purpose micro-processors cores. While hardware accelerators often are stateless, network processing exemplifies the need for stateful hardware acceleration. The packet oriented streaming nature of current networks enables data processing as soon as packets arrive rather than when the data of the whole network flow is available. Due to the concurrence of many flows, an accelerator must maintain and switch contexts between many states of the various accelerated streams embodied in the flows, which increases overhead associated with acceleration. We propose and evaluate dynamic reordering of requests of different accelerated streams in a hybrid on-chip/memory based request queue in order to reduce the associated overhead.

The transistor density of microprocessors continues to increase as technology scales. Microprocessors designers have taken advantage of the increased transistors by integrating a significant number of cores onto a single die. However, a large number of cores are met with diminishing returns due to software and hardware scalability issues and hence designers have started integrating on-chip special-purpose logic units (i.e., accelerators) that were previously available as PCI-attached units. It is anticipated that more accelerators will be integrated on-chip due to the increasing abundance of transistors and the fact that not all logic can be powered at all times due to power budget limits. Thus, on-chip accelerator architectures deserve more attention from the research community. There is a wide spectrum of research opportunities for design and optimization of accelerators. This paper attempts to bring out some insights by studying the data access streams of on-chip accelerators that hopefully foster some future research in this area. Specifically, this paper uses a few simple case studies to show some of the common characteristics of the data streams introduced by on-chip accelerators, discusses challenges and opportunities in exploiting these characteristics to optimize the power and performance of accelerators, and then analyzes the effectiveness of some simple optimizing extensions proposed.

This paper presents two complementary techniques to manage the power consumption of large-scale systems with a packet-switched interconnection network. First, we propose Thrifty Interconnection Network (TIN), where the network links are activated and de-activated dynamically with little or no overhead by using inherent system events to timely trigger link activation or de-activation. Second, we propose Network Power Shifting (NPS) that dynamically shifts the power budget between the compute nodes and their corresponding network components. TIN activates and trains the links in the interconnection network, just-in-time before the network communication is about to happen, and thriftily puts them into a low-power mode when communication is finished, hence reducing unnecessary network power consumption. Furthermore, the compute nodes can absorb the extra power budget shifted from its attached network components and increase their processor frequency for higher performance with NPS. Our simulation results on a set of real-world workload traces show that TIN can achieve on average 60% network power reduction, with the support of only one low-power mode. When NPS is enabled, the two together can achieve 12% application performance improvement and 13% overall system energy reduction. Further performance improvement is possible if the compute nodes can speed up more and fully utilize the extra power budget reinvested from the thrifty network with more aggressive cooling support.

Heterogeneous collaborative networks have been ever-increasingly concerned due to the constant development of wireless networks. However, before employed in commercial applications, the secure charging should be solved; say, the charging systems with the guarantee of security are vital to support this architecture. Meanwhile, nodes’ non-cooperation behavior should be under control as well. Hence, a secure incentive-based charging solution for heterogeneous collaborative networks integrating cellular and MANET (Ad Hoc) is proposed, utilizing charging receipt to thwart non-reputation attacks. Theoretical verification shows that proposed scheme not only grants the existence of selfish nodes to meet their rational demand, but is robust enough to circumvent various active attacks. Finally, simulation analysis reveals the influence of the parameters in proposed scheme on routing stability and node cooperation in low overhead.

QoS provisioning in multi-hop IEEE 802.11 networks is very challenging due to the interference nature of wireless medium and the contention-based behavior among neighboring nodes. In such networks, one of the key questions for QoS support is: given a specific topology and traffic condition, how much bandwidth can be utilized along a path in the network without violating QoS demand of existing traffic? Considering that in general QoS-sensitive traffic has the well-controlled sending rate, one key observation is that the network unsaturated condition should be considered. Another observation is that, not only the interaction between the new traffic and the existing ones that can be sensed (by the new one), but also the interaction between the new traffic and the traffic that is hidden but can have influence upon the new one should be studied. Based upon the above observations, we propose an analytical model for multi-hop IEEE 802.11 networks to calculate how much bandwidth can be utilized along a path without violating the QoS requirements of existing traffic. A notion, "free channel time", which is the time allowed for a wireless link to transmit data, is introduced to analyze the path capacity. Simulation results demonstrate that our proposed analytical model can accurately predict the path capacity under various network conditions without breaking QoS demands of all existing traffic

we propose an analytical model for multi-hop IEEE 802.11 networks to calculate how much bandwidth can be utilized along a path without violating the QoS requirements of existing rate-controlled traffic flows. A notion, "free channel time", which is the time allowed for a wireless link to transmit data, is introduced to analyze the path capacity. To achieve the goal, the proposed model effectively characterizes the unsaturated traffic condition. It could also depict the interaction between the newly injected traffic and the hidden traffic that could have influence upon the new traffic. Simulation results demonstrate that our proposed analytical model can accurately predict the path capacity under various network conditions without breaking QoS demands of all existing traffic.

In this paper we study the problem of using the rate adaptation technique to achieve energy efficiency in an IEEE 802.11-based multi-hop network. Specifically, we formulate it as an optimization problem, i.e., minimizing the total transmission power over transmission data rates, subject to the traffic requirements of all the nodes in a multi-hop network. Interestingly, we can show that this problem is actually a well-known multiple-choice knapsack problem, which is proven to be an NP-hard problem. So, instead of finding an optimal solution, which is NP-hard, we seek a sub-optimal solution. Our key technique to attack this problem is distributed cooperative rate adaptation. Here, we promote node cooperation due to our observation that the inequality in non-cooperative channel contention among nodes caused by hidden terminal phenomenon in a multi-hop network tends to result in energy inefficiency. Under this design philosophy, we propose a distributed cooperative rate adaptation (CRA) scheme and prove that it converges. Simulation results show that our CRA scheme can reduce the power consumption up to 86% as compared to the existing (non-cooperative) algorithm.

With the proliferation of portable computing devices and ascending popularity of group-oriented computing, wireless ad hoc network multicasting remains a challenging research subject. While the virtual multicast backbone (VMB) structure is commonly used in current multicast protocols, this paper focuses on the construction of the optimal VMB with the fewest forwarding nodes to decrease overhead and cost, due to the scarce resource in ad hoc networks. Instead of the conventional Steiner tree model, the optimal shared VMB in ad hoc networks is modeled as the minimum Steiner dominating set (MSCDS) in unit-disk graphs (UDG), which is NP-hard. A performance evaluation of flooding for MSCDS is given and a one-hop algorithm is proposed with an approximation ratio of at most 10. To adapt various network scenarios, this paper further presents a fully distributed d-hop algorithm also with a constant approximation ratio, which organizes multicast nodes to form a hierarchical VMB. Based on the hierarchical structure, this paper proposes some approaches to maintain and update VMB, and gives a security framework to exclude malicious nodes from multicast groups. Simulation results show that the proposed algorithms perform very well.