An all-digital clock and data recovery (CDR) with a digital threshold decision updating technique for SFI-5 application is presented in this paper. The CDR updates its decision upon the phase error reaching a threshold value by examining the phase errors in the data bits within an examining window at the baud rate. High jitter tolerance performance is obtained and the phase acquisition can be achieved within one baud period. The proposed CDR is embodied with 900 transistors and the core CDR consumes 5 mW with 1.2 V supply at 2.5 Gb/s. Measured results verify the digital threshold decision technique and its low-complexity implementation for SFI-5 application.

A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-μm CMOS process, the recovered clock exhibits a peak-to-peak jitter of 60ps for a 2-Gb/s PRBS-7 data and a phase noise of −93.5 dBc/Hz at 1-MHz offset. The core circuit consumes 40 mW at 1.8-V supply and occupies an area of 0.3 mm2.

This paper presents the design of a fully integrated wide-band low phase noise quadrature LC-tank VCO and high-speed frequency divider in a standard 90nm CMOS technology. The LC oscillator has a differential core with complementary cross-coupled MOS devices. The oscillation frequency can be tuned from 31GHz-41GHz, with a control voltage between 0 and 1V. The quadrature VCO draws a maximum of 6.5mA current from a 1.2V supply. The divider core is formed with low voltage swing current mode logic (CML) structure, which enables high frequency operation at very low power dissipation. The divider exhibits very wide locking range from 4GHz-41GHz, and it has an input sensitivity of -31dBm at 30GHz. The divider core draws only 750μA from a 1.2V supply. Both circuits occupy a chip area of about 150 × 250μm2.

This paper discusses a methodology employed to create a tool that quantifies the effects of signal integrity limitations particularly for high-speed applications. The tool is based on a platform of routines which predict performance over high-speed links. It contains routines that optimize transmitter pre-emphasis and receiver equalization that lead to superior BER performance. The tool is qualified against Agilent's ADS simulator and correlated to measurements.

A clock and data recovery architecture for highspeed communication systems is proposed. Based on early-late method, the bang-bang phase and frequency detectors work in two modes: half-rate mode and quarter-rate mode, thus a large applicable data rate range is available. Simulated in a 0.18/spl mu/m CMOS technology, the circuit exhibits a peak-to-peak jitter of 48ps in the recovered quarter-rate clock with PRBS length of 2/sup 15/-1 at 6.25-Gb/s. The data is recovered and demultiplexed inherently. In quarter-rate mode, the power dissipation is 80mW from a 1.8V supply.

An eye detection technique to detect maximum vertical eye opening points for data recovery circuit (CDR) applications and the circuit implementation of an eye detector (ED) are reported in this paper. The ED samples the incoming data to generate the retimed data and produces an error signal indicating whether the sampling point leads or lags the maximum eye opening point, where the lowest BER is expected. The ED is implemented in CMOS 0.18/spl mu/m technology, and its feasibility is confirmed by transistor-level simulations.

A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18/spl mu/m CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34 FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50m W at a 1.8V supply.

32 kb/s adaptive differential pulse coded modulation (ADPCM) is a widely accepted high quality speech coding algorithm. Single chip devices exist for 32 kb/s ADPCM. This algorithm requires a relatively large bandwidth and does not perform exceptionally well in noisy wireless environments. The 16 kb/s low-delay code excited linear prediction (LD-CELP) coding algorithm does perform well in noisy environments and requires a reduced bandwidth. Through algorithm optimization and simulated verification of mixed analog and digital VLSI partitioning a single chip implementing the 16 kb/s LD-CELP voice coding algorithm will be possible. The performance of this coder chip will be comparable to the quality of 32 kb/s ADPCM. In this paper we propose the use of a link between Comdisco's SPW and Synopsis to determine the hardware related performance degradation and the technology/complexity related power dissipation and area parameters. It will both prove the concept of design and determine the VLSI implementation feasibility.>

The authors present a simulation study evaluating the performance of trellis-coded modulation with combined code/ISI sequence estimation for high bit rate (800 kb/s) transmission on subscriber loops. The receiver contains a fractionally spaced forward filter of a decision feedback equalizer (DFE) as a front end. This is shown to suppress phase synchronized crosstalk very effectively. The performance is further enhanced by the use of trellis code with a large number of states received with an M algorithm sequence-estimating receiver with a smaller number of states.>