A method for switch-level timing simulation of bipolar emitter-coupled-logic (ECL) circuits is presented. The approach is based on the development of a switch level model of the transistor and on the representation of the circuit by a switch-graph. The circuit is partitioned into subcircuits, and the symbolic logic expressions, which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions, are then generated. Timing information is computed using a new physical delay model based on device equations, transistor interconnection, input slew rate, and loading conditions. The delay model was derived on the basis of average branch current analysis and incorporates more than 15 delay-sensitive circuit and SPICE BJT model parameters. The use of a novel parametric correction scheme permits greater freedom to handle complex effects such as high-level injection, parasitic resistances, and interconnection delay. In addition, the dynamic fanout effects due to base leakage current are incorporated by a fanout collapsing technique.>

The approach discussed is based on the efficient integration of the analog simulator with an analytic digital macromodel via the mixed A/D circuit partitioning, error and timestep control, and latency checking schemes. While maintaining accuracy constraints at every timepoint, this approach efficiently decouples the digital processing completely from the iteration-based analog algorithms. The waveform information of the digital subcircuits is provided at each timepoint by an accurate digital macromodel, which is derived analytically from the technology files. Therefore, advanced CMOS technologies can be incorporated easily. The proposed technique has been integrated into MISIM, a flexible CAE system for mixed A/D verification and rapid technology characterization. Several mixed A/D benchmark circuits have been tested and the results show that MISIM provides accurate mixed A/D simulation capability with a speed advantage of up to three orders of magnitude over SPICE3.>

The authors present an approach for the analytical timing model development of bipolar VLSI circuits. The approach is based on the development of the delay functions of three basic bipolar subcircuits. It is shown that accurate timing information for two high-speed digital circuit constructs, ECL (emitter coupled logic) and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The timing models have been shown to be accurate typically within 10% of SPICE's estimates with up to three orders of speedup for large-scale BJT (bipolar junction transistor) circuits.>