Demo Data from EDBT 2026 / reviewers in the wild / expert
Sergey Berezin
dblp:05/2504
· DBLP profile ↗
13ranked-venue papers
4as first author
1since 2021 · last 2025
0000-0002-8487-990XORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 9 · 2 first-authorTheory of computation · 8 · 2 first-authorArtificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Security and privacy · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Security and privacy of machine learning · 100% | |
| Artificial intelligence
1 paper |
Language models and text generation · 100% | |
| Software engineering, system software, and programming languages
2 papers |
Program verification · 86% Requirements engineering and software design · 14% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Security and privacy of machine learning
adversarial attack |
0.9 | 1 | 2025 | The TIP of the Iceberg: Revealing a Hidden Class of Task-in-Prompt Adversarial Attacks on LLMs · ACL (1) 2025 |
Security and privacy of machine learning › adversarial attack
jailbreak attack |
0.9 | 1 | 2025 | The TIP of the Iceberg: Revealing a Hidden Class of Task-in-Prompt Adversarial Attacks on LLMs · ACL (1) 2025 |
Natural language and speech › Language models and text generation
large language model |
0.3 | 1 | 2025 | The TIP of the Iceberg: Revealing a Hidden Class of Task-in-Prompt Adversarial Attacks on LLMs · ACL (1) 2025 |
Program verification › refinement
interface refinement |
0.0 | 1 | 2004 | Using Interface Refinement to Integrate Formal Verification into the Design Cycle · CAV 2004 |
Automated reasoning and model checking
satisfiability modulo theories |
0.0 | 1 | 2004 | CVC Lite: A New Implementation of the Cooperating Validity Checker Category B · CAV 2004 |
Requirements engineering and software design
design process |
0.0 | 1 | 2004 | Using Interface Refinement to Integrate Formal Verification into the Design Cycle · CAV 2004 |
Methods — techniques the papers use, named apart from their topics
prompt engineering · 1.7symbolic consistency testing · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | The TIP of the Iceberg: Revealing a Hidden Class of Task-in-Prompt Adversarial Attacks on LLMsabstractWe present a novel class of jailbreak adversarial attacks on LLMs, termed Task-in-Prompt (TIP) attacks. Our approach embeds sequence-to-sequence tasks (e.g., cipher decoding, riddles, code execution) into the model’s prompt to indirectly generate prohibited inputs. To systematically assess the effectiveness of these attacks, we introduce the PHRYGE benchmark. We demonstrate that our techniques successfully circumvent safeguards in six state-of-the-art language models, including GPT-4o and LLaMA 3.2. Our findings highlight critical weaknesses in current LLM safety alignment and underscore the urgent need for more sophisticated defence strategies. Sergey Berezin, Reza Farahbakhsh, Noël Crespi |
ACL (1) | 1 |
| 2017 | Bringing LTL Model Checking to Biologists
Zara Ahmed, David Benqué, Sergey Berezin, Anna Caroline E. Dahl, Jasmin Fisher, Benjamin A. Hall, Samin Ishtiaq, Jay Nanavati, Nir Piterman, Maik Riechert, Nikita Skoblov |
VMCAI | 3 |
| 2006 | A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware VerificationabstractWe introduce a heuristic for automatically checking the validity of first-order formulas of the form forallalphamexistbetanmiddot Psi(alpham,betan) that are encountered in inductive proofs of hardware correctness. The heuristic introduced in this paper is used to automatically check the validity of k-step induction formulas needed to verify hardware designs. The heuristic works on word-level designs that can have data and address buses of arbitrary widths. Our refinement heuristic relies on the idea of predicate instantiation introduced in (H. Abu-Haimed et al., 2003). The heuristic proves quantified formulas by the use of a validity checker, CVC (A. Stump et al., 2002), and a first-order theorem prover, Otter (W.W. McCune, 1994). Our heuristic can be used as a stand-alone technique to verify word-level designs or as a component in an interactive theorem prover. We show the effectiveness of this heuristic for hardware verification by verifying a number of hardware designs completely automatically. The large size of the quantified formulas encountered in these examples shows the effectiveness of our heuristic as a component of a theorem prover Husam Abu-Haimed, David L. Dill, Sergey Berezin |
FMCAD | 3 |
| 2004 | CVC Lite: A New Implementation of the Cooperating Validity Checker Category B
Clark W. Barrett, Sergey Berezin |
CAV | 2 |
| 2004 | Using Interface Refinement to Integrate Formal Verification into the Design Cycle
Jacob Chang, Sergey Berezin, David L. Dill |
CAV | 2 |
| 2003 | Strengthening Invariants by Symbolic Consistency Testing
Husam Abu-Haimed, Sergey Berezin, David L. Dill |
CAV | 2 |
| 2003 | An Online Proof-Producing Decision Procedure for Mixed-Integer Linear Arithmetic
Sergey Berezin, Vijay Ganesh 0001, David L. Dill |
TACAS | 1 |
| 2002 | Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods
Vijay Ganesh 0001, Sergey Berezin, David L. Dill |
FMCAD | 2 |
| 2002 | Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
Sergey Berezin, Edmund M. Clarke, Armin Biere, Yunshan Zhu |
Formal Methods Syst. Des. | 1 |
| 2001 | Incremental Verification by Abstraction
Yassine Lakhnech, Saddek Bensalem, Sergey Berezin, Sam Owre |
TACAS | 3 |
| 2001 | Athena: A Novel Approach to Efficient Automatic Security Protocol AnalysisabstractWe propose a new efficient automatic verification technique, Athena, for security protocol analysis. It uses a new efficient representation – our extension to the Strand Space Model, and utilizes techniques from both model checking and theorem proving approaches. Athena is fully automatic and is ab le to prove the correctness of many security protocols with arbitrary number of concurrent runs. The run time for a typical protocol from the literature, like the Needham–Schroeder protocol, is often a fraction of a second. Athena exploits several different techniques that enable it to analyze infinite sets of protocol runs and achieve such efficiency. Our extended Strand Space Model is a natural and efficient representation for the problem domain. The security properties are specified in a simple logic which permits both efficient proof search algorithms and has enough expressive power to specify interesting properties. The automatic proof search procedure borrows some efficient techniques from both model checking and theorem proving. We believe that it is the right combination of the new compact representation and all the techniques that actually makes Athena successful in fast and automatic verification of security protocols. Dawn Song, Sergey Berezin, Adrian Perrig |
J. Comput. Secur. | 2 |
| 1998 | Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yunshan Zhu |
FMCAD | 1 |
| 1998 | Model Checking: Historical Perspective and Example (Extended Abstract)
Edmund M. Clarke, Sergey Berezin |
TABLEAUX | 2 |