We demonstrate image segmentation processing by using a pre-calculating Ising memory implemented on a FPGA. Results show that the FPGA-based pre-calculating Ising memory can segment a prepared image in under 100μs.

Combinatorial optimization always contains many state search operations, which greatly reduce the efficiency of Von Neumann architecture. The Ising chip, expressing the behavior of magnetic spin systems with CMOS circuit, can efficiently support such operations. On the Ising chip, the state search can be carried out for all the spins in parallel. As the Ising chip is mainly SRAM based architecture, we propose Ising memory that enhancing the traditional memory with Ising ability, which can be easily integrated into Von Neumann architecture for both traditional data storage and efficiently solving combinatorial optimization problems. However, due to the non-memory logic for state search operations, directly integrating Ising ability into traditional memory would introduce additional 2× area overhead. To solve this problem, we propose pre-calculating structure to reduce the complexity of the state search circuit. Our proposal helps to reduce the non-memory area overhead to about 0.9× of the traditional memory. Moreover, we have physically designed an Ising memory and tested it with image segmentation problems. Our Ising memory can accelerate the segmenting processing by 26000× with only 0.0001× energy consumption. The experiment result shows that our Ising memory is a low cost method to enhance traditional memory with Ising ability for both data storage and solving combinatorial optimization problems.

Solving combinatorial optimization problems is a great challenge for Von Neumann-architecture computing. Although the Ising model could provide promising solutions for such problems, existing Ising chips, including superconductive, optical and CMOS-type circuit implementation, cannot meet the precision requirement of real-world combinatorial optimization applications. To facilitate the support for real-world applications, we propose three improvements over existing CMOS-type Ising chips: suitable narrow bit width memory cells with approximate multiply-adders, double random sources flipping method with cross random number generators and shared circuit design between adjacent spin nodes. With above improvements, we achieve high precision as well as maintaining the low cost characteristic of CMOS-type Ising chips. When searching the ground state of Ising models, our CMOS-type Ising chip can improve the precision to more than 99 percent over existing ones with about 93 percent precision. Moreover, its hardware cost is only 32 percent of the common implementation to achieve the same high precision. Specially, we have applied our Ising chip in image segmentation applications, a typical real-world application. The results show that, to find a segmentation with similar quality, our CMOS-type Ising chip can speed up the segmenting processing by 1900x with only 0.0170/00energy consumption compared with approximate algorithms operating on conventional computers.

This paper presents a brief overview of Schmitt Triggers and proposes a low voltage adjustable CMOS Schmitt trigger using body biasing technique. The voltage-feedback inverter with body control is employed to speed up the switching process, and control the intensity of the feedback. The proposed Schmitt trigger makes it particularly attractive for low-voltage high-speed applications. The CMOS Schmitt Trigger circuit has been designed using 40nm 1V CMOS technology and simulated using HSPICE with BSIM4 device models. Simulation results are presented.

In 3D NoC-based many-core systems, DRAM accesses behave differently due to their different communication distances and the latency gap of different DRAM accesses becomes bigger as the network size increases, which leads to unfair DRAM access performance among different nodes. This phenomenon may lead to high latencies for some DRAM accesses that become the performance bottleneck of the system. The paper addresses the DRAM access fairness problem in 3D NoC-based many-core systems by narrowing the latency difference of DRAM accesses as well as reducing the maximum latency. Firstly, the latency of a round-trip DRAM access is modeled and the factors causing DRAM access latency difference are discussed in detail. Secondly, the DRAM access fairness is further quantitatively analyzed through experiments. Thirdly, we propose to predict the network latency of round-trip DRAM accesses and use the predicted round-trip DRAM access time as the basis to prioritize the DRAM accesses in DRAM interfaces so that the DRAM accesses with potential high latencies can be transferred as early and fast as possible, thus achieving fair DRAM access. Experiments with synthetic and application workloads validate that our approach can achieve fair DRAM access and outperform the traditional First-Come-First-Serve (FCFS) scheduling policy and the scheduling policies proposed by reference [7] and [24] in terms of maximum latency, Latency Standard Deviation (LSD)1 and speedup. In the experiments, the maximum improvement of the maximum latency, LSD, and speedup are 12.8%, 6.57%, and 8.3% respectively. Besides, our proposal brings very small extra hardware overhead (<0.6%) in comparison to the three counterparts.

The efficacy of single instruction, multiple data (SIMD) architectures is limited when handling divergent control flows. This circumstance results in SIMD fragments using only a subset of the available lanes. We propose an iteration interleaving--based SIMD lane partition (IISLP) architecture that interleaves the execution of consecutive iterations and dynamically partitions SIMD lanes into branch paths with comparable execution time. The benefits are twofold: SIMD fragments under divergent branches can execute in parallel, and the pathology of fragment starvation can also be well eliminated. Our experiments show that IISLP doubles the performance of a baseline mechanism and provides a speedup of 28% versus instruction shuffle.

As the technology scales down, space radiation induced soft errors are becoming a critical issue for the reliability of Integrated Circuits (ICs). In this paper, we propose a novel layout-based Single-Event Transient (SET) injection approach to evaluate the Soft Error Rate (SER) of large combinational circuits in Complementary Metal-Oxide-Semiconductor (CMOS) bulk technology. We consider the effect of ion strike location on the SET pulse width in this approach. Heavy-ion experiments on two different inverter chains are conducted to verify this layout-based SET injection approach. The simulation and experiment results show that this approach can fairly reflect the SET pulse width distribution. Furthermore, we compare the soft error number calculated by our proposed layout-based approach with the normal SET injection approach, and illustrate the detailed circuit response obtained by our proposed approach.

The efficacy of widely used single instruction, multiple data architectures is often limited when handling divergent control flows and short vectors; both circumstances result in SIMD fragments that use only a subset of the available datapaths. This paper proposes a multiple SIMD, multiple data (MSMD) architecture with flexible SIMD datapaths that can be dynamically or statically repartitioned among multiple control flow paths, all executing simultaneously. The benefits are twofold: SIMD fragments resulting from divergent branches can execute in parallel, as can multiple kernels with short vectors. The resulting SIMD architecture can achieve the flexibility similar to a multiple instruction, multiple data architecture. We have both simulated the architecture and implemented a prototype. Our experiments with data-parallel benchmarks show that the architecture leads to 60% performance gains with an area overhead of only 3.06%.

SIMD architectures, comprising of both scalar and parallel units, have been widely used in media processors. To further improve the performance, much effort has been made to enhance the design of both units, while little attention has been placed on the relationship between the units. This paper demonstrates that a dynamic coupling mechanism, which can dynamically transform the scalar and parallel units between loosely and tightly coupled relationships, can achieve a better matching between existing SIMD architectures and media applications. The evaluation result shows that the dynamic coupling mechanism can achieve an average performance gain of 33.2% at an additional area cost of 4.57%.

This paper presents a novel heterogeneous multi-core Digital Signal Processor, named YHFT-QDSP, hosting one RISC CPU core and four VLIW DSP cores. The CPU core is responsible for task scheduling and management, while the DSP cores take charge of speeding up data processing. The YHFT-QDSP provides three kinds of interconnection communication. One is for inner-chip communication between the CPU core and the four DSP cores, the other two for both inner-chip and inter-chip communication amongst DSP cores. The YHFT-QDSP is implemented under SMIC®130nm LVT CMOS technology and can run [email protected] with 114.49 mm2die area.

The partitioning resources like pipelines and register files among clusters is proved to be an effective way to improve performance and scalability. However, improvement in scalability is limited by traditional instruction encoding schemes that quickly run out of bits in fixed-length instruction words to encode multiple register operands. Meanwhile, clustered processors may come at a cost of performance degradation, the major cause of which is the limited data locality arising from the lack of available registers and functional units. This paper introduces a highly scalable clustered architecture (HiSCA) to improve the scalability and performance of clustered processors. The pipeline of HiSCA provides high performance through in-order issuing, out-of-order execution and parallel but in-order commitment, while releasing instruction issuing from the heavy burden of dynamic scheduling. The hardware/software instruction encoding scheme of HiSCA splits instruction stream into chains of instructions (packs), and provides common information of instructions in the same packs in dedicated instruction words, thus reducing the total amount of information encoded in the instructions within the packs. HiSCA scales efficiently to 32 clusters with 1024 general purpose registers. Experiment results show that, for a 4-cluster and 8-issue configuration, HiSCA can achieve a 4.6% improvement in frequency with minimal hardware overhead, and an average of 13.3% performance speedup at the cost of 1.9% overhead to code size, compared with a traditional clustered processor with nearly the same hardware complexity.

This paper presents a Vector DMA Cache (VDC)scheme between the DMA bus and the Vector Memory (VM) in vector DSPs. The VDC can effectively reduce the VM access counts from the DMA requests and decrease the VM access conflicts. The VDC is specially designed for the DMA and not for the CPU, so it has some unique techniques which differ from the traditional CPU cache scheme. The main techniques of the VDC include the separate read cache and write cache, full line auto-updating policy and software cache coherence. Experimental results show the single-port VM plus the VDC can make programs reach more than 95% execution efficiency with only 44.1% and 51.4% chip area and power cost, compared with the dual-port VM scheme. And the single-port VM plus the VDC can reduce the execution cycles of programs by 3.7%~ 21.5% with only additional 7.3% and 6.3% chip area and power cost, compared with the pure single-port VM scheme.

The shuffle operation is one of the bottlenecks invector DSPs. The partitioning problem of the shuffle matrix will have a great effect on the design of the shuffle unit, when dealing with the small grain data shuffle using a smaller-sized crossbar. The traditional matrix block partitioning solution will bring much chip area, power consumption and critical path delay. This paper presents a new matrix partitioning solution: the odd-even partition, which has advantages in dealing with the data going into or out of the shuffle network. It can simplify the hardware design and improve the power efficacy of the shuffle unit in vector DSPs, compared with the matrix block partitioning solution. The principles and theorems of the odd-even partition are explained and proofed. The shuffle unit based on the odd-even partition is implemented. Some contrastive experimental results show that the odd-even partitioning solution can decrease the critical path delay by 12.2%~21.6%, reduce the hardware area by 20.9%~40.8% and cut down the power consumption by 23.5%~56.8%, compared with the matrix block partitioning solution.

This paper proposes a distributed and scalable hardware solution for efficient barrier synchronization management on many-core Network-on-Chips (NoCs). It includes two hardware modules, named Root Distributed and Scalable Barrier Synchronizer (Root DSBS) and Leaf Distributed and Scalable Barrier Synchronizer (Leaf DSBS). The Root DSBS is located in the central node, connecting to the processor core and the network interface. It provides a set of globally addressed barrier counters, sets the barrier and counts arriving "barrier acquire" requests, and releases the barrier and sends out "barrier release" acknowledgements once the barrier condition is satisfied. The Leaf DSBS is integrated into each router in the on-chip network. It is responsible for efficiently transmitting barrier synchronization related packets in the on-chip network to the Root DSBS. The Root DSBS in the central node and all Leaf DSBSs in routers cooperate together to accomplish barrier synchronization. Our solution has two salient features. One is called "Unicast Merging" - "barrier acquire" packets towards the same barrier are merged into one packet when they pass through the same router simultaneously. The purpose is to minimize the completion time of barrier acquiring by reducing the number of barrier synchronization related packets. The other is called "Broadcasting" - a "barrier release" packet is broadcasted to all synchronized nodes. Its object is to reduce area cost by avoiding storing synchronized node numbers as well as to minimize the completion time of barrier releasing by avoiding sending unicast "barrier release" packets. To evaluate the performance, we investigate hardware cost and employ both synthetic and application experiments. Synthesis and experiment results show that our distributed and scalable barrier synchronization obtains both area and performance advantage over the conventional barrier synchronization counterpart. The Root DSBS and Leaf DSBSs can run over 2GHz in TSMC®65nm technology with small area overhead. Our solution only costs a little completion time and generates well distributed and uniform network traffic. When the network size is 16×16, the application's performance improvement can achieve 24.60%.

Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We propose a microcoded controller as a hardware module in each node to connect the core, the local memory and the network. The controller is programmable where the DSM functions such as virtual-to-physical address translation, memory access and synchronization etc. are realized using microcode. To enable concurrent processing of memory requests from the local and remote cores, our controller features two mini-processors, one dealing with requests from the local core and the other from remote cores. Synthesis results suggest that the controller consumes 51k gates for the logic and can run up to 455 MHz in 130 nm technology. To evaluate its performance, we use synthetic and application workloads. Results show that, when the system size is scaled up, the delay overhead incurred by the controller may become less significant when compared with the network delay. In this way, the delay efficiency of our DSM solution is close to hardware solutions on average but still have all the flexibility of software solutions.

The emergence of large-scale chip multicore processors makes the on-chip parallel H.264/AVC encoder with high parallelism feasible. To reduce the data reload frequency, a hierarchical chip multi-core DSP platform with overall 64 DSP cores is designed to accommodate the computation/data-intensive H.264/AVC encoder. To increase parallelism, macro block level parallelism is exploited in this paper and wave front algorithm is utilized. Centralized shared memory in super nodes of this hierarchical DSP platform affords larger local space to hold the frequently used data and reduce bandwidth requirement. Subtask level parallelism within motion estimation, intra prediction and mode decision is further exploited to keep the DSP cores in a super node busy even only one macro block are assigned to a super node. Because of lack of available macro blocks in filling and emptying stages when encoding a frame, super nodes cannot be kept busy all the time and speedups of 13, 24, 26 and 49 are achieved for QCIF, SIF, CIF and HD sequences, respectively. To further improve the speedups and make best use of the processor resources, frame level parallelism should be exploited with carefully tuned memory allocation policy.

Motion estimation is the most computationally intensive part in a typical video encoder. This paper introduces a novel prediction method based on multiple search centers, which can efficiently improve the prediction accuracy. According to the amount and the magnitude of predictive search centers, the search range is dynamically adjusted in order to reduce the computational complexity. Based on multiple search centers prediction and dynamic search range adjustment, a new fast algorithm is proposed. Experimental results show that, on an average, the proposed algorithm gains similar rate-distortion performance to the original FFS, UMHexagonS and EPZS algorithms in H.264 reference software, while reducing about 97.4%, 63.0%, and 42.9% computational complexity respectively.

This paper presents a motion estimation coprocessor, supporting real-time high definition (HD) video coding. The proposed coprocessor employs a 2D data-reusing processing element array and a multi-standard cost comparator for distortion computation of variable size block. An instruction-set suitable for performing various ME algorithms is developed, providing the flexibility needed for different coding standards and various applications. In 0.13μm CMOS technology, the coprocessor is implemented with 303K gates at operating frequency of 550MHz. A performance comparison to the reference architectures reveals that only the proposed processor can provide the processing capacity for 1920×1080, 60 fps video sequences at 33×33 search window.

Due to its high-computational complexity and poor parallelism, the context-based adaptive binary arithmetic coder (CABAC) increasingly poses a bottleneck in the large-scale parallel video encoder like H.264 on a manycore platform. Motivated by the organization of the contexts models in CABAC, this letter presents a tri-thread parallel evolution of CABAC. The evolutional coder, which is named P3-CABAC, statically divides syntax elements into three predefined groups, each of which forms a parallel thread. Since the P3-CABAC is thread-level parallelizable and implementation-friendly for manycore processors, it presents a rational consideration for entropy coding in block-based video encoders in the manycore era.

In this paper, we propose a new digital signal processor architecture SPVA (Scalable Parallel VLIW architecture) for Software Defined Radio. The proposed architecture organizes function units into arithmetic units, and other units. The former are organized as SIMD clusters and the latter are organized as control clusters. Advantages of the proposed architecture include exploiting data parallelism through SIMD VLIW clusters, hiding memory latency through static schedule schemes, and exposing delay of branch and memory access to programmers and compilers. The experiments' results on critical benchmarks show that this architecture provides significant computation speedup compared to conventional VLIW DSP.

In this paper, a bit-rate estimation method is proposed, which could improve the performance of the H.264 encoder and avoid the strict data-dependencies of mode decision. After that, an efficient parallel algorithm for H.264 encoder with CABAC entropy coding is presented based on the Macro-Block Region Partition (MBRP) parallel method and the bit-rate estimation technique. Simulation results show that, the proposed parallel algorithm could improve the performance of H.264 encoder efficiently while maintaining the similar RD performance as JM 10.2.

To overcome the problems of traditional delay models, this paper uses a circuit simulator to calculate gate delay in static timing analysis. We analyzed the effect of multiple inputs simultaneous switching(MISS) on gate delay and proposed a MISS model to calculate the worst case gate delay. Based on this model, we developed the test waveform generation algorithms for complementary CMOS logic and pass transistor logic. By combining gate delay simulation with functional model extraction techniques of transistor circuits, we implemented a transistor level static timing analysis tool called SpiceTime. Results on ten IS-CAS85 benchmark circuits indicated that modules of significant size can be verified by SpiceTime with high precisions.

As the gap between processor speed and memory speed continues to increase, memory system becomes the bottleneck of the processor. Multiple instructions queuing for accessing main memory appear frequently, the regular changes of the access address stream often appear as well. Utilizing the characteristics of memory access, and considering different speeds of accessing DRAM in the hit, empty and conflict miss cases, this paper proposes a DRAM precharge policy based on address analysis. By collecting statistical information of address distribution of all the instructions waiting for accessing memory, and analyzing the regular changes of access addresses, this method can predict the access of each bank, make judgment of the appropriate moment to precharge each DRAM bank. The experimental results show that comparing with the commonly used close page and open page precharge policies, this method can decrease the cycles per instruction by 15.7% and 4.3% respectively.

Light detection and ranging is a relatively new technology, developed to complement traditional remote sensing technology. Digital aerial image provides reflectance information for land cover while LIDAR data provide more accurate geometrical information. There is much potential for fusing these two sources to achieve increased accuracy and utility for feature detection and classification. In order to assist Guangxi Electric Power Design Institute to improve their efficiency in power transmission line selection and design, field survey work, and reduce the cost, we have recently carried out the first power line project by using LIDAR and high resolution digital camera in China. The use of coloring LIDAR points by RGB of digital images makes it possible for obtaining high quality of in-room surveying, feature detection and classification. In addition, high quality and high resolution of DEM, DSM, DOM and visualization provides our customer not only with better selection and design of power line route, and reduced survey work, but also significant savings by 10 percent reduction of power line construction.

Current VLSI designs face a serious performance bottleneck due to reverse scaling of global interconnects as CMOS technology scales into VDSM regime. Interconnections techniques which decrease delay, power, and ensure signal integrity, play an important role in the growth of semiconductor industry into future generations. In this paper we present a novel hybrid insertion methodology for on-chip global interconnects. It takes advantage of repeaters and low-swing differential-signaling transceivers on driving long wires in different length, and optimally inserts them along the wires in order to decrease delay, power and gate area cost of interconnects. Simulation results using HSPICE for 0.18mum process showed that delay, power, delay-energy-product (EDP) and gate area cost were considerably decreased compared with other approaches available. Moreover, its computational technique is relatively easy and not limited to a specific low-swing differential-signaling transceiver. Therefore the methodology is very suitable for integration in EDA tool flow and beneficial for the reuse of low-swing differential-signaling transceivers

On-line control flow checking is able to detect wrong program execution paths caused by transient or intermittent hardware faults. Focusing on fault detection for YHFT-DSP, an embedded processor with very long instruction words (VLIW) structure, a hybrid control flow checking method (VLIW-CFC, V-CFC) based on signature monitoring is proposed. Signature instructions are designed for transmitting the redundancy information stored in signature and they are executed in unoccupied instruction slots to minimize the overhead of processor performance. Instruction signature is obtained by compressing instruction codes in a basic block, and it guarantees the execution integrality and correctness of this block. Branch signature is obtained from the program control flow graph (CFG) and dynamic offset signature instructions (DOSI), and it guarantees the correct execution sequences of multiple blocks. V-CFC with the two signatures is able to check control flow errors including execution sequences and bit flips of instruction codes. V-CFC reaches the high error-detection coverage, low performance loss and hardware costs, and it is well suited for embedded systems.

In this paper, we present a lookup table based model for delay and power estimation of low-swing interconnects: LSIEM. It can be used during high-level design planning, synthesis, and simulation of interconnect-centric VDSM designs. LSIEM is an accurate and efficient high-level estimation model. It has been tested on a wide range of parameters and shown to have over 90% accuracy with respect to HSPICE simulation results.