Low-complexity detection schemes are studied for additive white Gaussian noise channels with an unknown and unbounded offset constant over each memory read. Detectors based on the Pearson distance are analyzed, and a new lower bound on the word error rate of Modified Pearson (MP) detection is derived. Three novel detectors are proposed: the Simplified Pearson (SP), the Ultra-Simplified Pearson (USP), and the Adjusted-Threshold (AT) detectors. The USP and AT detectors are designed to be robust against destructive readings. The proposed schemes are particularly suited for memory systems employing ramp-reading architectures. The analysis demonstrates that the proposed detectors achieve competitive error-rate performance with significantly reduced complexity compared to MP detection.

This work investigates the error performance of detection schemes based on the minimum Pearson distance in the context of additive white Gaussian noise channels with unknown and unbounded offset, constant throughout each channel use. We derive a lower bound on the word error rate under modified Pearson (MP) detection. Additionally, we introduce a new and low-complexity detection strategy, namely the Simplified Pearson (SP) detector. We analyze and compare the error performance of the SP detector with that of the MP detector.

We propose the Active Compute Memory (ACM), a near-memory-processing architecture capable of performing key–value sort directly in the DRAM. In the ACM architecture, sort is merely the writing of data into memory with one addressing protocol (perspective) and reading it back with different perspective. The first perspective is conventional, based on the data address; the second perspective is the sorted order. The ACM requires additional tables to store the meta-data and moderate control logic enhancements that can be implemented directly in the DRAM silicon. By these modest enhancements to DRAM, ACM exploits the parallelism inherently available in the row buffer to enable sort with$O(n)$complexity. This leads to an order of magnitude improvement in ACM performance and energy compared to conventional$O(n\log{}n)$CPU-centric sort algorithms. The ACM also shows superior performance compared to other near-memory sort accelerators. This is because the ACM processing is done near the row buffer and it exploits much lower memory access latency, higher bandwidth and wider parallel processing. The sort operation covered in this paper is just an example of an address management operation that can be efficiently implemented directly in the DRAM silicon. We release as an open source the simulation infrastructure for the ACM performance and energy modeling. We would encourage the community to use it, adapt it to other PIM proposals, and share their own evaluations.

Today's mobile devices are equipped with sophis-ticated chain-of-trust mechanisms, able to successfully mitigate tampering of critical software components. However, this tech-nology, on the one hand, hinders the permanence of malware, thus raising the complexity for developing rootkits. On the other hand, the freedom of the end-user is limited. In fact, with all the security features enabled, one could not run any privileged code without it being signed by the Original Equipment Manufacturer; modifying any component of the root partition would cause a device read error and small modifications could be even rolled back automatically. Original Equipment Manufacturers typically provide mechanisms to (partially) disable these security features. However, they usually require two conditions: every unlock request must be approved by them, e.g. for warranty implications; secondly, to preserve the device security level, each time a security feature is disabled, the user data must be completely erased. We analyze several bootloader related vulnerabilities which allow to bypass these two requirements by exploiting design and implementation flaws in smartphones from different vendors. We then propose a novel architecture for secure device status storage and management. Our proposal relies only on commodity hardware features, which can be found on most mobile platforms. Furthermore, differently from many commercial implementations, we do not consider the storage device firmware as trusted, this makes our attack surface smaller than all of the examined alternatives.

Emerging non-volatile memories (NVMs) have the potential to change the memory-storage hierarchy in computing devices, and even to replace DRAM as main memories. In fact NVMs, beside offering byte-addressability and data persistence, promise better scalability and higher capacity than DRAM. However, from a security point of view, the persistent nature of emerging memories provides a larger time window to exfiltrate data from a device with respect to current DRAM-based main memories, and NVMs have in general lower write endurance than DRAM, thus requiring wear-out conscious encryption schemes. In this work we propose an architectural solution to secure non-volatile emerging memories, providing confidentiality, integrity and authenticity to the entire set of data, addresses and commands. Our solution relies on securing and authenticating the entire information transport between the host controller and the memory, enabling the storage of cleartext data inside the NVM. Such an approach allows to retain the advantage of differential write strategies without forsaking security. We validate our proposed architecture through the simulation of a set of software benchmarks on an embedded architecture, employing the gem5 trace-based architectural simulator.

Emerging memory technologies (like PCM, MRAM and 3D XPoint) can make data storage as fast as the rest of the system. But to cope with the reliability targets of storage applications, error correcting codes (ECCs) able to correct many errors might be needed anyway. Hierarchical codes, ECCs enabling two levels of correction, can be good candidates to satisfy these reliability targets, without impacting (on average) the low-latency characteristics of these technologies. In particular, an Ultra-Fast (UF) ECC can be used as first trial as long as it is able to flag its failures with high probability and low latency. In this paper we design an UF-ECC able to produce a check for incorrect decoding with probability lower than the typical target uncorrectable bit-error rate (UBER) of storage applications (e.g. 1e-15) and with a latency comparable with the UF-ECC correction process.

High-performance storage class memories could benefit from a fast decoding error correcting code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore, we propose an architecture for fast decoding of double and triple ECCs. In our architecture, any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular, the error locator polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here, we describe a gate-level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation.

The logical structure of a formal theory of general chemistry, where the properties of all molecules are deduced from those of the constituting atoms and bonds (whose properties are assigned a priori), has been constructed. This theory, however, admits the material world as a model ("the theory represents the reality") only if its mathematical structure is based on fuzzy arithmetics. In this way fuzzy logic enters as the basic element of foundational theory like chemistry, rather than simply a tool to manage poorly defined situations.

The paper studies the implementation feasibility of a VLS (virtual lambda sensor) by a TSK (Takagi, Sugeno, Kang) singleton FIS (fuzzy inference system). Such a sensor could be used in a model based EMS (engine management system) for trade gasoline engines. The FIS design target is to obtain a system with a fixed data representation (i.e., 10 bit) and a limited number of inputs, outputs, rules and membership.

After demonstrating adequately the usefulness of evolutionary multiobjective optimization (EMO) algorithms in finding multiple Pareto-optimal solutions for static multiobjective optimization problems, there is now a growing need for solving dynamic multiobjective optimization problems in a similar manner. In this paper, we focus on addressing this issue by developing a number of test problems and by suggesting a baseline algorithm. Since in a dynamic multiobjective optimization problem, the resulting Pareto-optimal set is expected to change with time (or, iteration of the optimization process), a suite of five test problems offering different patterns of such changes and different difficulties in tracking the dynamic Pareto-optimal front by a multiobjective optimization algorithm is presented. Moreover, a simple example of a dynamic multiobjective optimization problem arising from a dynamic control loop is presented. An extension to a previously proposed direction-based search method is proposed for solving such problems and tested on the proposed test problems. The test problems introduced in this paper should encourage researchers interested in multiobjective optimization and dynamic optimization problems to develop more efficient algorithms in the near future.

When dealing with many-objectives optimization problems, the concepts of Pareto-optimality and Pareto-dominance are often inefficient in modeling and simulating human decision making. This leads to an unpractical size for the set of Pareto-optimal (PO) solutions, and an additional selection criteria among solutions is usually arbitrarily considered. In the paper, different fuzzy-based definitions of optimality and dominated solutions, being nonpreference based, are introduced and tested on analytical test cases, in order to show their validity and nearness to human decision making. Based on this definitions, different subsets of PO solution set can be computed using simple and clear information provided by the decision maker and using a parameter value ranging from zero to one. When the value of the above parameter is zero, the introduced definitions coincide with classical Pareto-optimality and dominance. When the parameter value is increased, different subset of PO solutions can be obtained corresponding to higher degrees of optimality.

Although many authors have proposed constraints on membership functions for automatic optimization processes, formal definitions of these constraints are usually not well connected with the theory of partitions in many-valued and fuzzy logic. Our aim here is to derive these constraints from the theory of partitions in MV-logic, and to analyze the concept of refinement of a partition.

An approach for modeling chaotic dynamics is proposed. It is based on a linguistic description of chaotic phenomena, that can be easily related to a fuzzy system design. This approach allows building chaotic generators by means of few fuzzy sets and using a small number of fuzzy rules, It is also possible to create chaotic signals with assigned characteristics (e.g., Lyapunov exponents). Fuzzy descriptions of well-known discrete chaotic maps are therefore introduced, denoting an improved robustness to parameter changes.