In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for power grid analysis rely on a model of representing the transistor network as a current source. The disadvantage of the above model is that the drain capacitance of the PMOS transistors which are already on is not modeled. The drain capacitance of the PMOS transistors which are on, act much like a decoupling capacitance in the power grid. By ignoring the drain capacitance, the voltage drop predicted is pessimistic. This implies that a designer is likely to overestimate the amount of decoupling capacitance needed. In our proposed model, we model the transistor network as a simple switch in series with a RC circuit. The presence of switches leads to a non-constant conductance matrix. So, the switch is modeled behaviorally to make the conductance matrix a constant in presence of switches. The resulting conductance matrix is a M-matrix thus making it amenable to linear algebraic methods presented in the literature. The proposed model is nearly as accurate as the SPICE model in predicting the voltage drop. We demonstrate that the current source model of the transistor network has an error of about 10% in predicting the voltage drop. The proposed model offers the middle ground between the accuracy of SPICE simulation and the speed of the current source model. The proposed model is 20--30x faster than SPICE. It also reduces the size of the decoupling capacitance by 2--10x in comparison with the methods presented in the literature.

A quick literature survey revealed that many researchers have and continue to work on automatic test pattern generation for analog and mixed-signal circuits and systems, however, very few if any have addressed the problem of test set size. This paper presents a novel test set compaction algorithm which takes a generated test set and maximally reduces the number of test vectors required while maximizing the fault coverage. Results show that 58.33% reduction can be achieved. Smaller test set implies lower total test time and long test times have been identified as one of the bottlenecks in analog and mixed-signal test.

In this paper, we present methods for constructing optimal tests to detect structural faults in analog integrated circuits in the presence of process variation. The analog test determination problem is formulated as selecting an optimal subset from an initial large set of tests with optimality criteria defined in terms of fault coverage and fault separation on a given fault set. The process variation may be represented either deterministically by box constraints or statistically as random variables. Each of these representations require different methods for computing the detectabilities. In the deterministic case, the detectability measures are computed by a combination of analytical and numerical optimization techniques. Such an approach helps reduce the number of simulations by up to three times over traditional Monte Carlo methods. This approach produces more compact test sets compared to a linear sensitivity analysis while being closer in accuracy to the Monte Carlo method. In the statistical case, the detectability measures are computed as separation distances between the good and faulty distributions. These distributions represented nonparametrically are generated by traditional Monte Carlo techniques. Once the deterministic or statistical detectabilities are computed for the entire test set, a test compaction step is performed which is a covering problem. On solving this covering problem eve get a test set with optimal fault coverage and fault separation.

In this work we present a behavioral fault simulation technique for mixed-signal ICs, wherein a robust function approximation method namely regression splines are applied to automatically extract behavioral block parameters. The use of these robust high-level functions enables true behavioral fault simulation while preserving the statistical dependence on the process tolerance. We demonstrate significant speed-up over traditional Monte Carlo methods for two typical mixed-signal circuits, a sigma-delta modulator and a PLL.

In this paper we present an approach to construct dynamic test signals for analog circuits. Using the integral measure for characterizing time-domain signals, we extend the minmax formulation of the static test problem to the dynamic case. A sub-optimal solution strategy, similar to dynamic programming methods is used to construct the test waveforms. The approach presented here may be used to construct input signals for an on-chip test scheme or for the selection of an external stimulus applied through an arbitrary waveform generator.